mtd: denali: detect the number of banks

Not all configurations of the Denali controller support 4 banks. The controller can support between 1 and 16 banks. Detect this from the design features register. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

mtd: denali: detect the number of banks
Not all configurations of the Denali controller support 4 banks. The controller can support between 1 and 16 banks. Detect this from the design features register. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Jamie Iles · David Woodhouse
1 parent 9589bf5bed
Showing 2 changed files with 21 additions and 9 deletions Side-by-side Diff
drivers/mtd/nand/denali.c
drivers/mtd/nand/denali.h
@@ -178,11 +178,11 @@
 	dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
 		       __FILE__, __LINE__, __func__);
  
-	for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
+	for (i = 0 ; i < denali->max_banks; i++)
 		iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
 		denali->flash_reg + INTR_STATUS(i));
  
-	for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
+	for (i = 0 ; i < denali->max_banks; i++) {
 		iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
 		while (!(ioread32(denali->flash_reg +
 				INTR_STATUS(i)) &
@@ -194,7 +194,7 @@
 			"NAND Reset operation timed out on bank %d\n", i);
 	}
  
-	for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
+	for (i = 0; i < denali->max_banks; i++)
 		iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
 			denali->flash_reg + INTR_STATUS(i));
  
  
@@ -405,11 +405,11 @@
  */
 static void find_valid_banks(struct denali_nand_info *denali)
 {
-	uint32_t id[LLD_MAX_FLASH_BANKS];
+	uint32_t id[denali->max_banks];
 	int i;
  
 	denali->total_used_banks = 1;
-	for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < denali->max_banks; i++) {
 		index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
 		index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
 		index_addr_read_data(denali,
@@ -445,6 +445,17 @@
 		"denali->total_used_banks: %d\n", denali->total_used_banks);
 }
  
+/*
+ * Use the configuration feature register to determine the maximum number of
+ * banks that the hardware supports.
+ */
+static void detect_max_banks(struct denali_nand_info *denali)
+{
+	uint32_t features = ioread32(denali->flash_reg + FEATURES);
+
+	denali->max_banks = 2 << (features & FEATURES__N_BANKS);
+}
+
 static void detect_partition_feature(struct denali_nand_info *denali)
 {
 	/* For MRST platform, denali->fwblks represent the
@@ -562,7 +573,7 @@
 	int_mask = DENALI_IRQ_ALL;
  
 	/* Clear all status bits */
-	for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i)
+	for (i = 0; i < denali->max_banks; ++i)
 		iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
  
 	denali_irq_enable(denali, int_mask);
@@ -579,7 +590,7 @@
 {
 	int i;
  
-	for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i)
+	for (i = 0; i < denali->max_banks; ++i)
 		iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
 }
  
@@ -1345,6 +1356,7 @@
 	/* Should set value for these registers when init */
 	iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
 	iowrite32(1, denali->flash_reg + ECC_ENABLE);
+	detect_max_banks(denali);
 	denali_nand_timing_set(denali);
 	denali_irq_init(denali);
 }
@@ -1522,7 +1534,7 @@
 	/* scan for NAND devices attached to the controller
 	 * this is the first stage in a two step process to register
 	 * with the nand subsystem */
-	if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
+	if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
 		ret = -ENXIO;
 		goto failed_req_irq;
 	}
@@ -454,7 +454,6 @@
 #define READ_WRITE_ENABLE_HIGH_COUNT    22
  
 #define ECC_SECTOR_SIZE     512
-#define LLD_MAX_FLASH_BANKS     4
  
 #define DENALI_BUF_SIZE		(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
  
@@ -494,6 +493,7 @@
 	uint32_t totalblks;
 	uint32_t blksperchip;
 	uint32_t bbtskipbytes;
+	uint32_t max_banks;
 };
  
 #endif /*_LLD_NAND_*/
...	...	@@ -178,11 +178,11 @@
178	178	dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
179	179	__FILE__, __LINE__, __func__);
180	180
181		- for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
	181	+ for (i = 0 ; i < denali->max_banks; i++)
182	182	iowrite32(INTR_STATUS__RST_COMP \| INTR_STATUS__TIME_OUT,
183	183	denali->flash_reg + INTR_STATUS(i));
184	184
185		- for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
	185	+ for (i = 0 ; i < denali->max_banks; i++) {
186	186	iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
187	187	while (!(ioread32(denali->flash_reg +
188	188	INTR_STATUS(i)) &
...	...	@@ -194,7 +194,7 @@
194	194	"NAND Reset operation timed out on bank %d\n", i);
195	195	}
196	196
197		- for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
	197	+ for (i = 0; i < denali->max_banks; i++)
198	198	iowrite32(INTR_STATUS__RST_COMP \| INTR_STATUS__TIME_OUT,
199	199	denali->flash_reg + INTR_STATUS(i));
200	200
201	201
...	...	@@ -405,11 +405,11 @@
405	405	*/
406	406	static void find_valid_banks(struct denali_nand_info *denali)
407	407	{
408		- uint32_t id[LLD_MAX_FLASH_BANKS];
	408	+ uint32_t id[denali->max_banks];
409	409	int i;
410	410
411	411	denali->total_used_banks = 1;
412		- for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
	412	+ for (i = 0; i < denali->max_banks; i++) {
413	413	index_addr(denali, (uint32_t)(MODE_11 \| (i << 24) \| 0), 0x90);
414	414	index_addr(denali, (uint32_t)(MODE_11 \| (i << 24) \| 1), 0);
415	415	index_addr_read_data(denali,
...	...	@@ -445,6 +445,17 @@
445	445	"denali->total_used_banks: %d\n", denali->total_used_banks);
446	446	}
447	447
	448	+/*
	449	+ * Use the configuration feature register to determine the maximum number of
	450	+ * banks that the hardware supports.
	451	+ */
	452	+static void detect_max_banks(struct denali_nand_info *denali)
	453	+{
	454	+ uint32_t features = ioread32(denali->flash_reg + FEATURES);
	455	+
	456	+ denali->max_banks = 2 << (features & FEATURES__N_BANKS);
	457	+}
	458	+
448	459	static void detect_partition_feature(struct denali_nand_info *denali)
449	460	{
450	461	/* For MRST platform, denali->fwblks represent the
...	...	@@ -562,7 +573,7 @@
562	573	int_mask = DENALI_IRQ_ALL;
563	574
564	575	/* Clear all status bits */
565		- for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i)
	576	+ for (i = 0; i < denali->max_banks; ++i)
566	577	iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
567	578
568	579	denali_irq_enable(denali, int_mask);
...	...	@@ -579,7 +590,7 @@
579	590	{
580	591	int i;
581	592
582		- for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i)
	593	+ for (i = 0; i < denali->max_banks; ++i)
583	594	iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
584	595	}
585	596
...	...	@@ -1345,6 +1356,7 @@
1345	1356	/* Should set value for these registers when init */
1346	1357	iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1347	1358	iowrite32(1, denali->flash_reg + ECC_ENABLE);
	1359	+ detect_max_banks(denali);
1348	1360	denali_nand_timing_set(denali);
1349	1361	denali_irq_init(denali);
1350	1362	}
...	...	@@ -1522,7 +1534,7 @@
1522	1534	/* scan for NAND devices attached to the controller
1523	1535	* this is the first stage in a two step process to register
1524	1536	* with the nand subsystem */
1525		- if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
	1537	+ if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
1526	1538	ret = -ENXIO;
1527	1539	goto failed_req_irq;
1528	1540	}
...	...	@@ -454,7 +454,6 @@
454	454	#define READ_WRITE_ENABLE_HIGH_COUNT 22
455	455
456	456	#define ECC_SECTOR_SIZE 512
457		-#define LLD_MAX_FLASH_BANKS 4
458	457
459	458	#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
460	459
...	...	@@ -494,6 +493,7 @@
494	493	uint32_t totalblks;
495	494	uint32_t blksperchip;
496	495	uint32_t bbtskipbytes;
	496	+ uint32_t max_banks;
497	497	};
498	498
499	499	#endif /_LLD_NAND_/