firewire: normalize STATE_CLEAR/SET CSR access interface

Push the maintenance of STATE_CLEAR/SET.abdicate down into the card driver. This way, the read/write_csr_reg driver method works uniformly across all CSR offsets. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>

firewire: normalize STATE_CLEAR/SET CSR access interface
Push the maintenance of STATE_CLEAR/SET.abdicate down into the card driver. This way, the read/write_csr_reg driver method works uniformly across all CSR offsets. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Stefan Richter
1 parent db3c9cc105
Showing 5 changed files with 30 additions and 40 deletions Side-by-side Diff
drivers/firewire/core-topology.c
drivers/firewire/core-transaction.c
drivers/firewire/core.h
drivers/firewire/ohci.c
include/linux/firewire.h
@@ -524,7 +524,7 @@
 }
  
 void fw_core_handle_bus_reset(struct fw_card *card, int node_id, int generation,
-			      int self_id_count, u32 *self_ids)
+			      int self_id_count, u32 *self_ids, bool bm_abdicate)
 {
 	struct fw_node *local_node;
 	unsigned long flags;
@@ -552,8 +552,7 @@
 	smp_wmb();
 	card->generation = generation;
 	card->reset_jiffies = jiffies;
-	card->bm_abdicate = card->csr_abdicate;
-	card->csr_abdicate = false;
+	card->bm_abdicate = bm_abdicate;
 	fw_schedule_bm_work(card, 0);
  
 	local_node = build_tree(card, self_ids, self_id_count);
@@ -982,20 +982,6 @@
 	{ .start = CSR_REGISTER_BASE,
 	  .end   = CSR_REGISTER_BASE | CSR_CONFIG_ROM, };
  
-static u32 read_state_register(struct fw_card *card)
-{
-	u32 value;
-
-	/* Bit 8 (cmstr): */
-	value = card->driver->read_csr_reg(card, CSR_STATE_CLEAR);
-
-	/* Bit 10 (abdicate): */
-	if (card->csr_abdicate)
-		value |= CSR_STATE_BIT_ABDICATE;
-
-	return value;
-}
-
 static void update_split_timeout(struct fw_card *card)
 {
 	unsigned int cycles;
  
  
  
  
  
@@ -1021,29 +1007,25 @@
  
 	switch (reg) {
 	case CSR_STATE_CLEAR:
-		if (tcode == TCODE_READ_QUADLET_REQUEST) {
-			*data = cpu_to_be32(read_state_register(card));
-		} else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
+		if (tcode == TCODE_READ_QUADLET_REQUEST)
+			*data = cpu_to_be32(card->driver->
+					read_csr_reg(card, CSR_STATE_CLEAR));
+		else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
 			card->driver->write_csr_reg(card, CSR_STATE_CLEAR,
 						    be32_to_cpu(*data));
-			if (*data & cpu_to_be32(CSR_STATE_BIT_ABDICATE))
-				card->csr_abdicate = false;
-		} else {
+		else
 			rcode = RCODE_TYPE_ERROR;
-		}
 		break;
  
 	case CSR_STATE_SET:
-		if (tcode == TCODE_READ_QUADLET_REQUEST) {
-			*data = cpu_to_be32(read_state_register(card));
-		} else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
+		if (tcode == TCODE_READ_QUADLET_REQUEST)
+			*data = cpu_to_be32(card->driver->
+					read_csr_reg(card, CSR_STATE_SET));
+		else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
 			card->driver->write_csr_reg(card, CSR_STATE_SET,
 						    be32_to_cpu(*data));
-			if (*data & cpu_to_be32(CSR_STATE_BIT_ABDICATE))
-				card->csr_abdicate = true;
-		} else {
+		else
 			rcode = RCODE_TYPE_ERROR;
-		}
 		break;
  
 	case CSR_NODE_IDS:
@@ -1063,7 +1045,8 @@
  
 	case CSR_RESET_START:
 		if (tcode == TCODE_WRITE_QUADLET_REQUEST)
-			card->csr_abdicate = false;
+			card->driver->write_csr_reg(card, CSR_STATE_CLEAR,
+						    CSR_STATE_BIT_ABDICATE);
 		else
 			rcode = RCODE_TYPE_ERROR;
 		break;
@@ -196,7 +196,7 @@
 }
  
 void fw_core_handle_bus_reset(struct fw_card *card, int node_id,
-			      int generation, int self_id_count, u32 *self_ids);
+	int generation, int self_id_count, u32 *self_ids, bool bm_abdicate);
 void fw_destroy_nodes(struct fw_card *card);
  
 /*
@@ -174,6 +174,7 @@
 	unsigned int pri_req_max;
 	u32 bus_time;
 	bool is_root;
+	bool csr_state_setclear_abdicate;
  
 	/*
 	 * Spinlock for accessing fw_ohci data.  Never call out of
@@ -1529,7 +1530,9 @@
 		    self_id_count, ohci->self_id_buffer);
  
 	fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
-				 self_id_count, ohci->self_id_buffer);
+				 self_id_count, ohci->self_id_buffer,
+				 ohci->csr_state_setclear_abdicate);
+	ohci->csr_state_setclear_abdicate = false;
 }
  
 static irqreturn_t irq_handler(int irq, void *data)
  
  
  
@@ -2032,14 +2035,17 @@
 	switch (csr_offset) {
 	case CSR_STATE_CLEAR:
 	case CSR_STATE_SET:
-		/* the controller driver handles only the cmstr bit */
 		if (ohci->is_root &&
 		    (reg_read(ohci, OHCI1394_LinkControlSet) &
 		     OHCI1394_LinkControl_cycleMaster))
-			return CSR_STATE_BIT_CMSTR;
+			value = CSR_STATE_BIT_CMSTR;
 		else
-			return 0;
+			value = 0;
+		if (ohci->csr_state_setclear_abdicate)
+			value |= CSR_STATE_BIT_ABDICATE;
  
+		return value;
+
 	case CSR_NODE_IDS:
 		return reg_read(ohci, OHCI1394_NodeID) << 16;
  
  
@@ -2078,12 +2084,13 @@
  
 	switch (csr_offset) {
 	case CSR_STATE_CLEAR:
-		/* the controller driver handles only the cmstr bit */
 		if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
 			reg_write(ohci, OHCI1394_LinkControlClear,
 				  OHCI1394_LinkControl_cycleMaster);
 			flush_writes(ohci);
 		}
+		if (value & CSR_STATE_BIT_ABDICATE)
+			ohci->csr_state_setclear_abdicate = false;
 		break;
  
 	case CSR_STATE_SET:
@@ -2092,6 +2099,8 @@
 				  OHCI1394_LinkControl_cycleMaster);
 			flush_writes(ohci);
 		}
+		if (value & CSR_STATE_BIT_ABDICATE)
+			ohci->csr_state_setclear_abdicate = true;
 		break;
  
 	case CSR_NODE_IDS:
@@ -119,8 +119,7 @@
 	int bm_retries;
 	int bm_generation;
 	__be32 bm_transaction_data[2];
-	bool bm_abdicate; /* value of csr_abdicate before last bus reset */
-	bool csr_abdicate; /* visible in CSR STATE_CLEAR/SET registers */
+	bool bm_abdicate;
  
 	bool priority_budget_implemented;	/* controller feature */
 	bool broadcast_channel_auto_allocated;	/* controller feature */
...	...	@@ -524,7 +524,7 @@
524	524	}
525	525
526	526	void fw_core_handle_bus_reset(struct fw_card *card, int node_id, int generation,
527		- int self_id_count, u32 *self_ids)
	527	+ int self_id_count, u32 *self_ids, bool bm_abdicate)
528	528	{
529	529	struct fw_node *local_node;
530	530	unsigned long flags;
...	...	@@ -552,8 +552,7 @@
552	552	smp_wmb();
553	553	card->generation = generation;
554	554	card->reset_jiffies = jiffies;
555		- card->bm_abdicate = card->csr_abdicate;
556		- card->csr_abdicate = false;
	555	+ card->bm_abdicate = bm_abdicate;
557	556	fw_schedule_bm_work(card, 0);
558	557
559	558	local_node = build_tree(card, self_ids, self_id_count);
...	...	@@ -982,20 +982,6 @@
982	982	{ .start = CSR_REGISTER_BASE,
983	983	.end = CSR_REGISTER_BASE \| CSR_CONFIG_ROM, };
984	984
985		-static u32 read_state_register(struct fw_card *card)
986		-{
987		- u32 value;
988		-
989		- /* Bit 8 (cmstr): */
990		- value = card->driver->read_csr_reg(card, CSR_STATE_CLEAR);
991		-
992		- /* Bit 10 (abdicate): */
993		- if (card->csr_abdicate)
994		- value \|= CSR_STATE_BIT_ABDICATE;
995		-
996		- return value;
997		-}
998		-
999	985	static void update_split_timeout(struct fw_card *card)
1000	986	{
1001	987	unsigned int cycles;
1002	988
1003	989
1004	990
1005	991
1006	992
...	...	@@ -1021,29 +1007,25 @@
1021	1007
1022	1008	switch (reg) {
1023	1009	case CSR_STATE_CLEAR:
1024		- if (tcode == TCODE_READ_QUADLET_REQUEST) {
1025		- *data = cpu_to_be32(read_state_register(card));
1026		- } else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
	1010	+ if (tcode == TCODE_READ_QUADLET_REQUEST)
	1011	+ *data = cpu_to_be32(card->driver->
	1012	+ read_csr_reg(card, CSR_STATE_CLEAR));
	1013	+ else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
1027	1014	card->driver->write_csr_reg(card, CSR_STATE_CLEAR,
1028	1015	be32_to_cpu(*data));
1029		- if (*data & cpu_to_be32(CSR_STATE_BIT_ABDICATE))
1030		- card->csr_abdicate = false;
1031		- } else {
	1016	+ else
1032	1017	rcode = RCODE_TYPE_ERROR;
1033		- }
1034	1018	break;
1035	1019
1036	1020	case CSR_STATE_SET:
1037		- if (tcode == TCODE_READ_QUADLET_REQUEST) {
1038		- *data = cpu_to_be32(read_state_register(card));
1039		- } else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
	1021	+ if (tcode == TCODE_READ_QUADLET_REQUEST)
	1022	+ *data = cpu_to_be32(card->driver->
	1023	+ read_csr_reg(card, CSR_STATE_SET));
	1024	+ else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
1040	1025	card->driver->write_csr_reg(card, CSR_STATE_SET,
1041	1026	be32_to_cpu(*data));
1042		- if (*data & cpu_to_be32(CSR_STATE_BIT_ABDICATE))
1043		- card->csr_abdicate = true;
1044		- } else {
	1027	+ else
1045	1028	rcode = RCODE_TYPE_ERROR;
1046		- }
1047	1029	break;
1048	1030
1049	1031	case CSR_NODE_IDS:
...	...	@@ -1063,7 +1045,8 @@
1063	1045
1064	1046	case CSR_RESET_START:
1065	1047	if (tcode == TCODE_WRITE_QUADLET_REQUEST)
1066		- card->csr_abdicate = false;
	1048	+ card->driver->write_csr_reg(card, CSR_STATE_CLEAR,
	1049	+ CSR_STATE_BIT_ABDICATE);
1067	1050	else
1068	1051	rcode = RCODE_TYPE_ERROR;
1069	1052	break;
...	...	@@ -196,7 +196,7 @@
196	196	}
197	197
198	198	void fw_core_handle_bus_reset(struct fw_card *card, int node_id,
199		- int generation, int self_id_count, u32 *self_ids);
	199	+ int generation, int self_id_count, u32 *self_ids, bool bm_abdicate);
200	200	void fw_destroy_nodes(struct fw_card *card);
201	201
202	202	/*
...	...	@@ -174,6 +174,7 @@
174	174	unsigned int pri_req_max;
175	175	u32 bus_time;
176	176	bool is_root;
	177	+ bool csr_state_setclear_abdicate;
177	178
178	179	/*
179	180	* Spinlock for accessing fw_ohci data. Never call out of
...	...	@@ -1529,7 +1530,9 @@
1529	1530	self_id_count, ohci->self_id_buffer);
1530	1531
1531	1532	fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1532		- self_id_count, ohci->self_id_buffer);
	1533	+ self_id_count, ohci->self_id_buffer,
	1534	+ ohci->csr_state_setclear_abdicate);
	1535	+ ohci->csr_state_setclear_abdicate = false;
1533	1536	}
1534	1537
1535	1538	static irqreturn_t irq_handler(int irq, void *data)
1536	1539
1537	1540
1538	1541
...	...	@@ -2032,14 +2035,17 @@
2032	2035	switch (csr_offset) {
2033	2036	case CSR_STATE_CLEAR:
2034	2037	case CSR_STATE_SET:
2035		- /* the controller driver handles only the cmstr bit */
2036	2038	if (ohci->is_root &&
2037	2039	(reg_read(ohci, OHCI1394_LinkControlSet) &
2038	2040	OHCI1394_LinkControl_cycleMaster))
2039		- return CSR_STATE_BIT_CMSTR;
	2041	+ value = CSR_STATE_BIT_CMSTR;
2040	2042	else
2041		- return 0;
	2043	+ value = 0;
	2044	+ if (ohci->csr_state_setclear_abdicate)
	2045	+ value \|= CSR_STATE_BIT_ABDICATE;
2042	2046
	2047	+ return value;
	2048	+
2043	2049	case CSR_NODE_IDS:
2044	2050	return reg_read(ohci, OHCI1394_NodeID) << 16;
2045	2051
2046	2052
...	...	@@ -2078,12 +2084,13 @@
2078	2084
2079	2085	switch (csr_offset) {
2080	2086	case CSR_STATE_CLEAR:
2081		- /* the controller driver handles only the cmstr bit */
2082	2087	if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2083	2088	reg_write(ohci, OHCI1394_LinkControlClear,
2084	2089	OHCI1394_LinkControl_cycleMaster);
2085	2090	flush_writes(ohci);
2086	2091	}
	2092	+ if (value & CSR_STATE_BIT_ABDICATE)
	2093	+ ohci->csr_state_setclear_abdicate = false;
2087	2094	break;
2088	2095
2089	2096	case CSR_STATE_SET:
...	...	@@ -2092,6 +2099,8 @@
2092	2099	OHCI1394_LinkControl_cycleMaster);
2093	2100	flush_writes(ohci);
2094	2101	}
	2102	+ if (value & CSR_STATE_BIT_ABDICATE)
	2103	+ ohci->csr_state_setclear_abdicate = true;
2095	2104	break;
2096	2105
2097	2106	case CSR_NODE_IDS:
...	...	@@ -119,8 +119,7 @@
119	119	int bm_retries;
120	120	int bm_generation;
121	121	__be32 bm_transaction_data[2];
122		- bool bm_abdicate; /* value of csr_abdicate before last bus reset */
123		- bool csr_abdicate; /* visible in CSR STATE_CLEAR/SET registers */
	122	+ bool bm_abdicate;
124	123
125	124	bool priority_budget_implemented; /* controller feature */
126	125	bool broadcast_channel_auto_allocated; /* controller feature */