Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit c8de83624c33b2f5dc6ba497477fc2019b547949

Authored by Guenter Roeck
Committed by Guenter Roeck
1 parent 8c103696fa
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

hwmon: (dme1737) Fix checkpatch issues 

Fixed:
WARNING: braces {} are not necessary for any arm of this statement
WARNING: braces {} are not necessary for single statement blocks
WARNING: simple_strtol is obsolete, use kstrtol instead

Modify multi-line comments to follow Documentation/CodingStyle.

Also: s/#define^I/#define /

Not fixed (false positive):
ERROR: Macros with multiple statements should be enclosed in a do - while loop

Cc: Juerg Haefliger <juergh@gmail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Showing 1 changed file with 290 additions and 216 deletions Side-by-side Diff

drivers/hwmon/dme1737.c
Diff comments   View file @ c8de836
Changes suppressed. Click to show
... ... @@ -82,12 +82,12 @@
82 82 * --------------------------------------------------------------------- */
83 83  
84 84 /* Voltages (in) numbered 0-7 (ix) */
85   -#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
  85 +#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
86 86 (ix) < 7 ? 0x94 + (ix) : \
87 87 0x1f)
88   -#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
  88 +#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
89 89 : 0x91 + (ix) * 2)
90   -#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
  90 +#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
91 91 : 0x92 + (ix) * 2)
92 92  
93 93 /* Temperatures (temp) numbered 0-2 (ix) */
94 94  
... ... @@ -97,14 +97,16 @@
97 97 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
98 98 : 0x1c + (ix))
99 99  
100   -/* Voltage and temperature LSBs
  100 +/*
  101 + * Voltage and temperature LSBs
101 102 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
102 103 * IN_TEMP_LSB(0) = [in5, in6]
103 104 * IN_TEMP_LSB(1) = [temp3, temp1]
104 105 * IN_TEMP_LSB(2) = [in4, temp2]
105 106 * IN_TEMP_LSB(3) = [in3, in0]
106 107 * IN_TEMP_LSB(4) = [in2, in1]
107   - * IN_TEMP_LSB(5) = [res, in7] */
  108 + * IN_TEMP_LSB(5) = [res, in7]
  109 + */
108 110 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
109 111 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
110 112 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
111 113  
112 114  
113 115  
114 116  
115 117  
... ... @@ -127,24 +129,30 @@
127 129 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
128 130 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
129 131 : 0xa3 + (ix))
130   -/* The layout of the ramp rate registers is different from the other pwm
  132 +/*
  133 + * The layout of the ramp rate registers is different from the other pwm
131 134 * registers. The bits for the 3 PWMs are stored in 2 registers:
132 135 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
133   - * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */
  136 + * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
  137 + */
134 138 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
135 139  
136 140 /* Thermal zones 0-2 */
137 141 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
138 142 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
139   -/* The layout of the hysteresis registers is different from the other zone
  143 +/*
  144 + * The layout of the hysteresis registers is different from the other zone
140 145 * registers. The bits for the 3 zones are stored in 2 registers:
141 146 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
142   - * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */
  147 + * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES]
  148 + */
143 149 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
144 150  
145   -/* Alarm registers and bit mapping
  151 +/*
  152 + * Alarm registers and bit mapping
146 153 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
147   - * alarm value [0, ALARM3, ALARM2, ALARM1]. */
  154 + * alarm value [0, ALARM3, ALARM2, ALARM1].
  155 + */
148 156 #define DME1737_REG_ALARM1 0x41
149 157 #define DME1737_REG_ALARM2 0x42
150 158 #define DME1737_REG_ALARM3 0x83
151 159  
... ... @@ -257,9 +265,11 @@
257 265 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
258 266 IN_NOMINAL_DME1737)
259 267  
260   -/* Voltage input
  268 +/*
  269 + * Voltage input
261 270 * Voltage inputs have 16 bits resolution, limit values have 8 bits
262   - * resolution. */
  271 + * resolution.
  272 + */
263 273 static inline int IN_FROM_REG(int reg, int nominal, int res)
264 274 {
265 275 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
266 276  
... ... @@ -270,10 +280,12 @@
270 280 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255);
271 281 }
272 282  
273   -/* Temperature input
  283 +/*
  284 + * Temperature input
274 285 * The register values represent temperatures in 2's complement notation from
275 286 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
276   - * values have 8 bits resolution. */
  287 + * values have 8 bits resolution.
  288 + */
277 289 static inline int TEMP_FROM_REG(int reg, int res)
278 290 {
279 291 return (reg * 1000) >> (res - 8);
280 292  
281 293  
282 294  
... ... @@ -300,18 +312,19 @@
300 312 int i;
301 313  
302 314 for (i = 15; i > 0; i--) {
303   - if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) {
  315 + if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
304 316 break;
305   - }
306 317 }
307 318  
308 319 return (reg & 0x0f) | (i << 4);
309 320 }
310 321  
311   -/* Temperature hysteresis
  322 +/*
  323 + * Temperature hysteresis
312 324 * Register layout:
313 325 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
314   - * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] */
  326 + * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
  327 + */
315 328 static inline int TEMP_HYST_FROM_REG(int reg, int ix)
316 329 {
317 330 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
318 331  
319 332  
... ... @@ -327,11 +340,10 @@
327 340 /* Fan input RPM */
328 341 static inline int FAN_FROM_REG(int reg, int tpc)
329 342 {
330   - if (tpc) {
  343 + if (tpc)
331 344 return tpc * reg;
332   - } else {
  345 + else
333 346 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
334   - }
335 347 }
336 348  
337 349 static inline int FAN_TO_REG(int val, int tpc)
338 350  
339 351  
340 352  
... ... @@ -344,17 +356,21 @@
344 356 }
345 357 }
346 358  
347   -/* Fan TPC (tach pulse count)
  359 +/*
  360 + * Fan TPC (tach pulse count)
348 361 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
349   - * is configured in legacy (non-tpc) mode */
  362 + * is configured in legacy (non-tpc) mode
  363 + */
350 364 static inline int FAN_TPC_FROM_REG(int reg)
351 365 {
352 366 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
353 367 }
354 368  
355   -/* Fan type
  369 +/*
  370 + * Fan type
356 371 * The type of a fan is expressed in number of pulses-per-revolution that it
357   - * emits */
  372 + * emits
  373 + */
358 374 static inline int FAN_TYPE_FROM_REG(int reg)
359 375 {
360 376 int edge = (reg >> 1) & 0x03;
361 377  
... ... @@ -378,9 +394,8 @@
378 394 int i;
379 395  
380 396 for (i = 10; i > 0; i--) {
381   - if (reg == FAN_MAX[i]) {
  397 + if (reg == FAN_MAX[i])
382 398 break;
383   - }
384 399 }
385 400  
386 401 return 1000 + i * 500;
387 402  
388 403  
... ... @@ -391,15 +406,15 @@
391 406 int i;
392 407  
393 408 for (i = 10; i > 0; i--) {
394   - if (val > (1000 + (i - 1) * 500)) {
  409 + if (val > (1000 + (i - 1) * 500))
395 410 break;
396   - }
397 411 }
398 412  
399 413 return FAN_MAX[i];
400 414 }
401 415  
402   -/* PWM enable
  416 +/*
  417 + * PWM enable
403 418 * Register to enable mapping:
404 419 * 000: 2 fan on zone 1 auto
405 420 * 001: 2 fan on zone 2 auto
... ... @@ -408,7 +423,8 @@
408 423 * 100: -1 fan disabled
409 424 * 101: 2 fan on hottest of zones 2,3 auto
410 425 * 110: 2 fan on hottest of zones 1,2,3 auto
411   - * 111: 1 fan in manual mode */
  426 + * 111: 1 fan in manual mode
  427 + */
412 428 static inline int PWM_EN_FROM_REG(int reg)
413 429 {
414 430 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
... ... @@ -423,7 +439,8 @@
423 439 return (reg & 0x1f) | ((en & 0x07) << 5);
424 440 }
425 441  
426   -/* PWM auto channels zone
  442 +/*
  443 + * PWM auto channels zone
427 444 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
428 445 * corresponding to zone x+1):
429 446 * 000: 001 fan on zone 1 auto
... ... @@ -433,7 +450,8 @@
433 450 * 100: 000 fan disabled
434 451 * 101: 110 fan on hottest of zones 2,3 auto
435 452 * 110: 111 fan on hottest of zones 1,2,3 auto
436   - * 111: 000 fan in manual mode */
  453 + * 111: 000 fan in manual mode
  454 + */
437 455 static inline int PWM_ACZ_FROM_REG(int reg)
438 456 {
439 457 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
440 458  
441 459  
442 460  
... ... @@ -468,19 +486,20 @@
468 486 i = 11;
469 487 } else {
470 488 for (i = 9; i > 0; i--) {
471   - if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) {
  489 + if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
472 490 break;
473   - }
474 491 }
475 492 }
476 493  
477 494 return (reg & 0xf0) | i;
478 495 }
479 496  
480   -/* PWM ramp rate
  497 +/*
  498 + * PWM ramp rate
481 499 * Register layout:
482 500 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
483   - * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */
  501 + * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
  502 + */
484 503 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
485 504  
486 505 static inline int PWM_RR_FROM_REG(int reg, int ix)
487 506  
... ... @@ -495,9 +514,8 @@
495 514 int i;
496 515  
497 516 for (i = 0; i < 7; i++) {
498   - if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) {
  517 + if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
499 518 break;
500   - }
501 519 }
502 520  
503 521 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
504 522  
... ... @@ -516,9 +534,11 @@
516 534 return val ? reg | en : reg & ~en;
517 535 }
518 536  
519   -/* PWM min/off
  537 +/*
  538 + * PWM min/off
520 539 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
521   - * the register layout). */
  540 + * the register layout).
  541 + */
522 542 static inline int PWM_OFF_FROM_REG(int reg, int ix)
523 543 {
524 544 return (reg >> (ix + 5)) & 0x01;
525 545  
526 546  
... ... @@ -604,12 +624,13 @@
604 624  
605 625 /* In (voltage) registers */
606 626 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
607   - /* Voltage inputs are stored as 16 bit values even
  627 + /*
  628 + * Voltage inputs are stored as 16 bit values even
608 629 * though they have only 12 bits resolution. This is
609   - * to make it consistent with the temp inputs. */
610   - if (ix == 7 && !(data->has_features & HAS_IN7)) {
  630 + * to make it consistent with the temp inputs.
  631 + */
  632 + if (ix == 7 && !(data->has_features & HAS_IN7))
611 633 continue;
612   - }
613 634 data->in[ix] = dme1737_read(data,
614 635 DME1737_REG_IN(ix)) << 8;
615 636 data->in_min[ix] = dme1737_read(data,
616 637  
... ... @@ -620,11 +641,13 @@
620 641  
621 642 /* Temp registers */
622 643 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
623   - /* Temp inputs are stored as 16 bit values even
  644 + /*
  645 + * Temp inputs are stored as 16 bit values even
624 646 * though they have only 12 bits resolution. This is
625 647 * to take advantage of implicit conversions between
626 648 * register values (2's complement) and temp values
627   - * (signed decimal). */
  649 + * (signed decimal).
  650 + */
628 651 data->temp[ix] = dme1737_read(data,
629 652 DME1737_REG_TEMP(ix)) << 8;
630 653 data->temp_min[ix] = dme1737_read(data,
631 654  
632 655  
633 656  
634 657  
635 658  
... ... @@ -637,21 +660,21 @@
637 660 }
638 661 }
639 662  
640   - /* In and temp LSB registers
  663 + /*
  664 + * In and temp LSB registers
641 665 * The LSBs are latched when the MSBs are read, so the order in
642 666 * which the registers are read (MSB first, then LSB) is
643   - * important! */
  667 + * important!
  668 + */
644 669 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
645   - if (ix == 5 && !(data->has_features & HAS_IN7)) {
  670 + if (ix == 5 && !(data->has_features & HAS_IN7))
646 671 continue;
647   - }
648 672 lsb[ix] = dme1737_read(data,
649 673 DME1737_REG_IN_TEMP_LSB(ix));
650 674 }
651 675 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
652   - if (ix == 7 && !(data->has_features & HAS_IN7)) {
  676 + if (ix == 7 && !(data->has_features & HAS_IN7))
653 677 continue;
654   - }
655 678 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
656 679 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
657 680 }
658 681  
... ... @@ -662,11 +685,12 @@
662 685  
663 686 /* Fan registers */
664 687 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
665   - /* Skip reading registers if optional fans are not
666   - * present */
667   - if (!(data->has_features & HAS_FAN(ix))) {
  688 + /*
  689 + * Skip reading registers if optional fans are not
  690 + * present
  691 + */
  692 + if (!(data->has_features & HAS_FAN(ix)))
668 693 continue;
669   - }
670 694 data->fan[ix] = dme1737_read(data,
671 695 DME1737_REG_FAN(ix));
672 696 data->fan[ix] |= dme1737_read(data,
673 697  
... ... @@ -686,11 +710,12 @@
686 710  
687 711 /* PWM registers */
688 712 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
689   - /* Skip reading registers if optional PWMs are not
690   - * present */
691   - if (!(data->has_features & HAS_PWM(ix))) {
  713 + /*
  714 + * Skip reading registers if optional PWMs are not
  715 + * present
  716 + */
  717 + if (!(data->has_features & HAS_PWM(ix)))
692 718 continue;
693   - }
694 719 data->pwm[ix] = dme1737_read(data,
695 720 DME1737_REG_PWM(ix));
696 721 data->pwm_freq[ix] = dme1737_read(data,
697 722  
... ... @@ -711,9 +736,8 @@
711 736 /* Thermal zone registers */
712 737 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
713 738 /* Skip reading registers if zone3 is not present */
714   - if ((ix == 2) && !(data->has_features & HAS_ZONE3)) {
  739 + if ((ix == 2) && !(data->has_features & HAS_ZONE3))
715 740 continue;
716   - }
717 741 /* sch5127 zone2 registers are special */
718 742 if ((ix == 1) && (data->type == sch5127)) {
719 743 data->zone_low[1] = dme1737_read(data,
... ... @@ -737,8 +761,10 @@
737 761 /* Alarm registers */
738 762 data->alarms = dme1737_read(data,
739 763 DME1737_REG_ALARM1);
740   - /* Bit 7 tells us if the other alarm registers are non-zero and
741   - * therefore also need to be read */
  764 + /*
  765 + * Bit 7 tells us if the other alarm registers are non-zero and
  766 + * therefore also need to be read
  767 + */
742 768 if (data->alarms & 0x80) {
743 769 data->alarms |= dme1737_read(data,
744 770 DME1737_REG_ALARM2) << 8;
745 771  
746 772  
... ... @@ -746,22 +772,18 @@
746 772 DME1737_REG_ALARM3) << 16;
747 773 }
748 774  
749   - /* The ISA chips require explicit clearing of alarm bits.
  775 + /*
  776 + * The ISA chips require explicit clearing of alarm bits.
750 777 * Don't worry, an alarm will come back if the condition
751   - * that causes it still exists */
  778 + * that causes it still exists
  779 + */
752 780 if (!data->client) {
753   - if (data->alarms & 0xff0000) {
754   - dme1737_write(data, DME1737_REG_ALARM3,
755   - 0xff);
756   - }
757   - if (data->alarms & 0xff00) {
758   - dme1737_write(data, DME1737_REG_ALARM2,
759   - 0xff);
760   - }
761   - if (data->alarms & 0xff) {
762   - dme1737_write(data, DME1737_REG_ALARM1,
763   - 0xff);
764   - }
  781 + if (data->alarms & 0xff0000)
  782 + dme1737_write(data, DME1737_REG_ALARM3, 0xff);
  783 + if (data->alarms & 0xff00)
  784 + dme1737_write(data, DME1737_REG_ALARM2, 0xff);
  785 + if (data->alarms & 0xff)
  786 + dme1737_write(data, DME1737_REG_ALARM1, 0xff);
765 787 }
766 788  
767 789 data->last_update = jiffies;
768 790  
... ... @@ -822,8 +844,13 @@
822 844 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
823 845 int ix = sensor_attr_2->index;
824 846 int fn = sensor_attr_2->nr;
825   - long val = simple_strtol(buf, NULL, 10);
  847 + long val;
  848 + int err;
826 849  
  850 + err = kstrtol(buf, 10, &val);
  851 + if (err)
  852 + return err;
  853 +
827 854 mutex_lock(&data->update_lock);
828 855 switch (fn) {
829 856 case SYS_IN_MIN:
830 857  
... ... @@ -901,8 +928,13 @@
901 928 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
902 929 int ix = sensor_attr_2->index;
903 930 int fn = sensor_attr_2->nr;
904   - long val = simple_strtol(buf, NULL, 10);
  931 + long val;
  932 + int err;
905 933  
  934 + err = kstrtol(buf, 10, &val);
  935 + if (err)
  936 + return err;
  937 +
906 938 mutex_lock(&data->update_lock);
907 939 switch (fn) {
908 940 case SYS_TEMP_MIN:
909 941  
910 942  
... ... @@ -952,11 +984,10 @@
952 984 switch (fn) {
953 985 case SYS_ZONE_AUTO_CHANNELS_TEMP:
954 986 /* check config2 for non-standard temp-to-zone mapping */
955   - if ((ix == 1) && (data->config2 & 0x02)) {
  987 + if ((ix == 1) && (data->config2 & 0x02))
956 988 res = 4;
957   - } else {
  989 + else
958 990 res = 1 << ix;
959   - }
960 991 break;
961 992 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
962 993 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
963 994  
... ... @@ -989,8 +1020,13 @@
989 1020 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
990 1021 int ix = sensor_attr_2->index;
991 1022 int fn = sensor_attr_2->nr;
992   - long val = simple_strtol(buf, NULL, 10);
  1023 + long val;
  1024 + int err;
993 1025  
  1026 + err = kstrtol(buf, 10, &val);
  1027 + if (err)
  1028 + return err;
  1029 +
994 1030 mutex_lock(&data->update_lock);
995 1031 switch (fn) {
996 1032 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
... ... @@ -1014,8 +1050,10 @@
1014 1050 /* Refresh the cache */
1015 1051 data->zone_low[ix] = dme1737_read(data,
1016 1052 DME1737_REG_ZONE_LOW(ix));
1017   - /* Modify the temp range value (which is stored in the upper
1018   - * nibble of the pwm_freq register) */
  1053 + /*
  1054 + * Modify the temp range value (which is stored in the upper
  1055 + * nibble of the pwm_freq register)
  1056 + */
1019 1057 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1020 1058 TEMP_FROM_REG(data->zone_low[ix], 8),
1021 1059 dme1737_read(data,
1022 1060  
... ... @@ -1095,8 +1133,13 @@
1095 1133 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1096 1134 int ix = sensor_attr_2->index;
1097 1135 int fn = sensor_attr_2->nr;
1098   - long val = simple_strtol(buf, NULL, 10);
  1136 + long val;
  1137 + int err;
1099 1138  
  1139 + err = kstrtol(buf, 10, &val);
  1140 + if (err)
  1141 + return err;
  1142 +
1100 1143 mutex_lock(&data->update_lock);
1101 1144 switch (fn) {
1102 1145 case SYS_FAN_MIN:
1103 1146  
1104 1147  
1105 1148  
1106 1149  
1107 1150  
... ... @@ -1170,21 +1213,19 @@
1170 1213  
1171 1214 switch (fn) {
1172 1215 case SYS_PWM:
1173   - if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) {
  1216 + if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0)
1174 1217 res = 255;
1175   - } else {
  1218 + else
1176 1219 res = data->pwm[ix];
1177   - }
1178 1220 break;
1179 1221 case SYS_PWM_FREQ:
1180 1222 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1181 1223 break;
1182 1224 case SYS_PWM_ENABLE:
1183   - if (ix >= 3) {
  1225 + if (ix >= 3)
1184 1226 res = 1; /* pwm[5-6] hard-wired to manual mode */
1185   - } else {
  1227 + else
1186 1228 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
1187   - }
1188 1229 break;
1189 1230 case SYS_PWM_RAMP_RATE:
1190 1231 /* Only valid for pwm[1-3] */
1191 1232  
1192 1233  
1193 1234  
1194 1235  
1195 1236  
... ... @@ -1192,19 +1233,17 @@
1192 1233 break;
1193 1234 case SYS_PWM_AUTO_CHANNELS_ZONE:
1194 1235 /* Only valid for pwm[1-3] */
1195   - if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
  1236 + if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2)
1196 1237 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
1197   - } else {
  1238 + else
1198 1239 res = data->pwm_acz[ix];
1199   - }
1200 1240 break;
1201 1241 case SYS_PWM_AUTO_PWM_MIN:
1202 1242 /* Only valid for pwm[1-3] */
1203   - if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) {
  1243 + if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix))
1204 1244 res = data->pwm_min[ix];
1205   - } else {
  1245 + else
1206 1246 res = 0;
1207   - }
1208 1247 break;
1209 1248 case SYS_PWM_AUTO_POINT1_PWM:
1210 1249 /* Only valid for pwm[1-3] */
1211 1250  
... ... @@ -1233,8 +1272,13 @@
1233 1272 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1234 1273 int ix = sensor_attr_2->index;
1235 1274 int fn = sensor_attr_2->nr;
1236   - long val = simple_strtol(buf, NULL, 10);
  1275 + long val;
  1276 + int err;
1237 1277  
  1278 + err = kstrtol(buf, 10, &val);
  1279 + if (err)
  1280 + return err;
  1281 +
1238 1282 mutex_lock(&data->update_lock);
1239 1283 switch (fn) {
1240 1284 case SYS_PWM:
... ... @@ -1307,8 +1351,10 @@
1307 1351 /* Change permissions of pwm[ix] to read-only */
1308 1352 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1309 1353 S_IRUGO);
1310   - /* Turn on auto mode using the saved zone channel
1311   - * assignment */
  1354 + /*
  1355 + * Turn on auto mode using the saved zone channel
  1356 + * assignment
  1357 + */
1312 1358 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1313 1359 data->pwm_acz[ix],
1314 1360 data->pwm_config[ix]);
... ... @@ -1338,8 +1384,10 @@
1338 1384 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1339 1385 data->pwm_rr[ix > 0]);
1340 1386 }
1341   - /* Enable/disable the feature only if the associated PWM
1342   - * output is in automatic mode. */
  1387 + /*
  1388 + * Enable/disable the feature only if the associated PWM
  1389 + * output is in automatic mode.
  1390 + */
1343 1391 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1344 1392 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1345 1393 data->pwm_rr[ix > 0]);
1346 1394  
... ... @@ -1361,15 +1409,19 @@
1361 1409 data->pwm_config[ix] = dme1737_read(data,
1362 1410 DME1737_REG_PWM_CONFIG(ix));
1363 1411 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1364   - /* PWM is already in auto mode so update the temp
1365   - * channel assignment */
  1412 + /*
  1413 + * PWM is already in auto mode so update the temp
  1414 + * channel assignment
  1415 + */
1366 1416 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1367 1417 data->pwm_config[ix]);
1368 1418 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1369 1419 data->pwm_config[ix]);
1370 1420 } else {
1371   - /* PWM is not in auto mode so we save the temp
1372   - * channel assignment for later use */
  1421 + /*
  1422 + * PWM is not in auto mode so we save the temp
  1423 + * channel assignment for later use
  1424 + */
1373 1425 data->pwm_acz[ix] = val;
1374 1426 }
1375 1427 break;
1376 1428  
... ... @@ -1378,10 +1430,12 @@
1378 1430 /* Refresh the cache */
1379 1431 data->pwm_min[ix] = dme1737_read(data,
1380 1432 DME1737_REG_PWM_MIN(ix));
1381   - /* There are only 2 values supported for the auto_pwm_min
  1433 + /*
  1434 + * There are only 2 values supported for the auto_pwm_min
1382 1435 * value: 0 or auto_point1_pwm. So if the temperature drops
1383 1436 * below the auto_point1_temp_hyst value, the fan either turns
1384   - * off or runs at auto_point1_pwm duty-cycle. */
  1437 + * off or runs at auto_point1_pwm duty-cycle.
  1438 + */
1385 1439 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1386 1440 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
1387 1441 dme1737_read(data,
1388 1442  
... ... @@ -1426,8 +1480,13 @@
1426 1480 const char *buf, size_t count)
1427 1481 {
1428 1482 struct dme1737_data *data = dev_get_drvdata(dev);
1429   - long val = simple_strtol(buf, NULL, 10);
  1483 + long val;
  1484 + int err;
1430 1485  
  1486 + err = kstrtol(buf, 10, &val);
  1487 + if (err)
  1488 + return err;
  1489 +
1431 1490 data->vrm = val;
1432 1491 return count;
1433 1492 }
1434 1493  
... ... @@ -1586,10 +1645,12 @@
1586 1645 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1587 1646 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
1588 1647  
1589   -/* This struct holds all the attributes that are always present and need to be
  1648 +/*
  1649 + * This struct holds all the attributes that are always present and need to be
1590 1650 * created unconditionally. The attributes that need modification of their
1591 1651 * permissions are created read-only and write permissions are added or removed
1592   - * on the fly when required */
  1652 + * on the fly when required
  1653 + */
1593 1654 static struct attribute *dme1737_attr[] = {
1594 1655 /* Voltages */
1595 1656 &sensor_dev_attr_in0_input.dev_attr.attr,
1596 1657  
... ... @@ -1652,9 +1713,11 @@
1652 1713 .attrs = dme1737_attr,
1653 1714 };
1654 1715  
1655   -/* The following struct holds temp offset attributes, which are not available
  1716 +/*
  1717 + * The following struct holds temp offset attributes, which are not available
1656 1718 * in all chips. The following chips support them:
1657   - * DME1737, SCH311x */
  1719 + * DME1737, SCH311x
  1720 + */
1658 1721 static struct attribute *dme1737_temp_offset_attr[] = {
1659 1722 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1660 1723 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1661 1724  
... ... @@ -1666,9 +1729,11 @@
1666 1729 .attrs = dme1737_temp_offset_attr,
1667 1730 };
1668 1731  
1669   -/* The following struct holds VID related attributes, which are not available
  1732 +/*
  1733 + * The following struct holds VID related attributes, which are not available
1670 1734 * in all chips. The following chips support them:
1671   - * DME1737 */
  1735 + * DME1737
  1736 + */
1672 1737 static struct attribute *dme1737_vid_attr[] = {
1673 1738 &dev_attr_vrm.attr,
1674 1739 &dev_attr_cpu0_vid.attr,
1675 1740  
... ... @@ -1679,9 +1744,11 @@
1679 1744 .attrs = dme1737_vid_attr,
1680 1745 };
1681 1746  
1682   -/* The following struct holds temp zone 3 related attributes, which are not
  1747 +/*
  1748 + * The following struct holds temp zone 3 related attributes, which are not
1683 1749 * available in all chips. The following chips support them:
1684   - * DME1737, SCH311x, SCH5027 */
  1750 + * DME1737, SCH311x, SCH5027
  1751 + */
1685 1752 static struct attribute *dme1737_zone3_attr[] = {
1686 1753 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1687 1754 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1688 1755  
... ... @@ -1695,9 +1762,11 @@
1695 1762 };
1696 1763  
1697 1764  
1698   -/* The following struct holds temp zone hysteresis related attributes, which
  1765 +/*
  1766 + * The following struct holds temp zone hysteresis related attributes, which
1699 1767 * are not available in all chips. The following chips support them:
1700   - * DME1737, SCH311x */
  1768 + * DME1737, SCH311x
  1769 + */
1701 1770 static struct attribute *dme1737_zone_hyst_attr[] = {
1702 1771 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1703 1772 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1704 1773  
... ... @@ -1709,9 +1778,11 @@
1709 1778 .attrs = dme1737_zone_hyst_attr,
1710 1779 };
1711 1780  
1712   -/* The following struct holds voltage in7 related attributes, which
  1781 +/*
  1782 + * The following struct holds voltage in7 related attributes, which
1713 1783 * are not available in all chips. The following chips support them:
1714   - * SCH5127 */
  1784 + * SCH5127
  1785 + */
1715 1786 static struct attribute *dme1737_in7_attr[] = {
1716 1787 &sensor_dev_attr_in7_input.dev_attr.attr,
1717 1788 &sensor_dev_attr_in7_min.dev_attr.attr,
1718 1789  
... ... @@ -1724,9 +1795,11 @@
1724 1795 .attrs = dme1737_in7_attr,
1725 1796 };
1726 1797  
1727   -/* The following structs hold the PWM attributes, some of which are optional.
  1798 +/*
  1799 + * The following structs hold the PWM attributes, some of which are optional.
1728 1800 * Their creation depends on the chip configuration which is determined during
1729   - * module load. */
  1801 + * module load.
  1802 + */
1730 1803 static struct attribute *dme1737_pwm1_attr[] = {
1731 1804 &sensor_dev_attr_pwm1.dev_attr.attr,
1732 1805 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1733 1806  
1734 1807  
1735 1808  
... ... @@ -1779,18 +1852,22 @@
1779 1852 { .attrs = dme1737_pwm6_attr },
1780 1853 };
1781 1854  
1782   -/* The following struct holds auto PWM min attributes, which are not available
  1855 +/*
  1856 + * The following struct holds auto PWM min attributes, which are not available
1783 1857 * in all chips. Their creation depends on the chip type which is determined
1784   - * during module load. */
  1858 + * during module load.
  1859 + */
1785 1860 static struct attribute *dme1737_auto_pwm_min_attr[] = {
1786 1861 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1787 1862 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1788 1863 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1789 1864 };
1790 1865  
1791   -/* The following structs hold the fan attributes, some of which are optional.
  1866 +/*
  1867 + * The following structs hold the fan attributes, some of which are optional.
1792 1868 * Their creation depends on the chip configuration which is determined during
1793   - * module load. */
  1869 + * module load.
  1870 + */
1794 1871 static struct attribute *dme1737_fan1_attr[] = {
1795 1872 &sensor_dev_attr_fan1_input.dev_attr.attr,
1796 1873 &sensor_dev_attr_fan1_min.dev_attr.attr,
... ... @@ -1843,8 +1920,10 @@
1843 1920 { .attrs = dme1737_fan6_attr },
1844 1921 };
1845 1922  
1846   -/* The permissions of the following zone attributes are changed to read-
1847   - * writeable if the chip is *not* locked. Otherwise they stay read-only. */
  1923 +/*
  1924 + * The permissions of the following zone attributes are changed to read-
  1925 + * writeable if the chip is *not* locked. Otherwise they stay read-only.
  1926 + */
1848 1927 static struct attribute *dme1737_zone_chmod_attr[] = {
1849 1928 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1850 1929 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
... ... @@ -1860,8 +1939,10 @@
1860 1939 };
1861 1940  
1862 1941  
1863   -/* The permissions of the following zone 3 attributes are changed to read-
1864   - * writeable if the chip is *not* locked. Otherwise they stay read-only. */
  1942 +/*
  1943 + * The permissions of the following zone 3 attributes are changed to read-
  1944 + * writeable if the chip is *not* locked. Otherwise they stay read-only.
  1945 + */
1865 1946 static struct attribute *dme1737_zone3_chmod_attr[] = {
1866 1947 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1867 1948 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1868 1949  
... ... @@ -1873,9 +1954,11 @@
1873 1954 .attrs = dme1737_zone3_chmod_attr,
1874 1955 };
1875 1956  
1876   -/* The permissions of the following PWM attributes are changed to read-
  1957 +/*
  1958 + * The permissions of the following PWM attributes are changed to read-
1877 1959 * writeable if the chip is *not* locked and the respective PWM is available.
1878   - * Otherwise they stay read-only. */
  1960 + * Otherwise they stay read-only.
  1961 + */
1879 1962 static struct attribute *dme1737_pwm1_chmod_attr[] = {
1880 1963 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1881 1964 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
... ... @@ -1920,8 +2003,10 @@
1920 2003 { .attrs = dme1737_pwm6_chmod_attr },
1921 2004 };
1922 2005  
1923   -/* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
1924   - * chip is not locked. Otherwise they are read-only. */
  2006 +/*
  2007 + * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
  2008 + * chip is not locked. Otherwise they are read-only.
  2009 + */
1925 2010 static struct attribute *dme1737_pwm_chmod_attr[] = {
1926 2011 &sensor_dev_attr_pwm1.dev_attr.attr,
1927 2012 &sensor_dev_attr_pwm2.dev_attr.attr,
1928 2013  
... ... @@ -1975,9 +2060,8 @@
1975 2060 {
1976 2061 struct attribute **attr;
1977 2062  
1978   - for (attr = group->attrs; *attr; attr++) {
  2063 + for (attr = group->attrs; *attr; attr++)
1979 2064 dme1737_chmod_file(dev, *attr, mode);
1980   - }
1981 2065 }
1982 2066  
1983 2067 static void dme1737_remove_files(struct device *dev)
1984 2068  
1985 2069  
1986 2070  
1987 2071  
1988 2072  
1989 2073  
1990 2074  
... ... @@ -2003,26 +2087,20 @@
2003 2087 }
2004 2088 }
2005 2089  
2006   - if (data->has_features & HAS_TEMP_OFFSET) {
  2090 + if (data->has_features & HAS_TEMP_OFFSET)
2007 2091 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
2008   - }
2009   - if (data->has_features & HAS_VID) {
  2092 + if (data->has_features & HAS_VID)
2010 2093 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
2011   - }
2012   - if (data->has_features & HAS_ZONE3) {
  2094 + if (data->has_features & HAS_ZONE3)
2013 2095 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
2014   - }
2015   - if (data->has_features & HAS_ZONE_HYST) {
  2096 + if (data->has_features & HAS_ZONE_HYST)
2016 2097 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
2017   - }
2018   - if (data->has_features & HAS_IN7) {
  2098 + if (data->has_features & HAS_IN7)
2019 2099 sysfs_remove_group(&dev->kobj, &dme1737_in7_group);
2020   - }
2021 2100 sysfs_remove_group(&dev->kobj, &dme1737_group);
2022 2101  
2023   - if (!data->client) {
  2102 + if (!data->client)
2024 2103 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
2025   - }
2026 2104 }
2027 2105  
2028 2106 static int dme1737_create_files(struct device *dev)
2029 2107  
2030 2108  
2031 2109  
2032 2110  
2033 2111  
2034 2112  
2035 2113  
2036 2114  
2037 2115  
2038 2116  
2039 2117  
2040 2118  
2041 2119  
... ... @@ -2033,48 +2111,41 @@
2033 2111 /* Create a name attribute for ISA devices */
2034 2112 if (!data->client) {
2035 2113 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr);
2036   - if (err) {
  2114 + if (err)
2037 2115 goto exit;
2038   - }
2039 2116 }
2040 2117  
2041 2118 /* Create standard sysfs attributes */
2042 2119 err = sysfs_create_group(&dev->kobj, &dme1737_group);
2043   - if (err) {
  2120 + if (err)
2044 2121 goto exit_remove;
2045   - }
2046 2122  
2047 2123 /* Create chip-dependent sysfs attributes */
2048 2124 if (data->has_features & HAS_TEMP_OFFSET) {
2049 2125 err = sysfs_create_group(&dev->kobj,
2050 2126 &dme1737_temp_offset_group);
2051   - if (err) {
  2127 + if (err)
2052 2128 goto exit_remove;
2053   - }
2054 2129 }
2055 2130 if (data->has_features & HAS_VID) {
2056 2131 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group);
2057   - if (err) {
  2132 + if (err)
2058 2133 goto exit_remove;
2059   - }
2060 2134 }
2061 2135 if (data->has_features & HAS_ZONE3) {
2062 2136 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group);
2063   - if (err) {
  2137 + if (err)
2064 2138 goto exit_remove;
2065   - }
2066 2139 }
2067 2140 if (data->has_features & HAS_ZONE_HYST) {
2068 2141 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group);
2069   - if (err) {
  2142 + if (err)
2070 2143 goto exit_remove;
2071   - }
2072 2144 }
2073 2145 if (data->has_features & HAS_IN7) {
2074 2146 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group);
2075   - if (err) {
  2147 + if (err)
2076 2148 goto exit_remove;
2077   - }
2078 2149 }
2079 2150  
2080 2151 /* Create fan sysfs attributes */
2081 2152  
... ... @@ -2082,9 +2153,8 @@
2082 2153 if (data->has_features & HAS_FAN(ix)) {
2083 2154 err = sysfs_create_group(&dev->kobj,
2084 2155 &dme1737_fan_group[ix]);
2085   - if (err) {
  2156 + if (err)
2086 2157 goto exit_remove;
2087   - }
2088 2158 }
2089 2159 }
2090 2160  
2091 2161  
2092 2162  
2093 2163  
2094 2164  
... ... @@ -2093,21 +2163,21 @@
2093 2163 if (data->has_features & HAS_PWM(ix)) {
2094 2164 err = sysfs_create_group(&dev->kobj,
2095 2165 &dme1737_pwm_group[ix]);
2096   - if (err) {
  2166 + if (err)
2097 2167 goto exit_remove;
2098   - }
2099 2168 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) {
2100 2169 err = sysfs_create_file(&dev->kobj,
2101 2170 dme1737_auto_pwm_min_attr[ix]);
2102   - if (err) {
  2171 + if (err)
2103 2172 goto exit_remove;
2104   - }
2105 2173 }
2106 2174 }
2107 2175 }
2108 2176  
2109   - /* Inform if the device is locked. Otherwise change the permissions of
2110   - * selected attributes from read-only to read-writeable. */
  2177 + /*
  2178 + * Inform if the device is locked. Otherwise change the permissions of
  2179 + * selected attributes from read-only to read-writeable.
  2180 + */
2111 2181 if (data->config & 0x02) {
2112 2182 dev_info(dev, "Device is locked. Some attributes "
2113 2183 "will be read-only.\n");
2114 2184  
2115 2185  
2116 2186  
2117 2187  
2118 2188  
2119 2189  
2120 2190  
... ... @@ -2194,26 +2264,30 @@
2194 2264 return -EFAULT;
2195 2265 }
2196 2266  
2197   - /* Determine which optional fan and pwm features are enabled (only
2198   - * valid for I2C devices) */
  2267 + /*
  2268 + * Determine which optional fan and pwm features are enabled (only
  2269 + * valid for I2C devices)
  2270 + */
2199 2271 if (client) { /* I2C chip */
2200 2272 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
2201 2273 /* Check if optional fan3 input is enabled */
2202   - if (data->config2 & 0x04) {
  2274 + if (data->config2 & 0x04)
2203 2275 data->has_features |= HAS_FAN(2);
2204   - }
2205 2276  
2206   - /* Fan4 and pwm3 are only available if the client's I2C address
  2277 + /*
  2278 + * Fan4 and pwm3 are only available if the client's I2C address
2207 2279 * is the default 0x2e. Otherwise the I/Os associated with
2208   - * these functions are used for addr enable/select. */
2209   - if (client->addr == 0x2e) {
  2280 + * these functions are used for addr enable/select.
  2281 + */
  2282 + if (client->addr == 0x2e)
2210 2283 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
2211   - }
2212 2284  
2213   - /* Determine which of the optional fan[5-6] and pwm[5-6]
  2285 + /*
  2286 + * Determine which of the optional fan[5-6] and pwm[5-6]
2214 2287 * features are enabled. For this, we need to query the runtime
2215 2288 * registers through the Super-IO LPC interface. Try both
2216   - * config ports 0x2e and 0x4e. */
  2289 + * config ports 0x2e and 0x4e.
  2290 + */
2217 2291 if (dme1737_i2c_get_features(0x2e, data) &&
2218 2292 dme1737_i2c_get_features(0x4e, data)) {
2219 2293 dev_warn(dev, "Failed to query Super-IO for optional "
2220 2294  
... ... @@ -2271,9 +2345,11 @@
2271 2345 ((reg >> 4) & 0x03) + 1);
2272 2346 }
2273 2347  
2274   - /* Switch pwm[1-3] to manual mode if they are currently disabled and
  2348 + /*
  2349 + * Switch pwm[1-3] to manual mode if they are currently disabled and
2275 2350 * set the duty-cycles to 0% (which is identical to the PWMs being
2276   - * disabled). */
  2351 + * disabled).
  2352 + */
2277 2353 if (!(data->config & 0x02)) {
2278 2354 for (ix = 0; ix < 3; ix++) {
2279 2355 data->pwm_config[ix] = dme1737_read(data,
2280 2356  
... ... @@ -2298,9 +2374,8 @@
2298 2374 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2299 2375  
2300 2376 /* Set VRM */
2301   - if (data->has_features & HAS_VID) {
  2377 + if (data->has_features & HAS_VID)
2302 2378 data->vrm = vid_which_vrm();
2303   - }
2304 2379  
2305 2380 return 0;
2306 2381 }
... ... @@ -2318,8 +2393,10 @@
2318 2393  
2319 2394 dme1737_sio_enter(sio_cip);
2320 2395  
2321   - /* Check device ID
2322   - * We currently know about two kinds of DME1737 and SCH5027. */
  2396 + /*
  2397 + * Check device ID
  2398 + * We currently know about two kinds of DME1737 and SCH5027.
  2399 + */
2323 2400 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2324 2401 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2325 2402 reg == SCH5027_ID)) {
2326 2403  
2327 2404  
2328 2405  
2329 2406  
2330 2407  
... ... @@ -2338,21 +2415,19 @@
2338 2415 goto exit;
2339 2416 }
2340 2417  
2341   - /* Read the runtime registers to determine which optional features
  2418 + /*
  2419 + * Read the runtime registers to determine which optional features
2342 2420 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
2343   - * to '10' if the respective feature is enabled. */
2344   - if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */
  2421 + * to '10' if the respective feature is enabled.
  2422 + */
  2423 + if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */
2345 2424 data->has_features |= HAS_FAN(5);
2346   - }
2347   - if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */
  2425 + if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */
2348 2426 data->has_features |= HAS_PWM(5);
2349   - }
2350   - if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */
  2427 + if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */
2351 2428 data->has_features |= HAS_FAN(4);
2352   - }
2353   - if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */
  2429 + if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */
2354 2430 data->has_features |= HAS_PWM(4);
2355   - }
2356 2431  
2357 2432 exit:
2358 2433 dme1737_sio_exit(sio_cip);
2359 2434  
... ... @@ -2369,9 +2444,8 @@
2369 2444 u8 company, verstep = 0;
2370 2445 const char *name;
2371 2446  
2372   - if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
  2447 + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2373 2448 return -ENODEV;
2374   - }
2375 2449  
2376 2450 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2377 2451 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
... ... @@ -2486,8 +2560,10 @@
2486 2560  
2487 2561 dme1737_sio_enter(sio_cip);
2488 2562  
2489   - /* Check device ID
2490   - * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 */
  2563 + /*
  2564 + * Check device ID
  2565 + * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127
  2566 + */
2491 2567 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2492 2568 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2493 2569 reg == SCH5127_ID)) {
... ... @@ -2507,8 +2583,10 @@
2507 2583 goto exit;
2508 2584 }
2509 2585  
2510   - /* Access to the hwmon registers is through an index/data register
2511   - * pair located at offset 0x70/0x71. */
  2586 + /*
  2587 + * Access to the hwmon registers is through an index/data register
  2588 + * pair located at offset 0x70/0x71.
  2589 + */
2512 2590 *addr = base_addr + 0x70;
2513 2591  
2514 2592 exit:
2515 2593  
2516 2594  
... ... @@ -2610,11 +2688,10 @@
2610 2688 }
2611 2689 }
2612 2690  
2613   - if (data->type == sch5127) {
  2691 + if (data->type == sch5127)
2614 2692 data->name = "sch5127";
2615   - } else {
  2693 + else
2616 2694 data->name = "sch311x";
2617   - }
2618 2695  
2619 2696 /* Initialize the mutex */
2620 2697 mutex_init(&data->update_lock);
2621 2698  
... ... @@ -2689,9 +2766,8 @@
2689 2766 unsigned short addr;
2690 2767  
2691 2768 err = i2c_add_driver(&dme1737_i2c_driver);
2692   - if (err) {
  2769 + if (err)
2693 2770 goto exit;
2694   - }
2695 2771  
2696 2772 if (dme1737_isa_detect(0x2e, &addr) &&
2697 2773 dme1737_isa_detect(0x4e, &addr) &&
2698 2774  
2699 2775  
2700 2776  
... ... @@ -2703,15 +2779,13 @@
2703 2779 }
2704 2780  
2705 2781 err = platform_driver_register(&dme1737_isa_driver);
2706   - if (err) {
  2782 + if (err)
2707 2783 goto exit_del_i2c_driver;
2708   - }
2709 2784  
2710 2785 /* Sets global pdev as a side effect */
2711 2786 err = dme1737_isa_device_add(addr);
2712   - if (err) {
  2787 + if (err)
2713 2788 goto exit_del_isa_driver;
2714   - }
2715 2789  
2716 2790 return 0;
2717 2791