ARM: OMAP2+: CM: AM43x clockdomain data

Add the data file to describe clock domains in AM43x SoC. OMAP4 clockdomain operations is being reused here. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Acked-by: Rajendra Nayak <rnayak@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>

ARM: OMAP2+: CM: AM43x clockdomain data
Add the data file to describe clock domains in AM43x SoC. OMAP4 clockdomain operations is being reused here. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Acked-by: Rajendra Nayak <rnayak@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Ambresh K · Paul Walmsley
1 parent eadc62fc43
Showing 3 changed files with 207 additions and 0 deletions Side-by-side Diff
arch/arm/mach-omap2/clockdomain.h
arch/arm/mach-omap2/clockdomains43xx_data.c
arch/arm/mach-omap2/cminst44xx.c
@@ -218,6 +218,7 @@
 extern void __init omap44xx_clockdomains_init(void);
 extern void __init omap54xx_clockdomains_init(void);
 extern void __init dra7xx_clockdomains_init(void);
+void am43xx_clockdomains_init(void);
  
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -226,6 +227,7 @@
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
 extern struct clkdm_ops am33xx_clkdm_operations;
+extern struct clkdm_ops am43xx_clkdm_operations;
  
 extern struct clkdm_dep gfx_24xx_wkdeps[];
 extern struct clkdm_dep dsp_24xx_wkdeps[];
+/*
+ * AM43xx Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "prcm44xx.h"
+#include "prcm43xx.h"
+
+static struct clockdomain l4_cefuse_43xx_clkdm = {
+	.name		  = "l4_cefuse_clkdm",
+	.pwrdm		  = { .name = "cefuse_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_CEFUSE_INST,
+	.clkdm_offs	  = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain mpu_43xx_clkdm = {
+	.name		  = "mpu_clkdm",
+	.pwrdm		  = { .name = "mpu_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_MPU_INST,
+	.clkdm_offs	  = AM43XX_CM_MPU_MPU_CDOFFS,
+	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4ls_43xx_clkdm = {
+	.name		  = "l4ls_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_L4LS_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain tamper_43xx_clkdm = {
+	.name		  = "tamper_clkdm",
+	.pwrdm		  = { .name = "tamper_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_TAMPER_INST,
+	.clkdm_offs	  = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_rtc_43xx_clkdm = {
+	.name		  = "l4_rtc_clkdm",
+	.pwrdm		  = { .name = "rtc_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_RTC_INST,
+	.clkdm_offs	  = AM43XX_CM_RTC_RTC_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain pruss_ocp_43xx_clkdm = {
+	.name		  = "pruss_ocp_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_ICSS_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain ocpwp_l3_43xx_clkdm = {
+	.name		  = "ocpwp_l3_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_tsc_43xx_clkdm = {
+	.name		  = "l3s_tsc_clkdm",
+	.pwrdm		  = { .name = "wkup_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_WKUP_INST,
+	.clkdm_offs	  = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain dss_43xx_clkdm = {
+	.name		  = "dss_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_DSS_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3_aon_43xx_clkdm = {
+	.name		  = "l3_aon_clkdm",
+	.pwrdm		  = { .name = "wkup_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_WKUP_INST,
+	.clkdm_offs	  = AM43XX_CM_WKUP_L3_AON_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain emif_43xx_clkdm = {
+	.name		  = "emif_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_EMIF_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_aon_43xx_clkdm = {
+	.name		  = "l4_wkup_aon_clkdm",
+	.pwrdm		  = { .name = "wkup_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_WKUP_INST,
+	.clkdm_offs	  = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
+};
+
+static struct clockdomain l3_43xx_clkdm = {
+	.name		  = "l3_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_L3_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_43xx_clkdm = {
+	.name		  = "l4_wkup_clkdm",
+	.pwrdm		  = { .name = "wkup_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_WKUP_INST,
+	.clkdm_offs	  = AM43XX_CM_WKUP_WKUP_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain cpsw_125mhz_43xx_clkdm = {
+	.name		  = "cpsw_125mhz_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_CPSW_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain gfx_l3_43xx_clkdm = {
+	.name		  = "gfx_l3_clkdm",
+	.pwrdm		  = { .name = "gfx_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_GFX_INST,
+	.clkdm_offs	  = AM43XX_CM_GFX_GFX_L3_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_43xx_clkdm = {
+	.name		  = "l3s_clkdm",
+	.pwrdm		  = { .name = "per_pwrdm" },
+	.prcm_partition	  = AM43XX_CM_PARTITION,
+	.cm_inst	  = AM43XX_CM_PER_INST,
+	.clkdm_offs	  = AM43XX_CM_PER_L3S_CDOFFS,
+	.flags		  = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain *clockdomains_am43xx[] __initdata = {
+	&l4_cefuse_43xx_clkdm,
+	&mpu_43xx_clkdm,
+	&l4ls_43xx_clkdm,
+	&tamper_43xx_clkdm,
+	&l4_rtc_43xx_clkdm,
+	&pruss_ocp_43xx_clkdm,
+	&ocpwp_l3_43xx_clkdm,
+	&l3s_tsc_43xx_clkdm,
+	&dss_43xx_clkdm,
+	&l3_aon_43xx_clkdm,
+	&emif_43xx_clkdm,
+	&l4_wkup_aon_43xx_clkdm,
+	&l3_43xx_clkdm,
+	&l4_wkup_43xx_clkdm,
+	&cpsw_125mhz_43xx_clkdm,
+	&gfx_l3_43xx_clkdm,
+	&l3s_43xx_clkdm,
+	NULL
+};
+
+void __init am43xx_clockdomains_init(void)
+{
+	clkdm_register_platform_funcs(&am43xx_clkdm_operations);
+	clkdm_register_clkdms(clockdomains_am43xx);
+	clkdm_complete_init();
+}
@@ -483,4 +483,13 @@
 	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
 	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
 };
+
+struct clkdm_ops am43xx_clkdm_operations = {
+	.clkdm_sleep		= omap4_clkdm_sleep,
+	.clkdm_wakeup		= omap4_clkdm_wakeup,
+	.clkdm_allow_idle	= omap4_clkdm_allow_idle,
+	.clkdm_deny_idle	= omap4_clkdm_deny_idle,
+	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
+	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
+};
...	...	@@ -218,6 +218,7 @@
218	218	extern void __init omap44xx_clockdomains_init(void);
219	219	extern void __init omap54xx_clockdomains_init(void);
220	220	extern void __init dra7xx_clockdomains_init(void);
	221	+void am43xx_clockdomains_init(void);
221	222
222	223	extern void clkdm_add_autodeps(struct clockdomain *clkdm);
223	224	extern void clkdm_del_autodeps(struct clockdomain *clkdm);
...	...	@@ -226,6 +227,7 @@
226	227	extern struct clkdm_ops omap3_clkdm_operations;
227	228	extern struct clkdm_ops omap4_clkdm_operations;
228	229	extern struct clkdm_ops am33xx_clkdm_operations;
	230	+extern struct clkdm_ops am43xx_clkdm_operations;
229	231
230	232	extern struct clkdm_dep gfx_24xx_wkdeps[];
231	233	extern struct clkdm_dep dsp_24xx_wkdeps[];
	1	+/*
	2	+ * AM43xx Clock domains framework
	3	+ *
	4	+ * Copyright (C) 2013 Texas Instruments, Inc.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify
	7	+ * it under the terms of the GNU General Public License version 2 as
	8	+ * published by the Free Software Foundation.
	9	+ */
	10	+
	11	+#include <linux/kernel.h>
	12	+#include <linux/io.h>
	13	+
	14	+#include "clockdomain.h"
	15	+#include "prcm44xx.h"
	16	+#include "prcm43xx.h"
	17	+
	18	+static struct clockdomain l4_cefuse_43xx_clkdm = {
	19	+ .name = "l4_cefuse_clkdm",
	20	+ .pwrdm = { .name = "cefuse_pwrdm" },
	21	+ .prcm_partition = AM43XX_CM_PARTITION,
	22	+ .cm_inst = AM43XX_CM_CEFUSE_INST,
	23	+ .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
	24	+ .flags = CLKDM_CAN_SWSUP,
	25	+};
	26	+
	27	+static struct clockdomain mpu_43xx_clkdm = {
	28	+ .name = "mpu_clkdm",
	29	+ .pwrdm = { .name = "mpu_pwrdm" },
	30	+ .prcm_partition = AM43XX_CM_PARTITION,
	31	+ .cm_inst = AM43XX_CM_MPU_INST,
	32	+ .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
	33	+ .flags = CLKDM_CAN_HWSUP_SWSUP,
	34	+};
	35	+
	36	+static struct clockdomain l4ls_43xx_clkdm = {
	37	+ .name = "l4ls_clkdm",
	38	+ .pwrdm = { .name = "per_pwrdm" },
	39	+ .prcm_partition = AM43XX_CM_PARTITION,
	40	+ .cm_inst = AM43XX_CM_PER_INST,
	41	+ .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
	42	+ .flags = CLKDM_CAN_SWSUP,
	43	+};
	44	+
	45	+static struct clockdomain tamper_43xx_clkdm = {
	46	+ .name = "tamper_clkdm",
	47	+ .pwrdm = { .name = "tamper_pwrdm" },
	48	+ .prcm_partition = AM43XX_CM_PARTITION,
	49	+ .cm_inst = AM43XX_CM_TAMPER_INST,
	50	+ .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
	51	+ .flags = CLKDM_CAN_SWSUP,
	52	+};
	53	+
	54	+static struct clockdomain l4_rtc_43xx_clkdm = {
	55	+ .name = "l4_rtc_clkdm",
	56	+ .pwrdm = { .name = "rtc_pwrdm" },
	57	+ .prcm_partition = AM43XX_CM_PARTITION,
	58	+ .cm_inst = AM43XX_CM_RTC_INST,
	59	+ .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
	60	+ .flags = CLKDM_CAN_SWSUP,
	61	+};
	62	+
	63	+static struct clockdomain pruss_ocp_43xx_clkdm = {
	64	+ .name = "pruss_ocp_clkdm",
	65	+ .pwrdm = { .name = "per_pwrdm" },
	66	+ .prcm_partition = AM43XX_CM_PARTITION,
	67	+ .cm_inst = AM43XX_CM_PER_INST,
	68	+ .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
	69	+ .flags = CLKDM_CAN_SWSUP,
	70	+};
	71	+
	72	+static struct clockdomain ocpwp_l3_43xx_clkdm = {
	73	+ .name = "ocpwp_l3_clkdm",
	74	+ .pwrdm = { .name = "per_pwrdm" },
	75	+ .prcm_partition = AM43XX_CM_PARTITION,
	76	+ .cm_inst = AM43XX_CM_PER_INST,
	77	+ .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
	78	+ .flags = CLKDM_CAN_SWSUP,
	79	+};
	80	+
	81	+static struct clockdomain l3s_tsc_43xx_clkdm = {
	82	+ .name = "l3s_tsc_clkdm",
	83	+ .pwrdm = { .name = "wkup_pwrdm" },
	84	+ .prcm_partition = AM43XX_CM_PARTITION,
	85	+ .cm_inst = AM43XX_CM_WKUP_INST,
	86	+ .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
	87	+ .flags = CLKDM_CAN_SWSUP,
	88	+};
	89	+
	90	+static struct clockdomain dss_43xx_clkdm = {
	91	+ .name = "dss_clkdm",
	92	+ .pwrdm = { .name = "per_pwrdm" },
	93	+ .prcm_partition = AM43XX_CM_PARTITION,
	94	+ .cm_inst = AM43XX_CM_PER_INST,
	95	+ .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
	96	+ .flags = CLKDM_CAN_SWSUP,
	97	+};
	98	+
	99	+static struct clockdomain l3_aon_43xx_clkdm = {
	100	+ .name = "l3_aon_clkdm",
	101	+ .pwrdm = { .name = "wkup_pwrdm" },
	102	+ .prcm_partition = AM43XX_CM_PARTITION,
	103	+ .cm_inst = AM43XX_CM_WKUP_INST,
	104	+ .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS,
	105	+ .flags = CLKDM_CAN_SWSUP,
	106	+};
	107	+
	108	+static struct clockdomain emif_43xx_clkdm = {
	109	+ .name = "emif_clkdm",
	110	+ .pwrdm = { .name = "per_pwrdm" },
	111	+ .prcm_partition = AM43XX_CM_PARTITION,
	112	+ .cm_inst = AM43XX_CM_PER_INST,
	113	+ .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
	114	+ .flags = CLKDM_CAN_SWSUP,
	115	+};
	116	+
	117	+static struct clockdomain l4_wkup_aon_43xx_clkdm = {
	118	+ .name = "l4_wkup_aon_clkdm",
	119	+ .pwrdm = { .name = "wkup_pwrdm" },
	120	+ .prcm_partition = AM43XX_CM_PARTITION,
	121	+ .cm_inst = AM43XX_CM_WKUP_INST,
	122	+ .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
	123	+};
	124	+
	125	+static struct clockdomain l3_43xx_clkdm = {
	126	+ .name = "l3_clkdm",
	127	+ .pwrdm = { .name = "per_pwrdm" },
	128	+ .prcm_partition = AM43XX_CM_PARTITION,
	129	+ .cm_inst = AM43XX_CM_PER_INST,
	130	+ .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
	131	+ .flags = CLKDM_CAN_SWSUP,
	132	+};
	133	+
	134	+static struct clockdomain l4_wkup_43xx_clkdm = {
	135	+ .name = "l4_wkup_clkdm",
	136	+ .pwrdm = { .name = "wkup_pwrdm" },
	137	+ .prcm_partition = AM43XX_CM_PARTITION,
	138	+ .cm_inst = AM43XX_CM_WKUP_INST,
	139	+ .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS,
	140	+ .flags = CLKDM_CAN_SWSUP,
	141	+};
	142	+
	143	+static struct clockdomain cpsw_125mhz_43xx_clkdm = {
	144	+ .name = "cpsw_125mhz_clkdm",
	145	+ .pwrdm = { .name = "per_pwrdm" },
	146	+ .prcm_partition = AM43XX_CM_PARTITION,
	147	+ .cm_inst = AM43XX_CM_PER_INST,
	148	+ .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
	149	+ .flags = CLKDM_CAN_SWSUP,
	150	+};
	151	+
	152	+static struct clockdomain gfx_l3_43xx_clkdm = {
	153	+ .name = "gfx_l3_clkdm",
	154	+ .pwrdm = { .name = "gfx_pwrdm" },
	155	+ .prcm_partition = AM43XX_CM_PARTITION,
	156	+ .cm_inst = AM43XX_CM_GFX_INST,
	157	+ .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS,
	158	+ .flags = CLKDM_CAN_SWSUP,
	159	+};
	160	+
	161	+static struct clockdomain l3s_43xx_clkdm = {
	162	+ .name = "l3s_clkdm",
	163	+ .pwrdm = { .name = "per_pwrdm" },
	164	+ .prcm_partition = AM43XX_CM_PARTITION,
	165	+ .cm_inst = AM43XX_CM_PER_INST,
	166	+ .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS,
	167	+ .flags = CLKDM_CAN_SWSUP,
	168	+};
	169	+
	170	+static struct clockdomain *clockdomains_am43xx[] __initdata = {
	171	+ &l4_cefuse_43xx_clkdm,
	172	+ &mpu_43xx_clkdm,
	173	+ &l4ls_43xx_clkdm,
	174	+ &tamper_43xx_clkdm,
	175	+ &l4_rtc_43xx_clkdm,
	176	+ &pruss_ocp_43xx_clkdm,
	177	+ &ocpwp_l3_43xx_clkdm,
	178	+ &l3s_tsc_43xx_clkdm,
	179	+ &dss_43xx_clkdm,
	180	+ &l3_aon_43xx_clkdm,
	181	+ &emif_43xx_clkdm,
	182	+ &l4_wkup_aon_43xx_clkdm,
	183	+ &l3_43xx_clkdm,
	184	+ &l4_wkup_43xx_clkdm,
	185	+ &cpsw_125mhz_43xx_clkdm,
	186	+ &gfx_l3_43xx_clkdm,
	187	+ &l3s_43xx_clkdm,
	188	+ NULL
	189	+};
	190	+
	191	+void __init am43xx_clockdomains_init(void)
	192	+{
	193	+ clkdm_register_platform_funcs(&am43xx_clkdm_operations);
	194	+ clkdm_register_clkdms(clockdomains_am43xx);
	195	+ clkdm_complete_init();
	196	+}
...	...	@@ -483,4 +483,13 @@
483	483	.clkdm_clk_enable = omap4_clkdm_clk_enable,
484	484	.clkdm_clk_disable = omap4_clkdm_clk_disable,
485	485	};
	486	+
	487	+struct clkdm_ops am43xx_clkdm_operations = {
	488	+ .clkdm_sleep = omap4_clkdm_sleep,
	489	+ .clkdm_wakeup = omap4_clkdm_wakeup,
	490	+ .clkdm_allow_idle = omap4_clkdm_allow_idle,
	491	+ .clkdm_deny_idle = omap4_clkdm_deny_idle,
	492	+ .clkdm_clk_enable = omap4_clkdm_clk_enable,
	493	+ .clkdm_clk_disable = omap4_clkdm_clk_disable,
	494	+};