powerpc/85xx: Rename p2040_rdb.c to p2041_rdb.c

There's only p2041rdb board for official release, but the p2041 silicon on the board can be converted to p2040 silicon without XAUI and L2 cache function, then the board becomes p2040rdb board. so we use the file name p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also consistent with the board name under U-Boot. During the rename we make few other minor changes to the device tree: * Move USB phy setting into p2041si.dtsi as its SoC not board defined * Convert PCI clock-frequency to decimal to be more readable Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

powerpc/85xx: Rename p2040_rdb.c to p2041_rdb.c
There's only p2041rdb board for official release, but the p2041 silicon on the board can be converted to p2040 silicon without XAUI and L2 cache function, then the board becomes p2040rdb board. so we use the file name p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also consistent with the board name under U-Boot. During the rename we make few other minor changes to the device tree: * Move USB phy setting into p2041si.dtsi as its SoC not board defined * Convert PCI clock-frequency to decimal to be more readable Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu · Kumar Gala
1 parent d70cb31de8
Showing 9 changed files with 877 additions and 882 deletions Side-by-side Diff
arch/powerpc/boot/dts/p2040rdb.dts
arch/powerpc/boot/dts/p2040si.dtsi
arch/powerpc/boot/dts/p2041rdb.dts
arch/powerpc/boot/dts/p2041si.dtsi
arch/powerpc/configs/corenet32_smp_defconfig
arch/powerpc/platforms/85xx/Kconfig
arch/powerpc/platforms/85xx/Makefile
arch/powerpc/platforms/85xx/p2040_rdb.c
arch/powerpc/platforms/85xx/p2041_rdb.c
-/*
- * P2040RDB Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/include/ "p2040si.dtsi"
-
-/ {
-	model = "fsl,P2040RDB";
-	compatible = "fsl,P2040RDB";
-	#address-cells = <2>;
-	#size-cells = <2>;
-	interrupt-parent = <&mpic>;
-
-	memory {
-		device_type = "memory";
-	};
-
-	soc: soc@ffe000000 {
-		spi@110000 {
-			flash@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spansion,s25sl12801";
-				reg = <0>;
-				spi-max-frequency = <40000000>; /* input clock */
-				partition@u-boot {
-					label = "u-boot";
-					reg = <0x00000000 0x00100000>;
-					read-only;
-				};
-				partition@kernel {
-					label = "kernel";
-					reg = <0x00100000 0x00500000>;
-					read-only;
-				};
-				partition@dtb {
-					label = "dtb";
-					reg = <0x00600000 0x00100000>;
-					read-only;
-				};
-				partition@fs {
-					label = "file system";
-					reg = <0x00700000 0x00900000>;
-				};
-			};
-		};
-
-		i2c@118000 {
-			lm75b@48 {
-				compatible = "nxp,lm75a";
-				reg = <0x48>;
-			};
-			eeprom@50 {
-				compatible = "at24,24c256";
-				reg = <0x50>;
-			};
-			rtc@68 {
-				compatible = "pericom,pt7c4338";
-				reg = <0x68>;
-			};
-		};
-
-		i2c@118100 {
-			eeprom@50 {
-				compatible = "at24,24c256";
-				reg = <0x50>;
-			};
-		};
-
-		usb0: usb@210000 {
-			phy_type = "utmi";
-		};
-
-		usb1: usb@211000 {
-			dr_mode = "host";
-			phy_type = "utmi";
-		};
-	};
-
-	localbus@ffe124000 {
-		reg = <0xf 0xfe124000 0 0x1000>;
-		ranges = <0 0 0xf 0xe8000000 0x08000000>;
-
-		flash@0,0 {
-			compatible = "cfi-flash";
-			reg = <0 0 0x08000000>;
-			bank-width = <2>;
-			device-width = <2>;
-		};
-	};
-
-	pci0: pcie@ffe200000 {
-		reg = <0xf 0xfe200000 0 0x1000>;
-		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
-			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
-		pcie@0 {
-			ranges = <0x02000000 0 0xe0000000
-				  0x02000000 0 0xe0000000
-				  0 0x20000000
-
-				  0x01000000 0 0x00000000
-				  0x01000000 0 0x00000000
-				  0 0x00010000>;
-		};
-	};
-
-	pci1: pcie@ffe201000 {
-		reg = <0xf 0xfe201000 0 0x1000>;
-		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
-			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
-		pcie@0 {
-			ranges = <0x02000000 0 0xe0000000
-				  0x02000000 0 0xe0000000
-				  0 0x20000000
-
-				  0x01000000 0 0x00000000
-				  0x01000000 0 0x00000000
-				  0 0x00010000>;
-		};
-	};
-
-	pci2: pcie@ffe202000 {
-		reg = <0xf 0xfe202000 0 0x1000>;
-		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
-			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
-		pcie@0 {
-			ranges = <0x02000000 0 0xe0000000
-				  0x02000000 0 0xe0000000
-				  0 0x20000000
-
-				  0x01000000 0 0x00000000
-				  0x01000000 0 0x00000000
-				  0 0x00010000>;
-		};
-	};
-};
-/*
- * P2040 Silicon Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/dts-v1/;
-
-/ {
-	compatible = "fsl,P2040";
-	#address-cells = <2>;
-	#size-cells = <2>;
-	interrupt-parent = <&mpic>;
-
-	aliases {
-		ccsr = &soc;
-
-		serial0 = &serial0;
-		serial1 = &serial1;
-		serial2 = &serial2;
-		serial3 = &serial3;
-		pci0 = &pci0;
-		pci1 = &pci1;
-		pci2 = &pci2;
-		usb0 = &usb0;
-		usb1 = &usb1;
-		dma0 = &dma0;
-		dma1 = &dma1;
-		sdhc = &sdhc;
-		msi0 = &msi0;
-		msi1 = &msi1;
-		msi2 = &msi2;
-
-		crypto = &crypto;
-		sec_jr0 = &sec_jr0;
-		sec_jr1 = &sec_jr1;
-		sec_jr2 = &sec_jr2;
-		sec_jr3 = &sec_jr3;
-		rtic_a = &rtic_a;
-		rtic_b = &rtic_b;
-		rtic_c = &rtic_c;
-		rtic_d = &rtic_d;
-		sec_mon = &sec_mon;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: PowerPC,e500mc@0 {
-			device_type = "cpu";
-			reg = <0>;
-			next-level-cache = <&L2_0>;
-			L2_0: l2-cache {
-				next-level-cache = <&cpc>;
-			};
-		};
-		cpu1: PowerPC,e500mc@1 {
-			device_type = "cpu";
-			reg = <1>;
-			next-level-cache = <&L2_1>;
-			L2_1: l2-cache {
-				next-level-cache = <&cpc>;
-			};
-		};
-		cpu2: PowerPC,e500mc@2 {
-			device_type = "cpu";
-			reg = <2>;
-			next-level-cache = <&L2_2>;
-			L2_2: l2-cache {
-				next-level-cache = <&cpc>;
-			};
-		};
-		cpu3: PowerPC,e500mc@3 {
-			device_type = "cpu";
-			reg = <3>;
-			next-level-cache = <&L2_3>;
-			L2_3: l2-cache {
-				next-level-cache = <&cpc>;
-			};
-		};
-	};
-
-	soc: soc@ffe000000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		device_type = "soc";
-		compatible = "simple-bus";
-		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-		reg = <0xf 0xfe000000 0 0x00001000>;
-
-		soc-sram-error {
-			compatible = "fsl,soc-sram-error";
-			interrupts = <16 2 1 29>;
-		};
-
-		corenet-law@0 {
-			compatible = "fsl,corenet-law";
-			reg = <0x0 0x1000>;
-			fsl,num-laws = <32>;
-		};
-
-		memory-controller@8000 {
-			compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
-			reg = <0x8000 0x1000>;
-			interrupts = <16 2 1 23>;
-		};
-
-		cpc: l3-cache-controller@10000 {
-			compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
-			reg = <0x10000 0x1000>;
-			interrupts = <16 2 1 27>;
-		};
-
-		corenet-cf@18000 {
-			compatible = "fsl,corenet-cf";
-			reg = <0x18000 0x1000>;
-			interrupts = <16 2 1 31>;
-			fsl,ccf-num-csdids = <32>;
-			fsl,ccf-num-snoopids = <32>;
-		};
-
-		iommu@20000 {
-			compatible = "fsl,pamu-v1.0", "fsl,pamu";
-			reg = <0x20000 0x4000>;
-			interrupts = <
-				24 2 0 0
-				16 2 1 30>;
-		};
-
-		mpic: pic@40000 {
-			clock-frequency = <0>;
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <4>;
-			reg = <0x40000 0x40000>;
-			compatible = "fsl,mpic", "chrp,open-pic";
-			device_type = "open-pic";
-		};
-
-		msi0: msi@41600 {
-			compatible = "fsl,mpic-msi";
-			reg = <0x41600 0x200>;
-			msi-available-ranges = <0 0x100>;
-			interrupts = <
-				0xe0 0 0 0
-				0xe1 0 0 0
-				0xe2 0 0 0
-				0xe3 0 0 0
-				0xe4 0 0 0
-				0xe5 0 0 0
-				0xe6 0 0 0
-				0xe7 0 0 0>;
-		};
-
-		msi1: msi@41800 {
-			compatible = "fsl,mpic-msi";
-			reg = <0x41800 0x200>;
-			msi-available-ranges = <0 0x100>;
-			interrupts = <
-				0xe8 0 0 0
-				0xe9 0 0 0
-				0xea 0 0 0
-				0xeb 0 0 0
-				0xec 0 0 0
-				0xed 0 0 0
-				0xee 0 0 0
-				0xef 0 0 0>;
-		};
-
-		msi2: msi@41a00 {
-			compatible = "fsl,mpic-msi";
-			reg = <0x41a00 0x200>;
-			msi-available-ranges = <0 0x100>;
-			interrupts = <
-				0xf0 0 0 0
-				0xf1 0 0 0
-				0xf2 0 0 0
-				0xf3 0 0 0
-				0xf4 0 0 0
-				0xf5 0 0 0
-				0xf6 0 0 0
-				0xf7 0 0 0>;
-		};
-
-		guts: global-utilities@e0000 {
-			compatible = "fsl,qoriq-device-config-1.0";
-			reg = <0xe0000 0xe00>;
-			fsl,has-rstcr;
-			#sleep-cells = <1>;
-			fsl,liodn-bits = <12>;
-		};
-
-		pins: global-utilities@e0e00 {
-			compatible = "fsl,qoriq-pin-control-1.0";
-			reg = <0xe0e00 0x200>;
-			#sleep-cells = <2>;
-		};
-
-		clockgen: global-utilities@e1000 {
-			compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
-			reg = <0xe1000 0x1000>;
-			clock-frequency = <0>;
-		};
-
-		rcpm: global-utilities@e2000 {
-			compatible = "fsl,qoriq-rcpm-1.0";
-			reg = <0xe2000 0x1000>;
-			#sleep-cells = <1>;
-		};
-
-		sfp: sfp@e8000 {
-			compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
-			reg	   = <0xe8000 0x1000>;
-		};
-
-		serdes: serdes@ea000 {
-			compatible = "fsl,p2040-serdes";
-			reg	   = <0xea000 0x1000>;
-		};
-
-		dma0: dma@100300 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
-			reg = <0x100300 0x4>;
-			ranges = <0x0 0x100100 0x200>;
-			cell-index = <0>;
-			dma-channel@0 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x0 0x80>;
-				cell-index = <0>;
-				interrupts = <28 2 0 0>;
-			};
-			dma-channel@80 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x80 0x80>;
-				cell-index = <1>;
-				interrupts = <29 2 0 0>;
-			};
-			dma-channel@100 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x100 0x80>;
-				cell-index = <2>;
-				interrupts = <30 2 0 0>;
-			};
-			dma-channel@180 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x180 0x80>;
-				cell-index = <3>;
-				interrupts = <31 2 0 0>;
-			};
-		};
-
-		dma1: dma@101300 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
-			reg = <0x101300 0x4>;
-			ranges = <0x0 0x101100 0x200>;
-			cell-index = <1>;
-			dma-channel@0 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x0 0x80>;
-				cell-index = <0>;
-				interrupts = <32 2 0 0>;
-			};
-			dma-channel@80 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x80 0x80>;
-				cell-index = <1>;
-				interrupts = <33 2 0 0>;
-			};
-			dma-channel@100 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x100 0x80>;
-				cell-index = <2>;
-				interrupts = <34 2 0 0>;
-			};
-			dma-channel@180 {
-				compatible = "fsl,p2040-dma-channel",
-						"fsl,eloplus-dma-channel";
-				reg = <0x180 0x80>;
-				cell-index = <3>;
-				interrupts = <35 2 0 0>;
-			};
-		};
-
-		spi@110000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
-			reg = <0x110000 0x1000>;
-			interrupts = <53 0x2 0 0>;
-			fsl,espi-num-chipselects = <4>;
-
-		};
-
-		sdhc: sdhc@114000 {
-			compatible = "fsl,p2040-esdhc", "fsl,esdhc";
-			reg = <0x114000 0x1000>;
-			interrupts = <48 2 0 0>;
-			sdhci,auto-cmd12;
-			clock-frequency = <0>;
-		};
-
-
-		i2c@118000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			cell-index = <0>;
-			compatible = "fsl-i2c";
-			reg = <0x118000 0x100>;
-			interrupts = <38 2 0 0>;
-			dfsrr;
-		};
-
-		i2c@118100 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			cell-index = <1>;
-			compatible = "fsl-i2c";
-			reg = <0x118100 0x100>;
-			interrupts = <38 2 0 0>;
-			dfsrr;
-		};
-
-		i2c@119000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			cell-index = <2>;
-			compatible = "fsl-i2c";
-			reg = <0x119000 0x100>;
-			interrupts = <39 2 0 0>;
-			dfsrr;
-		};
-
-		i2c@119100 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			cell-index = <3>;
-			compatible = "fsl-i2c";
-			reg = <0x119100 0x100>;
-			interrupts = <39 2 0 0>;
-			dfsrr;
-		};
-
-		serial0: serial@11c500 {
-			cell-index = <0>;
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0x11c500 0x100>;
-			clock-frequency = <0>;
-			interrupts = <36 2 0 0>;
-		};
-
-		serial1: serial@11c600 {
-			cell-index = <1>;
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0x11c600 0x100>;
-			clock-frequency = <0>;
-			interrupts = <36 2 0 0>;
-		};
-
-		serial2: serial@11d500 {
-			cell-index = <2>;
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0x11d500 0x100>;
-			clock-frequency = <0>;
-			interrupts = <37 2 0 0>;
-		};
-
-		serial3: serial@11d600 {
-			cell-index = <3>;
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0x11d600 0x100>;
-			clock-frequency = <0>;
-			interrupts = <37 2 0 0>;
-		};
-
-		gpio0: gpio@130000 {
-			compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
-			reg = <0x130000 0x1000>;
-			interrupts = <55 2 0 0>;
-			#gpio-cells = <2>;
-			gpio-controller;
-		};
-
-		usb0: usb@210000 {
-			compatible = "fsl,p2040-usb2-mph",
-					"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
-			reg = <0x210000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <44 0x2 0 0>;
-			port0;
-		};
-
-		usb1: usb@211000 {
-			compatible = "fsl,p2040-usb2-dr",
-					"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
-			reg = <0x211000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <45 0x2 0 0>;
-		};
-
-		sata@220000 {
-			compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
-			reg = <0x220000 0x1000>;
-			interrupts = <68 0x2 0 0>;
-		};
-
-		sata@221000 {
-			compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
-			reg = <0x221000 0x1000>;
-			interrupts = <69 0x2 0 0>;
-		};
-
-		crypto: crypto@300000 {
-			compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0x300000 0x10000>;
-			ranges = <0 0x300000 0x10000>;
-			interrupts = <92 2 0 0>;
-
-			sec_jr0: jr@1000 {
-				compatible = "fsl,sec-v4.2-job-ring",
-					     "fsl,sec-v4.0-job-ring";
-				reg = <0x1000 0x1000>;
-				interrupts = <88 2 0 0>;
-			};
-
-			sec_jr1: jr@2000 {
-				compatible = "fsl,sec-v4.2-job-ring",
-					     "fsl,sec-v4.0-job-ring";
-				reg = <0x2000 0x1000>;
-				interrupts = <89 2 0 0>;
-			};
-
-			sec_jr2: jr@3000 {
-				compatible = "fsl,sec-v4.2-job-ring",
-					     "fsl,sec-v4.0-job-ring";
-				reg = <0x3000 0x1000>;
-				interrupts = <90 2 0 0>;
-			};
-
-			sec_jr3: jr@4000 {
-				compatible = "fsl,sec-v4.2-job-ring",
-					     "fsl,sec-v4.0-job-ring";
-				reg = <0x4000 0x1000>;
-				interrupts = <91 2 0 0>;
-			};
-
-			rtic@6000 {
-				compatible = "fsl,sec-v4.2-rtic",
-					     "fsl,sec-v4.0-rtic";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				reg = <0x6000 0x100>;
-				ranges = <0x0 0x6100 0xe00>;
-
-				rtic_a: rtic-a@0 {
-					compatible = "fsl,sec-v4.2-rtic-memory",
-						     "fsl,sec-v4.0-rtic-memory";
-					reg = <0x00 0x20 0x100 0x80>;
-				};
-
-				rtic_b: rtic-b@20 {
-					compatible = "fsl,sec-v4.2-rtic-memory",
-						     "fsl,sec-v4.0-rtic-memory";
-					reg = <0x20 0x20 0x200 0x80>;
-				};
-
-				rtic_c: rtic-c@40 {
-					compatible = "fsl,sec-v4.2-rtic-memory",
-						     "fsl,sec-v4.0-rtic-memory";
-					reg = <0x40 0x20 0x300 0x80>;
-				};
-
-				rtic_d: rtic-d@60 {
-					compatible = "fsl,sec-v4.2-rtic-memory",
-						     "fsl,sec-v4.0-rtic-memory";
-					reg = <0x60 0x20 0x500 0x80>;
-				};
-			};
-		};
-
-		sec_mon: sec_mon@314000 {
-			compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
-			reg = <0x314000 0x1000>;
-			interrupts = <93 2 0 0>;
-		};
-
-	};
-
-	localbus@ffe124000 {
-		compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
-		interrupts = <25 2 0 0>;
-		#address-cells = <2>;
-		#size-cells = <1>;
-	};
-
-	pci0: pcie@ffe200000 {
-		compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
-		device_type = "pci";
-		#size-cells = <2>;
-		#address-cells = <3>;
-		bus-range = <0x0 0xff>;
-		clock-frequency = <0x1fca055>;
-		fsl,msi = <&msi0>;
-		interrupts = <16 2 1 15>;
-		pcie@0 {
-			reg = <0 0 0 0 0>;
-			#interrupt-cells = <1>;
-			#size-cells = <2>;
-			#address-cells = <3>;
-			device_type = "pci";
-			interrupts = <16 2 1 15>;
-			interrupt-map-mask = <0xf800 0 0 7>;
-			interrupt-map = <
-				/* IDSEL 0x0 */
-				0000 0 0 1 &mpic 40 1 0 0
-				0000 0 0 2 &mpic 1 1 0 0
-				0000 0 0 3 &mpic 2 1 0 0
-				0000 0 0 4 &mpic 3 1 0 0
-				>;
-		};
-	};
-
-	pci1: pcie@ffe201000 {
-		compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
-		device_type = "pci";
-		#size-cells = <2>;
-		#address-cells = <3>;
-		bus-range = <0 0xff>;
-		clock-frequency = <0x1fca055>;
-		fsl,msi = <&msi1>;
-		interrupts = <16 2 1 14>;
-		pcie@0 {
-			reg = <0 0 0 0 0>;
-			#interrupt-cells = <1>;
-			#size-cells = <2>;
-			#address-cells = <3>;
-			device_type = "pci";
-			interrupts = <16 2 1 14>;
-			interrupt-map-mask = <0xf800 0 0 7>;
-			interrupt-map = <
-				/* IDSEL 0x0 */
-				0000 0 0 1 &mpic 41 1 0 0
-				0000 0 0 2 &mpic 5 1 0 0
-				0000 0 0 3 &mpic 6 1 0 0
-				0000 0 0 4 &mpic 7 1 0 0
-				>;
-		};
-	};
-
-	pci2: pcie@ffe202000 {
-		compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
-		device_type = "pci";
-		#size-cells = <2>;
-		#address-cells = <3>;
-		bus-range = <0x0 0xff>;
-		clock-frequency = <0x1fca055>;
-		fsl,msi = <&msi2>;
-		interrupts = <16 2 1 13>;
-		pcie@0 {
-			reg = <0 0 0 0 0>;
-			#interrupt-cells = <1>;
-			#size-cells = <2>;
-			#address-cells = <3>;
-			device_type = "pci";
-			interrupts = <16 2 1 13>;
-			interrupt-map-mask = <0xf800 0 0 7>;
-			interrupt-map = <
-				/* IDSEL 0x0 */
-				0000 0 0 1 &mpic 42 1 0 0
-				0000 0 0 2 &mpic 9 1 0 0
-				0000 0 0 3 &mpic 10 1 0 0
-				0000 0 0 4 &mpic 11 1 0 0
-				>;
-		};
-	};
-};
+/*
+ * P2041RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "p2041si.dtsi"
+
+/ {
+	model = "fsl,P2041RDB";
+	compatible = "fsl,P2041RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	memory {
+		device_type = "memory";
+	};
+
+	soc: soc@ffe000000 {
+		spi@110000 {
+			flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spansion,s25sl12801";
+				reg = <0>;
+				spi-max-frequency = <40000000>; /* input clock */
+				partition@u-boot {
+					label = "u-boot";
+					reg = <0x00000000 0x00100000>;
+					read-only;
+				};
+				partition@kernel {
+					label = "kernel";
+					reg = <0x00100000 0x00500000>;
+					read-only;
+				};
+				partition@dtb {
+					label = "dtb";
+					reg = <0x00600000 0x00100000>;
+					read-only;
+				};
+				partition@fs {
+					label = "file system";
+					reg = <0x00700000 0x00900000>;
+				};
+			};
+		};
+
+		i2c@118000 {
+			lm75b@48 {
+				compatible = "nxp,lm75a";
+				reg = <0x48>;
+			};
+			eeprom@50 {
+				compatible = "at24,24c256";
+				reg = <0x50>;
+			};
+			rtc@68 {
+				compatible = "pericom,pt7c4338";
+				reg = <0x68>;
+			};
+		};
+
+		i2c@118100 {
+			eeprom@50 {
+				compatible = "at24,24c256";
+				reg = <0x50>;
+			};
+		};
+
+		usb1: usb@211000 {
+			dr_mode = "host";
+		};
+	};
+
+	localbus@ffe124000 {
+		reg = <0xf 0xfe124000 0 0x1000>;
+		ranges = <0 0 0xf 0xe8000000 0x08000000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x08000000>;
+			bank-width = <2>;
+			device-width = <2>;
+		};
+	};
+
+	pci0: pcie@ffe200000 {
+		reg = <0xf 0xfe200000 0 0x1000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x20000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+	pci1: pcie@ffe201000 {
+		reg = <0xf 0xfe201000 0 0x1000>;
+		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x20000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+	pci2: pcie@ffe202000 {
+		reg = <0xf 0xfe202000 0 0x1000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x20000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+};
+/*
+ * P2041 Silicon Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "fsl,P2041";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		ccsr = &soc;
+
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		pci0 = &pci0;
+		pci1 = &pci1;
+		pci2 = &pci2;
+		usb0 = &usb0;
+		usb1 = &usb1;
+		dma0 = &dma0;
+		dma1 = &dma1;
+		sdhc = &sdhc;
+		msi0 = &msi0;
+		msi1 = &msi1;
+		msi2 = &msi2;
+
+		crypto = &crypto;
+		sec_jr0 = &sec_jr0;
+		sec_jr1 = &sec_jr1;
+		sec_jr2 = &sec_jr2;
+		sec_jr3 = &sec_jr3;
+		rtic_a = &rtic_a;
+		rtic_b = &rtic_b;
+		rtic_c = &rtic_c;
+		rtic_d = &rtic_d;
+		sec_mon = &sec_mon;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e500mc@0 {
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+		cpu1: PowerPC,e500mc@1 {
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2_1>;
+			L2_1: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+		cpu2: PowerPC,e500mc@2 {
+			device_type = "cpu";
+			reg = <2>;
+			next-level-cache = <&L2_2>;
+			L2_2: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+		cpu3: PowerPC,e500mc@3 {
+			device_type = "cpu";
+			reg = <3>;
+			next-level-cache = <&L2_3>;
+			L2_3: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+	};
+
+	soc: soc@ffe000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+
+		soc-sram-error {
+			compatible = "fsl,soc-sram-error";
+			interrupts = <16 2 1 29>;
+		};
+
+		corenet-law@0 {
+			compatible = "fsl,corenet-law";
+			reg = <0x0 0x1000>;
+			fsl,num-laws = <32>;
+		};
+
+		memory-controller@8000 {
+			compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+			reg = <0x8000 0x1000>;
+			interrupts = <16 2 1 23>;
+		};
+
+		cpc: l3-cache-controller@10000 {
+			compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+			reg = <0x10000 0x1000>;
+			interrupts = <16 2 1 27>;
+		};
+
+		corenet-cf@18000 {
+			compatible = "fsl,corenet-cf";
+			reg = <0x18000 0x1000>;
+			interrupts = <16 2 1 31>;
+			fsl,ccf-num-csdids = <32>;
+			fsl,ccf-num-snoopids = <32>;
+		};
+
+		iommu@20000 {
+			compatible = "fsl,pamu-v1.0", "fsl,pamu";
+			reg = <0x20000 0x4000>;
+			interrupts = <
+				24 2 0 0
+				16 2 1 30>;
+		};
+
+		mpic: pic@40000 {
+			clock-frequency = <0>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+		};
+
+		msi0: msi@41600 {
+			compatible = "fsl,mpic-msi";
+			reg = <0x41600 0x200>;
+			msi-available-ranges = <0 0x100>;
+			interrupts = <
+				0xe0 0 0 0
+				0xe1 0 0 0
+				0xe2 0 0 0
+				0xe3 0 0 0
+				0xe4 0 0 0
+				0xe5 0 0 0
+				0xe6 0 0 0
+				0xe7 0 0 0>;
+		};
+
+		msi1: msi@41800 {
+			compatible = "fsl,mpic-msi";
+			reg = <0x41800 0x200>;
+			msi-available-ranges = <0 0x100>;
+			interrupts = <
+				0xe8 0 0 0
+				0xe9 0 0 0
+				0xea 0 0 0
+				0xeb 0 0 0
+				0xec 0 0 0
+				0xed 0 0 0
+				0xee 0 0 0
+				0xef 0 0 0>;
+		};
+
+		msi2: msi@41a00 {
+			compatible = "fsl,mpic-msi";
+			reg = <0x41a00 0x200>;
+			msi-available-ranges = <0 0x100>;
+			interrupts = <
+				0xf0 0 0 0
+				0xf1 0 0 0
+				0xf2 0 0 0
+				0xf3 0 0 0
+				0xf4 0 0 0
+				0xf5 0 0 0
+				0xf6 0 0 0
+				0xf7 0 0 0>;
+		};
+
+		guts: global-utilities@e0000 {
+			compatible = "fsl,qoriq-device-config-1.0";
+			reg = <0xe0000 0xe00>;
+			fsl,has-rstcr;
+			#sleep-cells = <1>;
+			fsl,liodn-bits = <12>;
+		};
+
+		pins: global-utilities@e0e00 {
+			compatible = "fsl,qoriq-pin-control-1.0";
+			reg = <0xe0e00 0x200>;
+			#sleep-cells = <2>;
+		};
+
+		clockgen: global-utilities@e1000 {
+			compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
+			reg = <0xe1000 0x1000>;
+			clock-frequency = <0>;
+		};
+
+		rcpm: global-utilities@e2000 {
+			compatible = "fsl,qoriq-rcpm-1.0";
+			reg = <0xe2000 0x1000>;
+			#sleep-cells = <1>;
+		};
+
+		sfp: sfp@e8000 {
+			compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
+			reg	   = <0xe8000 0x1000>;
+		};
+
+		serdes: serdes@ea000 {
+			compatible = "fsl,p2041-serdes";
+			reg	   = <0xea000 0x1000>;
+		};
+
+		dma0: dma@100300 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
+			reg = <0x100300 0x4>;
+			ranges = <0x0 0x100100 0x200>;
+			cell-index = <0>;
+			dma-channel@0 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x0 0x80>;
+				cell-index = <0>;
+				interrupts = <28 2 0 0>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x80 0x80>;
+				cell-index = <1>;
+				interrupts = <29 2 0 0>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x100 0x80>;
+				cell-index = <2>;
+				interrupts = <30 2 0 0>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x180 0x80>;
+				cell-index = <3>;
+				interrupts = <31 2 0 0>;
+			};
+		};
+
+		dma1: dma@101300 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
+			reg = <0x101300 0x4>;
+			ranges = <0x0 0x101100 0x200>;
+			cell-index = <1>;
+			dma-channel@0 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x0 0x80>;
+				cell-index = <0>;
+				interrupts = <32 2 0 0>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x80 0x80>;
+				cell-index = <1>;
+				interrupts = <33 2 0 0>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x100 0x80>;
+				cell-index = <2>;
+				interrupts = <34 2 0 0>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,p2041-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x180 0x80>;
+				cell-index = <3>;
+				interrupts = <35 2 0 0>;
+			};
+		};
+
+		spi@110000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
+			reg = <0x110000 0x1000>;
+			interrupts = <53 0x2 0 0>;
+			fsl,espi-num-chipselects = <4>;
+		};
+
+		sdhc: sdhc@114000 {
+			compatible = "fsl,p2041-esdhc", "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			interrupts = <48 2 0 0>;
+			sdhci,auto-cmd12;
+			clock-frequency = <0>;
+		};
+
+		i2c@118000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl-i2c";
+			reg = <0x118000 0x100>;
+			interrupts = <38 2 0 0>;
+			dfsrr;
+		};
+
+		i2c@118100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			compatible = "fsl-i2c";
+			reg = <0x118100 0x100>;
+			interrupts = <38 2 0 0>;
+			dfsrr;
+		};
+
+		i2c@119000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <2>;
+			compatible = "fsl-i2c";
+			reg = <0x119000 0x100>;
+			interrupts = <39 2 0 0>;
+			dfsrr;
+		};
+
+		i2c@119100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <3>;
+			compatible = "fsl-i2c";
+			reg = <0x119100 0x100>;
+			interrupts = <39 2 0 0>;
+			dfsrr;
+		};
+
+		serial0: serial@11c500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0x11c500 0x100>;
+			clock-frequency = <0>;
+			interrupts = <36 2 0 0>;
+		};
+
+		serial1: serial@11c600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0x11c600 0x100>;
+			clock-frequency = <0>;
+			interrupts = <36 2 0 0>;
+		};
+
+		serial2: serial@11d500 {
+			cell-index = <2>;
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0x11d500 0x100>;
+			clock-frequency = <0>;
+			interrupts = <37 2 0 0>;
+		};
+
+		serial3: serial@11d600 {
+			cell-index = <3>;
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0x11d600 0x100>;
+			clock-frequency = <0>;
+			interrupts = <37 2 0 0>;
+		};
+
+		gpio0: gpio@130000 {
+			compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
+			reg = <0x130000 0x1000>;
+			interrupts = <55 2 0 0>;
+			#gpio-cells = <2>;
+			gpio-controller;
+		};
+
+		usb0: usb@210000 {
+			compatible = "fsl,p2041-usb2-mph",
+					"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <44 0x2 0 0>;
+			phy_type = "utmi";
+			port0;
+		};
+
+		usb1: usb@211000 {
+			compatible = "fsl,p2041-usb2-dr",
+					"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <45 0x2 0 0>;
+			phy_type = "utmi";
+		};
+
+		sata@220000 {
+			compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+		};
+
+		sata@221000 {
+			compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
+			reg = <0x221000 0x1000>;
+			interrupts = <69 0x2 0 0>;
+		};
+
+		crypto: crypto@300000 {
+			compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x300000 0x10000>;
+			ranges = <0 0x300000 0x10000>;
+			interrupts = <92 2 0 0>;
+
+			sec_jr0: jr@1000 {
+				compatible = "fsl,sec-v4.2-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x1000 0x1000>;
+				interrupts = <88 2 0 0>;
+			};
+
+			sec_jr1: jr@2000 {
+				compatible = "fsl,sec-v4.2-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x2000 0x1000>;
+				interrupts = <89 2 0 0>;
+			};
+
+			sec_jr2: jr@3000 {
+				compatible = "fsl,sec-v4.2-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x3000 0x1000>;
+				interrupts = <90 2 0 0>;
+			};
+
+			sec_jr3: jr@4000 {
+				compatible = "fsl,sec-v4.2-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg = <0x4000 0x1000>;
+				interrupts = <91 2 0 0>;
+			};
+
+			rtic@6000 {
+				compatible = "fsl,sec-v4.2-rtic",
+					     "fsl,sec-v4.0-rtic";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x6000 0x100>;
+				ranges = <0x0 0x6100 0xe00>;
+
+				rtic_a: rtic-a@0 {
+					compatible = "fsl,sec-v4.2-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x00 0x20 0x100 0x80>;
+				};
+
+				rtic_b: rtic-b@20 {
+					compatible = "fsl,sec-v4.2-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x20 0x20 0x200 0x80>;
+				};
+
+				rtic_c: rtic-c@40 {
+					compatible = "fsl,sec-v4.2-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x40 0x20 0x300 0x80>;
+				};
+
+				rtic_d: rtic-d@60 {
+					compatible = "fsl,sec-v4.2-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x60 0x20 0x500 0x80>;
+				};
+			};
+		};
+
+		sec_mon: sec_mon@314000 {
+			compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+			reg = <0x314000 0x1000>;
+			interrupts = <93 2 0 0>;
+		};
+
+	};
+
+	localbus@ffe124000 {
+		compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
+		interrupts = <25 2 0 0>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+	};
+
+	pci0: pcie@ffe200000 {
+		compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+		device_type = "pci";
+		#size-cells = <2>;
+		#address-cells = <3>;
+		bus-range = <0x0 0xff>;
+		clock-frequency = <33333333>;
+		fsl,msi = <&msi0>;
+		interrupts = <16 2 1 15>;
+		pcie@0 {
+			reg = <0 0 0 0 0>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			device_type = "pci";
+			interrupts = <16 2 1 15>;
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x0 */
+				0000 0 0 1 &mpic 40 1 0 0
+				0000 0 0 2 &mpic 1 1 0 0
+				0000 0 0 3 &mpic 2 1 0 0
+				0000 0 0 4 &mpic 3 1 0 0
+				>;
+		};
+	};
+
+	pci1: pcie@ffe201000 {
+		compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+		device_type = "pci";
+		#size-cells = <2>;
+		#address-cells = <3>;
+		bus-range = <0 0xff>;
+		clock-frequency = <33333333>;
+		fsl,msi = <&msi1>;
+		interrupts = <16 2 1 14>;
+		pcie@0 {
+			reg = <0 0 0 0 0>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			device_type = "pci";
+			interrupts = <16 2 1 14>;
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x0 */
+				0000 0 0 1 &mpic 41 1 0 0
+				0000 0 0 2 &mpic 5 1 0 0
+				0000 0 0 3 &mpic 6 1 0 0
+				0000 0 0 4 &mpic 7 1 0 0
+				>;
+		};
+	};
+
+	pci2: pcie@ffe202000 {
+		compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+		device_type = "pci";
+		#size-cells = <2>;
+		#address-cells = <3>;
+		bus-range = <0x0 0xff>;
+		clock-frequency = <33333333>;
+		fsl,msi = <&msi2>;
+		interrupts = <16 2 1 13>;
+		pcie@0 {
+			reg = <0 0 0 0 0>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			device_type = "pci";
+			interrupts = <16 2 1 13>;
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x0 */
+				0000 0 0 1 &mpic 42 1 0 0
+				0000 0 0 2 &mpic 9 1 0 0
+				0000 0 0 3 &mpic 10 1 0 0
+				0000 0 0 4 &mpic 11 1 0 0
+				>;
+		};
+	};
+};
@@ -23,7 +23,7 @@
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_P2040_RDB=y
+CONFIG_P2041_RDB=y
 CONFIG_P3041_DS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
@@ -171,8 +171,8 @@
 	help
 	  This option enables support for the Wind River SBC8560 board
  
-config P2040_RDB
-	bool "Freescale P2040 RDB"
+config P2041_RDB
+	bool "Freescale P2041 RDB"
 	select DEFAULT_UIMAGE
 	select PPC_E500MC
 	select PHYS_64BIT
@@ -182,7 +182,7 @@
 	select HAS_RAPIDIO
 	select PPC_EPAPR_HV_PIC
 	help
-	  This option enables support for the P2040 RDB board
+	  This option enables support for the P2041 RDB board
  
 config P3041_DS
 	bool "Freescale P3041 DS"
@@ -13,7 +13,7 @@
 obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
 obj-$(CONFIG_P1022_DS)    += p1022_ds.o
 obj-$(CONFIG_P1023_RDS)   += p1023_rds.o
-obj-$(CONFIG_P2040_RDB)   += p2040_rdb.o corenet_ds.o
+obj-$(CONFIG_P2041_RDB)   += p2041_rdb.o corenet_ds.o
 obj-$(CONFIG_P3041_DS)    += p3041_ds.o corenet_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_P5020_DS)    += p5020_ds.o corenet_ds.o
-/*
- * P2040 RDB Setup
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/phy.h>
-
-#include <asm/system.h>
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init p2040_rdb_probe(void)
-{
-	unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
-	extern struct smp_ops_t smp_85xx_ops;
-#endif
-
-	if (of_flat_dt_is_compatible(root, "fsl,P2040RDB"))
-		return 1;
-
-	/* Check if we're running under the Freescale hypervisor */
-	if (of_flat_dt_is_compatible(root, "fsl,P2040RDB-hv")) {
-		ppc_md.init_IRQ = ehv_pic_init;
-		ppc_md.get_irq = ehv_pic_get_irq;
-		ppc_md.restart = fsl_hv_restart;
-		ppc_md.power_off = fsl_hv_halt;
-		ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
-		/*
-		 * Disable the timebase sync operations because we can't write
-		 * to the timebase registers under the hypervisor.
-		  */
-		smp_85xx_ops.give_timebase = NULL;
-		smp_85xx_ops.take_timebase = NULL;
-#endif
-		return 1;
-	}
-
-	return 0;
-}
-
-define_machine(p2040_rdb) {
-	.name			= "P2040 RDB",
-	.probe			= p2040_rdb_probe,
-	.setup_arch		= corenet_ds_setup_arch,
-	.init_IRQ		= corenet_ds_pic_init,
-#ifdef CONFIG_PCI
-	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
-#endif
-	.get_irq		= mpic_get_coreint_irq,
-	.restart		= fsl_rstcr_restart,
-	.calibrate_decr		= generic_calibrate_decr,
-	.progress		= udbg_progress,
-	.power_save		= e500_idle,
-};
-
-machine_device_initcall(p2040_rdb, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(p2040_rdb, swiotlb_setup_bus_notifier);
-#endif
+/*
+ * P2041 RDB Setup
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p2041_rdb_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+	extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+	if (of_flat_dt_is_compatible(root, "fsl,P2041RDB"))
+		return 1;
+
+	/* Check if we're running under the Freescale hypervisor */
+	if (of_flat_dt_is_compatible(root, "fsl,P2041RDB-hv")) {
+		ppc_md.init_IRQ = ehv_pic_init;
+		ppc_md.get_irq = ehv_pic_get_irq;
+		ppc_md.restart = fsl_hv_restart;
+		ppc_md.power_off = fsl_hv_halt;
+		ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+		/*
+		 * Disable the timebase sync operations because we can't write
+		 * to the timebase registers under the hypervisor.
+		  */
+		smp_85xx_ops.give_timebase = NULL;
+		smp_85xx_ops.take_timebase = NULL;
+#endif
+		return 1;
+	}
+
+	return 0;
+}
+
+define_machine(p2041_rdb) {
+	.name			= "P2041 RDB",
+	.probe			= p2041_rdb_probe,
+	.setup_arch		= corenet_ds_setup_arch,
+	.init_IRQ		= corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+	.get_irq		= mpic_get_coreint_irq,
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+	.power_save		= e500_idle,
+};
+
+machine_device_initcall(p2041_rdb, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
+#endif
1		-/*
2		- * P2040RDB Device Tree Source
3		- *
4		- * Copyright 2011 Freescale Semiconductor Inc.
5		- *
6		- * Redistribution and use in source and binary forms, with or without
7		- * modification, are permitted provided that the following conditions are met:
8		- * * Redistributions of source code must retain the above copyright
9		- * notice, this list of conditions and the following disclaimer.
10		- * * Redistributions in binary form must reproduce the above copyright
11		- * notice, this list of conditions and the following disclaimer in the
12		- * documentation and/or other materials provided with the distribution.
13		- * * Neither the name of Freescale Semiconductor nor the
14		- * names of its contributors may be used to endorse or promote products
15		- * derived from this software without specific prior written permission.
16		- *
17		- *
18		- * ALTERNATIVELY, this software may be distributed under the terms of the
19		- * GNU General Public License ("GPL") as published by the Free Software
20		- * Foundation, either version 2 of that License or (at your option) any
21		- * later version.
22		- *
23		- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24		- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25		- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26		- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27		- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28		- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29		- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30		- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31		- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32		- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33		- */
34		-
35		-/include/ "p2040si.dtsi"
36		-
37		-/ {
38		- model = "fsl,P2040RDB";
39		- compatible = "fsl,P2040RDB";
40		- #address-cells = <2>;
41		- #size-cells = <2>;
42		- interrupt-parent = <&mpic>;
43		-
44		- memory {
45		- device_type = "memory";
46		- };
47		-
48		- soc: soc@ffe000000 {
49		- spi@110000 {
50		- flash@0 {
51		- #address-cells = <1>;
52		- #size-cells = <1>;
53		- compatible = "spansion,s25sl12801";
54		- reg = <0>;
55		- spi-max-frequency = <40000000>; /* input clock */
56		- partition@u-boot {
57		- label = "u-boot";
58		- reg = <0x00000000 0x00100000>;
59		- read-only;
60		- };
61		- partition@kernel {
62		- label = "kernel";
63		- reg = <0x00100000 0x00500000>;
64		- read-only;
65		- };
66		- partition@dtb {
67		- label = "dtb";
68		- reg = <0x00600000 0x00100000>;
69		- read-only;
70		- };
71		- partition@fs {
72		- label = "file system";
73		- reg = <0x00700000 0x00900000>;
74		- };
75		- };
76		- };
77		-
78		- i2c@118000 {
79		- lm75b@48 {
80		- compatible = "nxp,lm75a";
81		- reg = <0x48>;
82		- };
83		- eeprom@50 {
84		- compatible = "at24,24c256";
85		- reg = <0x50>;
86		- };
87		- rtc@68 {
88		- compatible = "pericom,pt7c4338";
89		- reg = <0x68>;
90		- };
91		- };
92		-
93		- i2c@118100 {
94		- eeprom@50 {
95		- compatible = "at24,24c256";
96		- reg = <0x50>;
97		- };
98		- };
99		-
100		- usb0: usb@210000 {
101		- phy_type = "utmi";
102		- };
103		-
104		- usb1: usb@211000 {
105		- dr_mode = "host";
106		- phy_type = "utmi";
107		- };
108		- };
109		-
110		- localbus@ffe124000 {
111		- reg = <0xf 0xfe124000 0 0x1000>;
112		- ranges = <0 0 0xf 0xe8000000 0x08000000>;
113		-
114		- flash@0,0 {
115		- compatible = "cfi-flash";
116		- reg = <0 0 0x08000000>;
117		- bank-width = <2>;
118		- device-width = <2>;
119		- };
120		- };
121		-
122		- pci0: pcie@ffe200000 {
123		- reg = <0xf 0xfe200000 0 0x1000>;
124		- ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
125		- 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
126		- pcie@0 {
127		- ranges = <0x02000000 0 0xe0000000
128		- 0x02000000 0 0xe0000000
129		- 0 0x20000000
130		-
131		- 0x01000000 0 0x00000000
132		- 0x01000000 0 0x00000000
133		- 0 0x00010000>;
134		- };
135		- };
136		-
137		- pci1: pcie@ffe201000 {
138		- reg = <0xf 0xfe201000 0 0x1000>;
139		- ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
140		- 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
141		- pcie@0 {
142		- ranges = <0x02000000 0 0xe0000000
143		- 0x02000000 0 0xe0000000
144		- 0 0x20000000
145		-
146		- 0x01000000 0 0x00000000
147		- 0x01000000 0 0x00000000
148		- 0 0x00010000>;
149		- };
150		- };
151		-
152		- pci2: pcie@ffe202000 {
153		- reg = <0xf 0xfe202000 0 0x1000>;
154		- ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
155		- 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
156		- pcie@0 {
157		- ranges = <0x02000000 0 0xe0000000
158		- 0x02000000 0 0xe0000000
159		- 0 0x20000000
160		-
161		- 0x01000000 0 0x00000000
162		- 0x01000000 0 0x00000000
163		- 0 0x00010000>;
164		- };
165		- };
166		-};
1		-/*
2		- * P2040 Silicon Device Tree Source
3		- *
4		- * Copyright 2011 Freescale Semiconductor Inc.
5		- *
6		- * Redistribution and use in source and binary forms, with or without
7		- * modification, are permitted provided that the following conditions are met:
8		- * * Redistributions of source code must retain the above copyright
9		- * notice, this list of conditions and the following disclaimer.
10		- * * Redistributions in binary form must reproduce the above copyright
11		- * notice, this list of conditions and the following disclaimer in the
12		- * documentation and/or other materials provided with the distribution.
13		- * * Neither the name of Freescale Semiconductor nor the
14		- * names of its contributors may be used to endorse or promote products
15		- * derived from this software without specific prior written permission.
16		- *
17		- *
18		- * ALTERNATIVELY, this software may be distributed under the terms of the
19		- * GNU General Public License ("GPL") as published by the Free Software
20		- * Foundation, either version 2 of that License or (at your option) any
21		- * later version.
22		- *
23		- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24		- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25		- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26		- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27		- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28		- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29		- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30		- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31		- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32		- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33		- */
34		-
35		-/dts-v1/;
36		-
37		-/ {
38		- compatible = "fsl,P2040";
39		- #address-cells = <2>;
40		- #size-cells = <2>;
41		- interrupt-parent = <&mpic>;
42		-
43		- aliases {
44		- ccsr = &soc;
45		-
46		- serial0 = &serial0;
47		- serial1 = &serial1;
48		- serial2 = &serial2;
49		- serial3 = &serial3;
50		- pci0 = &pci0;
51		- pci1 = &pci1;
52		- pci2 = &pci2;
53		- usb0 = &usb0;
54		- usb1 = &usb1;
55		- dma0 = &dma0;
56		- dma1 = &dma1;
57		- sdhc = &sdhc;
58		- msi0 = &msi0;
59		- msi1 = &msi1;
60		- msi2 = &msi2;
61		-
62		- crypto = &crypto;
63		- sec_jr0 = &sec_jr0;
64		- sec_jr1 = &sec_jr1;
65		- sec_jr2 = &sec_jr2;
66		- sec_jr3 = &sec_jr3;
67		- rtic_a = &rtic_a;
68		- rtic_b = &rtic_b;
69		- rtic_c = &rtic_c;
70		- rtic_d = &rtic_d;
71		- sec_mon = &sec_mon;
72		- };
73		-
74		- cpus {
75		- #address-cells = <1>;
76		- #size-cells = <0>;
77		-
78		- cpu0: PowerPC,e500mc@0 {
79		- device_type = "cpu";
80		- reg = <0>;
81		- next-level-cache = <&L2_0>;
82		- L2_0: l2-cache {
83		- next-level-cache = <&cpc>;
84		- };
85		- };
86		- cpu1: PowerPC,e500mc@1 {
87		- device_type = "cpu";
88		- reg = <1>;
89		- next-level-cache = <&L2_1>;
90		- L2_1: l2-cache {
91		- next-level-cache = <&cpc>;
92		- };
93		- };
94		- cpu2: PowerPC,e500mc@2 {
95		- device_type = "cpu";
96		- reg = <2>;
97		- next-level-cache = <&L2_2>;
98		- L2_2: l2-cache {
99		- next-level-cache = <&cpc>;
100		- };
101		- };
102		- cpu3: PowerPC,e500mc@3 {
103		- device_type = "cpu";
104		- reg = <3>;
105		- next-level-cache = <&L2_3>;
106		- L2_3: l2-cache {
107		- next-level-cache = <&cpc>;
108		- };
109		- };
110		- };
111		-
112		- soc: soc@ffe000000 {
113		- #address-cells = <1>;
114		- #size-cells = <1>;
115		- device_type = "soc";
116		- compatible = "simple-bus";
117		- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
118		- reg = <0xf 0xfe000000 0 0x00001000>;
119		-
120		- soc-sram-error {
121		- compatible = "fsl,soc-sram-error";
122		- interrupts = <16 2 1 29>;
123		- };
124		-
125		- corenet-law@0 {
126		- compatible = "fsl,corenet-law";
127		- reg = <0x0 0x1000>;
128		- fsl,num-laws = <32>;
129		- };
130		-
131		- memory-controller@8000 {
132		- compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
133		- reg = <0x8000 0x1000>;
134		- interrupts = <16 2 1 23>;
135		- };
136		-
137		- cpc: l3-cache-controller@10000 {
138		- compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
139		- reg = <0x10000 0x1000>;
140		- interrupts = <16 2 1 27>;
141		- };
142		-
143		- corenet-cf@18000 {
144		- compatible = "fsl,corenet-cf";
145		- reg = <0x18000 0x1000>;
146		- interrupts = <16 2 1 31>;
147		- fsl,ccf-num-csdids = <32>;
148		- fsl,ccf-num-snoopids = <32>;
149		- };
150		-
151		- iommu@20000 {
152		- compatible = "fsl,pamu-v1.0", "fsl,pamu";
153		- reg = <0x20000 0x4000>;
154		- interrupts = <
155		- 24 2 0 0
156		- 16 2 1 30>;
157		- };
158		-
159		- mpic: pic@40000 {
160		- clock-frequency = <0>;
161		- interrupt-controller;
162		- #address-cells = <0>;
163		- #interrupt-cells = <4>;
164		- reg = <0x40000 0x40000>;
165		- compatible = "fsl,mpic", "chrp,open-pic";
166		- device_type = "open-pic";
167		- };
168		-
169		- msi0: msi@41600 {
170		- compatible = "fsl,mpic-msi";
171		- reg = <0x41600 0x200>;
172		- msi-available-ranges = <0 0x100>;
173		- interrupts = <
174		- 0xe0 0 0 0
175		- 0xe1 0 0 0
176		- 0xe2 0 0 0
177		- 0xe3 0 0 0
178		- 0xe4 0 0 0
179		- 0xe5 0 0 0
180		- 0xe6 0 0 0
181		- 0xe7 0 0 0>;
182		- };
183		-
184		- msi1: msi@41800 {
185		- compatible = "fsl,mpic-msi";
186		- reg = <0x41800 0x200>;
187		- msi-available-ranges = <0 0x100>;
188		- interrupts = <
189		- 0xe8 0 0 0
190		- 0xe9 0 0 0
191		- 0xea 0 0 0
192		- 0xeb 0 0 0
193		- 0xec 0 0 0
194		- 0xed 0 0 0
195		- 0xee 0 0 0
196		- 0xef 0 0 0>;
197		- };
198		-
199		- msi2: msi@41a00 {
200		- compatible = "fsl,mpic-msi";
201		- reg = <0x41a00 0x200>;
202		- msi-available-ranges = <0 0x100>;
203		- interrupts = <
204		- 0xf0 0 0 0
205		- 0xf1 0 0 0
206		- 0xf2 0 0 0
207		- 0xf3 0 0 0
208		- 0xf4 0 0 0
209		- 0xf5 0 0 0
210		- 0xf6 0 0 0
211		- 0xf7 0 0 0>;
212		- };
213		-
214		- guts: global-utilities@e0000 {
215		- compatible = "fsl,qoriq-device-config-1.0";
216		- reg = <0xe0000 0xe00>;
217		- fsl,has-rstcr;
218		- #sleep-cells = <1>;
219		- fsl,liodn-bits = <12>;
220		- };
221		-
222		- pins: global-utilities@e0e00 {
223		- compatible = "fsl,qoriq-pin-control-1.0";
224		- reg = <0xe0e00 0x200>;
225		- #sleep-cells = <2>;
226		- };
227		-
228		- clockgen: global-utilities@e1000 {
229		- compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
230		- reg = <0xe1000 0x1000>;
231		- clock-frequency = <0>;
232		- };
233		-
234		- rcpm: global-utilities@e2000 {
235		- compatible = "fsl,qoriq-rcpm-1.0";
236		- reg = <0xe2000 0x1000>;
237		- #sleep-cells = <1>;
238		- };
239		-
240		- sfp: sfp@e8000 {
241		- compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
242		- reg = <0xe8000 0x1000>;
243		- };
244		-
245		- serdes: serdes@ea000 {
246		- compatible = "fsl,p2040-serdes";
247		- reg = <0xea000 0x1000>;
248		- };
249		-
250		- dma0: dma@100300 {
251		- #address-cells = <1>;
252		- #size-cells = <1>;
253		- compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
254		- reg = <0x100300 0x4>;
255		- ranges = <0x0 0x100100 0x200>;
256		- cell-index = <0>;
257		- dma-channel@0 {
258		- compatible = "fsl,p2040-dma-channel",
259		- "fsl,eloplus-dma-channel";
260		- reg = <0x0 0x80>;
261		- cell-index = <0>;
262		- interrupts = <28 2 0 0>;
263		- };
264		- dma-channel@80 {
265		- compatible = "fsl,p2040-dma-channel",
266		- "fsl,eloplus-dma-channel";
267		- reg = <0x80 0x80>;
268		- cell-index = <1>;
269		- interrupts = <29 2 0 0>;
270		- };
271		- dma-channel@100 {
272		- compatible = "fsl,p2040-dma-channel",
273		- "fsl,eloplus-dma-channel";
274		- reg = <0x100 0x80>;
275		- cell-index = <2>;
276		- interrupts = <30 2 0 0>;
277		- };
278		- dma-channel@180 {
279		- compatible = "fsl,p2040-dma-channel",
280		- "fsl,eloplus-dma-channel";
281		- reg = <0x180 0x80>;
282		- cell-index = <3>;
283		- interrupts = <31 2 0 0>;
284		- };
285		- };
286		-
287		- dma1: dma@101300 {
288		- #address-cells = <1>;
289		- #size-cells = <1>;
290		- compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
291		- reg = <0x101300 0x4>;
292		- ranges = <0x0 0x101100 0x200>;
293		- cell-index = <1>;
294		- dma-channel@0 {
295		- compatible = "fsl,p2040-dma-channel",
296		- "fsl,eloplus-dma-channel";
297		- reg = <0x0 0x80>;
298		- cell-index = <0>;
299		- interrupts = <32 2 0 0>;
300		- };
301		- dma-channel@80 {
302		- compatible = "fsl,p2040-dma-channel",
303		- "fsl,eloplus-dma-channel";
304		- reg = <0x80 0x80>;
305		- cell-index = <1>;
306		- interrupts = <33 2 0 0>;
307		- };
308		- dma-channel@100 {
309		- compatible = "fsl,p2040-dma-channel",
310		- "fsl,eloplus-dma-channel";
311		- reg = <0x100 0x80>;
312		- cell-index = <2>;
313		- interrupts = <34 2 0 0>;
314		- };
315		- dma-channel@180 {
316		- compatible = "fsl,p2040-dma-channel",
317		- "fsl,eloplus-dma-channel";
318		- reg = <0x180 0x80>;
319		- cell-index = <3>;
320		- interrupts = <35 2 0 0>;
321		- };
322		- };
323		-
324		- spi@110000 {
325		- #address-cells = <1>;
326		- #size-cells = <0>;
327		- compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
328		- reg = <0x110000 0x1000>;
329		- interrupts = <53 0x2 0 0>;
330		- fsl,espi-num-chipselects = <4>;
331		-
332		- };
333		-
334		- sdhc: sdhc@114000 {
335		- compatible = "fsl,p2040-esdhc", "fsl,esdhc";
336		- reg = <0x114000 0x1000>;
337		- interrupts = <48 2 0 0>;
338		- sdhci,auto-cmd12;
339		- clock-frequency = <0>;
340		- };
341		-
342		-
343		- i2c@118000 {
344		- #address-cells = <1>;
345		- #size-cells = <0>;
346		- cell-index = <0>;
347		- compatible = "fsl-i2c";
348		- reg = <0x118000 0x100>;
349		- interrupts = <38 2 0 0>;
350		- dfsrr;
351		- };
352		-
353		- i2c@118100 {
354		- #address-cells = <1>;
355		- #size-cells = <0>;
356		- cell-index = <1>;
357		- compatible = "fsl-i2c";
358		- reg = <0x118100 0x100>;
359		- interrupts = <38 2 0 0>;
360		- dfsrr;
361		- };
362		-
363		- i2c@119000 {
364		- #address-cells = <1>;
365		- #size-cells = <0>;
366		- cell-index = <2>;
367		- compatible = "fsl-i2c";
368		- reg = <0x119000 0x100>;
369		- interrupts = <39 2 0 0>;
370		- dfsrr;
371		- };
372		-
373		- i2c@119100 {
374		- #address-cells = <1>;
375		- #size-cells = <0>;
376		- cell-index = <3>;
377		- compatible = "fsl-i2c";
378		- reg = <0x119100 0x100>;
379		- interrupts = <39 2 0 0>;
380		- dfsrr;
381		- };
382		-
383		- serial0: serial@11c500 {
384		- cell-index = <0>;
385		- device_type = "serial";
386		- compatible = "ns16550";
387		- reg = <0x11c500 0x100>;
388		- clock-frequency = <0>;
389		- interrupts = <36 2 0 0>;
390		- };
391		-
392		- serial1: serial@11c600 {
393		- cell-index = <1>;
394		- device_type = "serial";
395		- compatible = "ns16550";
396		- reg = <0x11c600 0x100>;
397		- clock-frequency = <0>;
398		- interrupts = <36 2 0 0>;
399		- };
400		-
401		- serial2: serial@11d500 {
402		- cell-index = <2>;
403		- device_type = "serial";
404		- compatible = "ns16550";
405		- reg = <0x11d500 0x100>;
406		- clock-frequency = <0>;
407		- interrupts = <37 2 0 0>;
408		- };
409		-
410		- serial3: serial@11d600 {
411		- cell-index = <3>;
412		- device_type = "serial";
413		- compatible = "ns16550";
414		- reg = <0x11d600 0x100>;
415		- clock-frequency = <0>;
416		- interrupts = <37 2 0 0>;
417		- };
418		-
419		- gpio0: gpio@130000 {
420		- compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
421		- reg = <0x130000 0x1000>;
422		- interrupts = <55 2 0 0>;
423		- #gpio-cells = <2>;
424		- gpio-controller;
425		- };
426		-
427		- usb0: usb@210000 {
428		- compatible = "fsl,p2040-usb2-mph",
429		- "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
430		- reg = <0x210000 0x1000>;
431		- #address-cells = <1>;
432		- #size-cells = <0>;
433		- interrupts = <44 0x2 0 0>;
434		- port0;
435		- };
436		-
437		- usb1: usb@211000 {
438		- compatible = "fsl,p2040-usb2-dr",
439		- "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
440		- reg = <0x211000 0x1000>;
441		- #address-cells = <1>;
442		- #size-cells = <0>;
443		- interrupts = <45 0x2 0 0>;
444		- };
445		-
446		- sata@220000 {
447		- compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
448		- reg = <0x220000 0x1000>;
449		- interrupts = <68 0x2 0 0>;
450		- };
451		-
452		- sata@221000 {
453		- compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
454		- reg = <0x221000 0x1000>;
455		- interrupts = <69 0x2 0 0>;
456		- };
457		-
458		- crypto: crypto@300000 {
459		- compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
460		- #address-cells = <1>;
461		- #size-cells = <1>;
462		- reg = <0x300000 0x10000>;
463		- ranges = <0 0x300000 0x10000>;
464		- interrupts = <92 2 0 0>;
465		-
466		- sec_jr0: jr@1000 {
467		- compatible = "fsl,sec-v4.2-job-ring",
468		- "fsl,sec-v4.0-job-ring";
469		- reg = <0x1000 0x1000>;
470		- interrupts = <88 2 0 0>;
471		- };
472		-
473		- sec_jr1: jr@2000 {
474		- compatible = "fsl,sec-v4.2-job-ring",
475		- "fsl,sec-v4.0-job-ring";
476		- reg = <0x2000 0x1000>;
477		- interrupts = <89 2 0 0>;
478		- };
479		-
480		- sec_jr2: jr@3000 {
481		- compatible = "fsl,sec-v4.2-job-ring",
482		- "fsl,sec-v4.0-job-ring";
483		- reg = <0x3000 0x1000>;
484		- interrupts = <90 2 0 0>;
485		- };
486		-
487		- sec_jr3: jr@4000 {
488		- compatible = "fsl,sec-v4.2-job-ring",
489		- "fsl,sec-v4.0-job-ring";
490		- reg = <0x4000 0x1000>;
491		- interrupts = <91 2 0 0>;
492		- };
493		-
494		- rtic@6000 {
495		- compatible = "fsl,sec-v4.2-rtic",
496		- "fsl,sec-v4.0-rtic";
497		- #address-cells = <1>;
498		- #size-cells = <1>;
499		- reg = <0x6000 0x100>;
500		- ranges = <0x0 0x6100 0xe00>;
501		-
502		- rtic_a: rtic-a@0 {
503		- compatible = "fsl,sec-v4.2-rtic-memory",
504		- "fsl,sec-v4.0-rtic-memory";
505		- reg = <0x00 0x20 0x100 0x80>;
506		- };
507		-
508		- rtic_b: rtic-b@20 {
509		- compatible = "fsl,sec-v4.2-rtic-memory",
510		- "fsl,sec-v4.0-rtic-memory";
511		- reg = <0x20 0x20 0x200 0x80>;
512		- };
513		-
514		- rtic_c: rtic-c@40 {
515		- compatible = "fsl,sec-v4.2-rtic-memory",
516		- "fsl,sec-v4.0-rtic-memory";
517		- reg = <0x40 0x20 0x300 0x80>;
518		- };
519		-
520		- rtic_d: rtic-d@60 {
521		- compatible = "fsl,sec-v4.2-rtic-memory",
522		- "fsl,sec-v4.0-rtic-memory";
523		- reg = <0x60 0x20 0x500 0x80>;
524		- };
525		- };
526		- };
527		-
528		- sec_mon: sec_mon@314000 {
529		- compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
530		- reg = <0x314000 0x1000>;
531		- interrupts = <93 2 0 0>;
532		- };
533		-
534		- };
535		-
536		- localbus@ffe124000 {
537		- compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
538		- interrupts = <25 2 0 0>;
539		- #address-cells = <2>;
540		- #size-cells = <1>;
541		- };
542		-
543		- pci0: pcie@ffe200000 {
544		- compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
545		- device_type = "pci";
546		- #size-cells = <2>;
547		- #address-cells = <3>;
548		- bus-range = <0x0 0xff>;
549		- clock-frequency = <0x1fca055>;
550		- fsl,msi = <&msi0>;
551		- interrupts = <16 2 1 15>;
552		- pcie@0 {
553		- reg = <0 0 0 0 0>;
554		- #interrupt-cells = <1>;
555		- #size-cells = <2>;
556		- #address-cells = <3>;
557		- device_type = "pci";
558		- interrupts = <16 2 1 15>;
559		- interrupt-map-mask = <0xf800 0 0 7>;
560		- interrupt-map = <
561		- /* IDSEL 0x0 */
562		- 0000 0 0 1 &mpic 40 1 0 0
563		- 0000 0 0 2 &mpic 1 1 0 0
564		- 0000 0 0 3 &mpic 2 1 0 0
565		- 0000 0 0 4 &mpic 3 1 0 0
566		- >;
567		- };
568		- };
569		-
570		- pci1: pcie@ffe201000 {
571		- compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
572		- device_type = "pci";
573		- #size-cells = <2>;
574		- #address-cells = <3>;
575		- bus-range = <0 0xff>;
576		- clock-frequency = <0x1fca055>;
577		- fsl,msi = <&msi1>;
578		- interrupts = <16 2 1 14>;
579		- pcie@0 {
580		- reg = <0 0 0 0 0>;
581		- #interrupt-cells = <1>;
582		- #size-cells = <2>;
583		- #address-cells = <3>;
584		- device_type = "pci";
585		- interrupts = <16 2 1 14>;
586		- interrupt-map-mask = <0xf800 0 0 7>;
587		- interrupt-map = <
588		- /* IDSEL 0x0 */
589		- 0000 0 0 1 &mpic 41 1 0 0
590		- 0000 0 0 2 &mpic 5 1 0 0
591		- 0000 0 0 3 &mpic 6 1 0 0
592		- 0000 0 0 4 &mpic 7 1 0 0
593		- >;
594		- };
595		- };
596		-
597		- pci2: pcie@ffe202000 {
598		- compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
599		- device_type = "pci";
600		- #size-cells = <2>;
601		- #address-cells = <3>;
602		- bus-range = <0x0 0xff>;
603		- clock-frequency = <0x1fca055>;
604		- fsl,msi = <&msi2>;
605		- interrupts = <16 2 1 13>;
606		- pcie@0 {
607		- reg = <0 0 0 0 0>;
608		- #interrupt-cells = <1>;
609		- #size-cells = <2>;
610		- #address-cells = <3>;
611		- device_type = "pci";
612		- interrupts = <16 2 1 13>;
613		- interrupt-map-mask = <0xf800 0 0 7>;
614		- interrupt-map = <
615		- /* IDSEL 0x0 */
616		- 0000 0 0 1 &mpic 42 1 0 0
617		- 0000 0 0 2 &mpic 9 1 0 0
618		- 0000 0 0 3 &mpic 10 1 0 0
619		- 0000 0 0 4 &mpic 11 1 0 0
620		- >;
621		- };
622		- };
623		-};
	1	+/*
	2	+ * P2041RDB Device Tree Source
	3	+ *
	4	+ * Copyright 2011 Freescale Semiconductor Inc.
	5	+ *
	6	+ * Redistribution and use in source and binary forms, with or without
	7	+ * modification, are permitted provided that the following conditions are met:
	8	+ * * Redistributions of source code must retain the above copyright
	9	+ * notice, this list of conditions and the following disclaimer.
	10	+ * * Redistributions in binary form must reproduce the above copyright
	11	+ * notice, this list of conditions and the following disclaimer in the
	12	+ * documentation and/or other materials provided with the distribution.
	13	+ * * Neither the name of Freescale Semiconductor nor the
	14	+ * names of its contributors may be used to endorse or promote products
	15	+ * derived from this software without specific prior written permission.
	16	+ *
	17	+ *
	18	+ * ALTERNATIVELY, this software may be distributed under the terms of the
	19	+ * GNU General Public License ("GPL") as published by the Free Software
	20	+ * Foundation, either version 2 of that License or (at your option) any
	21	+ * later version.
	22	+ *
	23	+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	+ */
	34	+
	35	+/include/ "p2041si.dtsi"
	36	+
	37	+/ {
	38	+ model = "fsl,P2041RDB";
	39	+ compatible = "fsl,P2041RDB";
	40	+ #address-cells = <2>;
	41	+ #size-cells = <2>;
	42	+ interrupt-parent = <&mpic>;
	43	+
	44	+ memory {
	45	+ device_type = "memory";
	46	+ };
	47	+
	48	+ soc: soc@ffe000000 {
	49	+ spi@110000 {
	50	+ flash@0 {
	51	+ #address-cells = <1>;
	52	+ #size-cells = <1>;
	53	+ compatible = "spansion,s25sl12801";
	54	+ reg = <0>;
	55	+ spi-max-frequency = <40000000>; /* input clock */
	56	+ partition@u-boot {
	57	+ label = "u-boot";
	58	+ reg = <0x00000000 0x00100000>;
	59	+ read-only;
	60	+ };
	61	+ partition@kernel {
	62	+ label = "kernel";
	63	+ reg = <0x00100000 0x00500000>;
	64	+ read-only;
	65	+ };
	66	+ partition@dtb {
	67	+ label = "dtb";
	68	+ reg = <0x00600000 0x00100000>;
	69	+ read-only;
	70	+ };
	71	+ partition@fs {
	72	+ label = "file system";
	73	+ reg = <0x00700000 0x00900000>;
	74	+ };
	75	+ };
	76	+ };
	77	+
	78	+ i2c@118000 {
	79	+ lm75b@48 {
	80	+ compatible = "nxp,lm75a";
	81	+ reg = <0x48>;
	82	+ };
	83	+ eeprom@50 {
	84	+ compatible = "at24,24c256";
	85	+ reg = <0x50>;
	86	+ };
	87	+ rtc@68 {
	88	+ compatible = "pericom,pt7c4338";
	89	+ reg = <0x68>;
	90	+ };
	91	+ };
	92	+
	93	+ i2c@118100 {
	94	+ eeprom@50 {
	95	+ compatible = "at24,24c256";
	96	+ reg = <0x50>;
	97	+ };
	98	+ };
	99	+
	100	+ usb1: usb@211000 {
	101	+ dr_mode = "host";
	102	+ };
	103	+ };
	104	+
	105	+ localbus@ffe124000 {
	106	+ reg = <0xf 0xfe124000 0 0x1000>;
	107	+ ranges = <0 0 0xf 0xe8000000 0x08000000>;
	108	+
	109	+ flash@0,0 {
	110	+ compatible = "cfi-flash";
	111	+ reg = <0 0 0x08000000>;
	112	+ bank-width = <2>;
	113	+ device-width = <2>;
	114	+ };
	115	+ };
	116	+
	117	+ pci0: pcie@ffe200000 {
	118	+ reg = <0xf 0xfe200000 0 0x1000>;
	119	+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
	120	+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
	121	+ pcie@0 {
	122	+ ranges = <0x02000000 0 0xe0000000
	123	+ 0x02000000 0 0xe0000000
	124	+ 0 0x20000000
	125	+
	126	+ 0x01000000 0 0x00000000
	127	+ 0x01000000 0 0x00000000
	128	+ 0 0x00010000>;
	129	+ };
	130	+ };
	131	+
	132	+ pci1: pcie@ffe201000 {
	133	+ reg = <0xf 0xfe201000 0 0x1000>;
	134	+ ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
	135	+ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
	136	+ pcie@0 {
	137	+ ranges = <0x02000000 0 0xe0000000
	138	+ 0x02000000 0 0xe0000000
	139	+ 0 0x20000000
	140	+
	141	+ 0x01000000 0 0x00000000
	142	+ 0x01000000 0 0x00000000
	143	+ 0 0x00010000>;
	144	+ };
	145	+ };
	146	+
	147	+ pci2: pcie@ffe202000 {
	148	+ reg = <0xf 0xfe202000 0 0x1000>;
	149	+ ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
	150	+ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
	151	+ pcie@0 {
	152	+ ranges = <0x02000000 0 0xe0000000
	153	+ 0x02000000 0 0xe0000000
	154	+ 0 0x20000000
	155	+
	156	+ 0x01000000 0 0x00000000
	157	+ 0x01000000 0 0x00000000
	158	+ 0 0x00010000>;
	159	+ };
	160	+ };
	161	+};
	1	+/*
	2	+ * P2041 Silicon Device Tree Source
	3	+ *
	4	+ * Copyright 2011 Freescale Semiconductor Inc.
	5	+ *
	6	+ * Redistribution and use in source and binary forms, with or without
	7	+ * modification, are permitted provided that the following conditions are met:
	8	+ * * Redistributions of source code must retain the above copyright
	9	+ * notice, this list of conditions and the following disclaimer.
	10	+ * * Redistributions in binary form must reproduce the above copyright
	11	+ * notice, this list of conditions and the following disclaimer in the
	12	+ * documentation and/or other materials provided with the distribution.
	13	+ * * Neither the name of Freescale Semiconductor nor the
	14	+ * names of its contributors may be used to endorse or promote products
	15	+ * derived from this software without specific prior written permission.
	16	+ *
	17	+ *
	18	+ * ALTERNATIVELY, this software may be distributed under the terms of the
	19	+ * GNU General Public License ("GPL") as published by the Free Software
	20	+ * Foundation, either version 2 of that License or (at your option) any
	21	+ * later version.
	22	+ *
	23	+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	+ */
	34	+
	35	+/dts-v1/;
	36	+
	37	+/ {
	38	+ compatible = "fsl,P2041";
	39	+ #address-cells = <2>;
	40	+ #size-cells = <2>;
	41	+ interrupt-parent = <&mpic>;
	42	+
	43	+ aliases {
	44	+ ccsr = &soc;
	45	+
	46	+ serial0 = &serial0;
	47	+ serial1 = &serial1;
	48	+ serial2 = &serial2;
	49	+ serial3 = &serial3;
	50	+ pci0 = &pci0;
	51	+ pci1 = &pci1;
	52	+ pci2 = &pci2;
	53	+ usb0 = &usb0;
	54	+ usb1 = &usb1;
	55	+ dma0 = &dma0;
	56	+ dma1 = &dma1;
	57	+ sdhc = &sdhc;
	58	+ msi0 = &msi0;
	59	+ msi1 = &msi1;
	60	+ msi2 = &msi2;
	61	+
	62	+ crypto = &crypto;
	63	+ sec_jr0 = &sec_jr0;
	64	+ sec_jr1 = &sec_jr1;
	65	+ sec_jr2 = &sec_jr2;
	66	+ sec_jr3 = &sec_jr3;
	67	+ rtic_a = &rtic_a;
	68	+ rtic_b = &rtic_b;
	69	+ rtic_c = &rtic_c;
	70	+ rtic_d = &rtic_d;
	71	+ sec_mon = &sec_mon;
	72	+ };
	73	+
	74	+ cpus {
	75	+ #address-cells = <1>;
	76	+ #size-cells = <0>;
	77	+
	78	+ cpu0: PowerPC,e500mc@0 {
	79	+ device_type = "cpu";
	80	+ reg = <0>;
	81	+ next-level-cache = <&L2_0>;
	82	+ L2_0: l2-cache {
	83	+ next-level-cache = <&cpc>;
	84	+ };
	85	+ };
	86	+ cpu1: PowerPC,e500mc@1 {
	87	+ device_type = "cpu";
	88	+ reg = <1>;
	89	+ next-level-cache = <&L2_1>;
	90	+ L2_1: l2-cache {
	91	+ next-level-cache = <&cpc>;
	92	+ };
	93	+ };
	94	+ cpu2: PowerPC,e500mc@2 {
	95	+ device_type = "cpu";
	96	+ reg = <2>;
	97	+ next-level-cache = <&L2_2>;
	98	+ L2_2: l2-cache {
	99	+ next-level-cache = <&cpc>;
	100	+ };
	101	+ };
	102	+ cpu3: PowerPC,e500mc@3 {
	103	+ device_type = "cpu";
	104	+ reg = <3>;
	105	+ next-level-cache = <&L2_3>;
	106	+ L2_3: l2-cache {
	107	+ next-level-cache = <&cpc>;
	108	+ };
	109	+ };
	110	+ };
	111	+
	112	+ soc: soc@ffe000000 {
	113	+ #address-cells = <1>;
	114	+ #size-cells = <1>;
	115	+ device_type = "soc";
	116	+ compatible = "simple-bus";
	117	+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
	118	+ reg = <0xf 0xfe000000 0 0x00001000>;
	119	+
	120	+ soc-sram-error {
	121	+ compatible = "fsl,soc-sram-error";
	122	+ interrupts = <16 2 1 29>;
	123	+ };
	124	+
	125	+ corenet-law@0 {
	126	+ compatible = "fsl,corenet-law";
	127	+ reg = <0x0 0x1000>;
	128	+ fsl,num-laws = <32>;
	129	+ };
	130	+
	131	+ memory-controller@8000 {
	132	+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
	133	+ reg = <0x8000 0x1000>;
	134	+ interrupts = <16 2 1 23>;
	135	+ };
	136	+
	137	+ cpc: l3-cache-controller@10000 {
	138	+ compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
	139	+ reg = <0x10000 0x1000>;
	140	+ interrupts = <16 2 1 27>;
	141	+ };
	142	+
	143	+ corenet-cf@18000 {
	144	+ compatible = "fsl,corenet-cf";
	145	+ reg = <0x18000 0x1000>;
	146	+ interrupts = <16 2 1 31>;
	147	+ fsl,ccf-num-csdids = <32>;
	148	+ fsl,ccf-num-snoopids = <32>;
	149	+ };
	150	+
	151	+ iommu@20000 {
	152	+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
	153	+ reg = <0x20000 0x4000>;
	154	+ interrupts = <
	155	+ 24 2 0 0
	156	+ 16 2 1 30>;
	157	+ };
	158	+
	159	+ mpic: pic@40000 {
	160	+ clock-frequency = <0>;
	161	+ interrupt-controller;
	162	+ #address-cells = <0>;
	163	+ #interrupt-cells = <4>;
	164	+ reg = <0x40000 0x40000>;
	165	+ compatible = "fsl,mpic", "chrp,open-pic";
	166	+ device_type = "open-pic";
	167	+ };
	168	+
	169	+ msi0: msi@41600 {
	170	+ compatible = "fsl,mpic-msi";
	171	+ reg = <0x41600 0x200>;
	172	+ msi-available-ranges = <0 0x100>;
	173	+ interrupts = <
	174	+ 0xe0 0 0 0
	175	+ 0xe1 0 0 0
	176	+ 0xe2 0 0 0
	177	+ 0xe3 0 0 0
	178	+ 0xe4 0 0 0
	179	+ 0xe5 0 0 0
	180	+ 0xe6 0 0 0
	181	+ 0xe7 0 0 0>;
	182	+ };
	183	+
	184	+ msi1: msi@41800 {
	185	+ compatible = "fsl,mpic-msi";
	186	+ reg = <0x41800 0x200>;
	187	+ msi-available-ranges = <0 0x100>;
	188	+ interrupts = <
	189	+ 0xe8 0 0 0
	190	+ 0xe9 0 0 0
	191	+ 0xea 0 0 0
	192	+ 0xeb 0 0 0
	193	+ 0xec 0 0 0
	194	+ 0xed 0 0 0
	195	+ 0xee 0 0 0
	196	+ 0xef 0 0 0>;
	197	+ };
	198	+
	199	+ msi2: msi@41a00 {
	200	+ compatible = "fsl,mpic-msi";
	201	+ reg = <0x41a00 0x200>;
	202	+ msi-available-ranges = <0 0x100>;
	203	+ interrupts = <
	204	+ 0xf0 0 0 0
	205	+ 0xf1 0 0 0
	206	+ 0xf2 0 0 0
	207	+ 0xf3 0 0 0
	208	+ 0xf4 0 0 0
	209	+ 0xf5 0 0 0
	210	+ 0xf6 0 0 0
	211	+ 0xf7 0 0 0>;
	212	+ };
	213	+
	214	+ guts: global-utilities@e0000 {
	215	+ compatible = "fsl,qoriq-device-config-1.0";
	216	+ reg = <0xe0000 0xe00>;
	217	+ fsl,has-rstcr;
	218	+ #sleep-cells = <1>;
	219	+ fsl,liodn-bits = <12>;
	220	+ };
	221	+
	222	+ pins: global-utilities@e0e00 {
	223	+ compatible = "fsl,qoriq-pin-control-1.0";
	224	+ reg = <0xe0e00 0x200>;
	225	+ #sleep-cells = <2>;
	226	+ };
	227	+
	228	+ clockgen: global-utilities@e1000 {
	229	+ compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
	230	+ reg = <0xe1000 0x1000>;
	231	+ clock-frequency = <0>;
	232	+ };
	233	+
	234	+ rcpm: global-utilities@e2000 {
	235	+ compatible = "fsl,qoriq-rcpm-1.0";
	236	+ reg = <0xe2000 0x1000>;
	237	+ #sleep-cells = <1>;
	238	+ };
	239	+
	240	+ sfp: sfp@e8000 {
	241	+ compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
	242	+ reg = <0xe8000 0x1000>;
	243	+ };
	244	+
	245	+ serdes: serdes@ea000 {
	246	+ compatible = "fsl,p2041-serdes";
	247	+ reg = <0xea000 0x1000>;
	248	+ };
	249	+
	250	+ dma0: dma@100300 {
	251	+ #address-cells = <1>;
	252	+ #size-cells = <1>;
	253	+ compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
	254	+ reg = <0x100300 0x4>;
	255	+ ranges = <0x0 0x100100 0x200>;
	256	+ cell-index = <0>;
	257	+ dma-channel@0 {
	258	+ compatible = "fsl,p2041-dma-channel",
	259	+ "fsl,eloplus-dma-channel";
	260	+ reg = <0x0 0x80>;
	261	+ cell-index = <0>;
	262	+ interrupts = <28 2 0 0>;
	263	+ };
	264	+ dma-channel@80 {
	265	+ compatible = "fsl,p2041-dma-channel",
	266	+ "fsl,eloplus-dma-channel";
	267	+ reg = <0x80 0x80>;
	268	+ cell-index = <1>;
	269	+ interrupts = <29 2 0 0>;
	270	+ };
	271	+ dma-channel@100 {
	272	+ compatible = "fsl,p2041-dma-channel",
	273	+ "fsl,eloplus-dma-channel";
	274	+ reg = <0x100 0x80>;
	275	+ cell-index = <2>;
	276	+ interrupts = <30 2 0 0>;
	277	+ };
	278	+ dma-channel@180 {
	279	+ compatible = "fsl,p2041-dma-channel",
	280	+ "fsl,eloplus-dma-channel";
	281	+ reg = <0x180 0x80>;
	282	+ cell-index = <3>;
	283	+ interrupts = <31 2 0 0>;
	284	+ };
	285	+ };
	286	+
	287	+ dma1: dma@101300 {
	288	+ #address-cells = <1>;
	289	+ #size-cells = <1>;
	290	+ compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
	291	+ reg = <0x101300 0x4>;
	292	+ ranges = <0x0 0x101100 0x200>;
	293	+ cell-index = <1>;
	294	+ dma-channel@0 {
	295	+ compatible = "fsl,p2041-dma-channel",
	296	+ "fsl,eloplus-dma-channel";
	297	+ reg = <0x0 0x80>;
	298	+ cell-index = <0>;
	299	+ interrupts = <32 2 0 0>;
	300	+ };
	301	+ dma-channel@80 {
	302	+ compatible = "fsl,p2041-dma-channel",
	303	+ "fsl,eloplus-dma-channel";
	304	+ reg = <0x80 0x80>;
	305	+ cell-index = <1>;
	306	+ interrupts = <33 2 0 0>;
	307	+ };
	308	+ dma-channel@100 {
	309	+ compatible = "fsl,p2041-dma-channel",
	310	+ "fsl,eloplus-dma-channel";
	311	+ reg = <0x100 0x80>;
	312	+ cell-index = <2>;
	313	+ interrupts = <34 2 0 0>;
	314	+ };
	315	+ dma-channel@180 {
	316	+ compatible = "fsl,p2041-dma-channel",
	317	+ "fsl,eloplus-dma-channel";
	318	+ reg = <0x180 0x80>;
	319	+ cell-index = <3>;
	320	+ interrupts = <35 2 0 0>;
	321	+ };
	322	+ };
	323	+
	324	+ spi@110000 {
	325	+ #address-cells = <1>;
	326	+ #size-cells = <0>;
	327	+ compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
	328	+ reg = <0x110000 0x1000>;
	329	+ interrupts = <53 0x2 0 0>;
	330	+ fsl,espi-num-chipselects = <4>;
	331	+ };
	332	+
	333	+ sdhc: sdhc@114000 {
	334	+ compatible = "fsl,p2041-esdhc", "fsl,esdhc";
	335	+ reg = <0x114000 0x1000>;
	336	+ interrupts = <48 2 0 0>;
	337	+ sdhci,auto-cmd12;
	338	+ clock-frequency = <0>;
	339	+ };
	340	+
	341	+ i2c@118000 {
	342	+ #address-cells = <1>;
	343	+ #size-cells = <0>;
	344	+ cell-index = <0>;
	345	+ compatible = "fsl-i2c";
	346	+ reg = <0x118000 0x100>;
	347	+ interrupts = <38 2 0 0>;
	348	+ dfsrr;
	349	+ };
	350	+
	351	+ i2c@118100 {
	352	+ #address-cells = <1>;
	353	+ #size-cells = <0>;
	354	+ cell-index = <1>;
	355	+ compatible = "fsl-i2c";
	356	+ reg = <0x118100 0x100>;
	357	+ interrupts = <38 2 0 0>;
	358	+ dfsrr;
	359	+ };
	360	+
	361	+ i2c@119000 {
	362	+ #address-cells = <1>;
	363	+ #size-cells = <0>;
	364	+ cell-index = <2>;
	365	+ compatible = "fsl-i2c";
	366	+ reg = <0x119000 0x100>;
	367	+ interrupts = <39 2 0 0>;
	368	+ dfsrr;
	369	+ };
	370	+
	371	+ i2c@119100 {
	372	+ #address-cells = <1>;
	373	+ #size-cells = <0>;
	374	+ cell-index = <3>;
	375	+ compatible = "fsl-i2c";
	376	+ reg = <0x119100 0x100>;
	377	+ interrupts = <39 2 0 0>;
	378	+ dfsrr;
	379	+ };
	380	+
	381	+ serial0: serial@11c500 {
	382	+ cell-index = <0>;
	383	+ device_type = "serial";
	384	+ compatible = "ns16550";
	385	+ reg = <0x11c500 0x100>;
	386	+ clock-frequency = <0>;
	387	+ interrupts = <36 2 0 0>;
	388	+ };
	389	+
	390	+ serial1: serial@11c600 {
	391	+ cell-index = <1>;
	392	+ device_type = "serial";
	393	+ compatible = "ns16550";
	394	+ reg = <0x11c600 0x100>;
	395	+ clock-frequency = <0>;
	396	+ interrupts = <36 2 0 0>;
	397	+ };
	398	+
	399	+ serial2: serial@11d500 {
	400	+ cell-index = <2>;
	401	+ device_type = "serial";
	402	+ compatible = "ns16550";
	403	+ reg = <0x11d500 0x100>;
	404	+ clock-frequency = <0>;
	405	+ interrupts = <37 2 0 0>;
	406	+ };
	407	+
	408	+ serial3: serial@11d600 {
	409	+ cell-index = <3>;
	410	+ device_type = "serial";
	411	+ compatible = "ns16550";
	412	+ reg = <0x11d600 0x100>;
	413	+ clock-frequency = <0>;
	414	+ interrupts = <37 2 0 0>;
	415	+ };
	416	+
	417	+ gpio0: gpio@130000 {
	418	+ compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
	419	+ reg = <0x130000 0x1000>;
	420	+ interrupts = <55 2 0 0>;
	421	+ #gpio-cells = <2>;
	422	+ gpio-controller;
	423	+ };
	424	+
	425	+ usb0: usb@210000 {
	426	+ compatible = "fsl,p2041-usb2-mph",
	427	+ "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
	428	+ reg = <0x210000 0x1000>;
	429	+ #address-cells = <1>;
	430	+ #size-cells = <0>;
	431	+ interrupts = <44 0x2 0 0>;
	432	+ phy_type = "utmi";
	433	+ port0;
	434	+ };
	435	+
	436	+ usb1: usb@211000 {
	437	+ compatible = "fsl,p2041-usb2-dr",
	438	+ "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
	439	+ reg = <0x211000 0x1000>;
	440	+ #address-cells = <1>;
	441	+ #size-cells = <0>;
	442	+ interrupts = <45 0x2 0 0>;
	443	+ phy_type = "utmi";
	444	+ };
	445	+
	446	+ sata@220000 {
	447	+ compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
	448	+ reg = <0x220000 0x1000>;
	449	+ interrupts = <68 0x2 0 0>;
	450	+ };
	451	+
	452	+ sata@221000 {
	453	+ compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
	454	+ reg = <0x221000 0x1000>;
	455	+ interrupts = <69 0x2 0 0>;
	456	+ };
	457	+
	458	+ crypto: crypto@300000 {
	459	+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
	460	+ #address-cells = <1>;
	461	+ #size-cells = <1>;
	462	+ reg = <0x300000 0x10000>;
	463	+ ranges = <0 0x300000 0x10000>;
	464	+ interrupts = <92 2 0 0>;
	465	+
	466	+ sec_jr0: jr@1000 {
	467	+ compatible = "fsl,sec-v4.2-job-ring",
	468	+ "fsl,sec-v4.0-job-ring";
	469	+ reg = <0x1000 0x1000>;
	470	+ interrupts = <88 2 0 0>;
	471	+ };
	472	+
	473	+ sec_jr1: jr@2000 {
	474	+ compatible = "fsl,sec-v4.2-job-ring",
	475	+ "fsl,sec-v4.0-job-ring";
	476	+ reg = <0x2000 0x1000>;
	477	+ interrupts = <89 2 0 0>;
	478	+ };
	479	+
	480	+ sec_jr2: jr@3000 {
	481	+ compatible = "fsl,sec-v4.2-job-ring",
	482	+ "fsl,sec-v4.0-job-ring";
	483	+ reg = <0x3000 0x1000>;
	484	+ interrupts = <90 2 0 0>;
	485	+ };
	486	+
	487	+ sec_jr3: jr@4000 {
	488	+ compatible = "fsl,sec-v4.2-job-ring",
	489	+ "fsl,sec-v4.0-job-ring";
	490	+ reg = <0x4000 0x1000>;
	491	+ interrupts = <91 2 0 0>;
	492	+ };
	493	+
	494	+ rtic@6000 {
	495	+ compatible = "fsl,sec-v4.2-rtic",
	496	+ "fsl,sec-v4.0-rtic";
	497	+ #address-cells = <1>;
	498	+ #size-cells = <1>;
	499	+ reg = <0x6000 0x100>;
	500	+ ranges = <0x0 0x6100 0xe00>;
	501	+
	502	+ rtic_a: rtic-a@0 {
	503	+ compatible = "fsl,sec-v4.2-rtic-memory",
	504	+ "fsl,sec-v4.0-rtic-memory";
	505	+ reg = <0x00 0x20 0x100 0x80>;
	506	+ };
	507	+
	508	+ rtic_b: rtic-b@20 {
	509	+ compatible = "fsl,sec-v4.2-rtic-memory",
	510	+ "fsl,sec-v4.0-rtic-memory";
	511	+ reg = <0x20 0x20 0x200 0x80>;
	512	+ };
	513	+
	514	+ rtic_c: rtic-c@40 {
	515	+ compatible = "fsl,sec-v4.2-rtic-memory",
	516	+ "fsl,sec-v4.0-rtic-memory";
	517	+ reg = <0x40 0x20 0x300 0x80>;
	518	+ };
	519	+
	520	+ rtic_d: rtic-d@60 {
	521	+ compatible = "fsl,sec-v4.2-rtic-memory",
	522	+ "fsl,sec-v4.0-rtic-memory";
	523	+ reg = <0x60 0x20 0x500 0x80>;
	524	+ };
	525	+ };
	526	+ };
	527	+
	528	+ sec_mon: sec_mon@314000 {
	529	+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
	530	+ reg = <0x314000 0x1000>;
	531	+ interrupts = <93 2 0 0>;
	532	+ };
	533	+
	534	+ };
	535	+
	536	+ localbus@ffe124000 {
	537	+ compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
	538	+ interrupts = <25 2 0 0>;
	539	+ #address-cells = <2>;
	540	+ #size-cells = <1>;
	541	+ };
	542	+
	543	+ pci0: pcie@ffe200000 {
	544	+ compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
	545	+ device_type = "pci";
	546	+ #size-cells = <2>;
	547	+ #address-cells = <3>;
	548	+ bus-range = <0x0 0xff>;
	549	+ clock-frequency = <33333333>;
	550	+ fsl,msi = <&msi0>;
	551	+ interrupts = <16 2 1 15>;
	552	+ pcie@0 {
	553	+ reg = <0 0 0 0 0>;
	554	+ #interrupt-cells = <1>;
	555	+ #size-cells = <2>;
	556	+ #address-cells = <3>;
	557	+ device_type = "pci";
	558	+ interrupts = <16 2 1 15>;
	559	+ interrupt-map-mask = <0xf800 0 0 7>;
	560	+ interrupt-map = <
	561	+ /* IDSEL 0x0 */
	562	+ 0000 0 0 1 &mpic 40 1 0 0
	563	+ 0000 0 0 2 &mpic 1 1 0 0
	564	+ 0000 0 0 3 &mpic 2 1 0 0
	565	+ 0000 0 0 4 &mpic 3 1 0 0
	566	+ >;
	567	+ };
	568	+ };
	569	+
	570	+ pci1: pcie@ffe201000 {
	571	+ compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
	572	+ device_type = "pci";
	573	+ #size-cells = <2>;
	574	+ #address-cells = <3>;
	575	+ bus-range = <0 0xff>;
	576	+ clock-frequency = <33333333>;
	577	+ fsl,msi = <&msi1>;
	578	+ interrupts = <16 2 1 14>;
	579	+ pcie@0 {
	580	+ reg = <0 0 0 0 0>;
	581	+ #interrupt-cells = <1>;
	582	+ #size-cells = <2>;
	583	+ #address-cells = <3>;
	584	+ device_type = "pci";
	585	+ interrupts = <16 2 1 14>;
	586	+ interrupt-map-mask = <0xf800 0 0 7>;
	587	+ interrupt-map = <
	588	+ /* IDSEL 0x0 */
	589	+ 0000 0 0 1 &mpic 41 1 0 0
	590	+ 0000 0 0 2 &mpic 5 1 0 0
	591	+ 0000 0 0 3 &mpic 6 1 0 0
	592	+ 0000 0 0 4 &mpic 7 1 0 0
	593	+ >;
	594	+ };
	595	+ };
	596	+
	597	+ pci2: pcie@ffe202000 {
	598	+ compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
	599	+ device_type = "pci";
	600	+ #size-cells = <2>;
	601	+ #address-cells = <3>;
	602	+ bus-range = <0x0 0xff>;
	603	+ clock-frequency = <33333333>;
	604	+ fsl,msi = <&msi2>;
	605	+ interrupts = <16 2 1 13>;
	606	+ pcie@0 {
	607	+ reg = <0 0 0 0 0>;
	608	+ #interrupt-cells = <1>;
	609	+ #size-cells = <2>;
	610	+ #address-cells = <3>;
	611	+ device_type = "pci";
	612	+ interrupts = <16 2 1 13>;
	613	+ interrupt-map-mask = <0xf800 0 0 7>;
	614	+ interrupt-map = <
	615	+ /* IDSEL 0x0 */
	616	+ 0000 0 0 1 &mpic 42 1 0 0
	617	+ 0000 0 0 2 &mpic 9 1 0 0
	618	+ 0000 0 0 3 &mpic 10 1 0 0
	619	+ 0000 0 0 4 &mpic 11 1 0 0
	620	+ >;
	621	+ };
	622	+ };
	623	+};
...	...	@@ -23,7 +23,7 @@
23	23	CONFIG_MODULE_FORCE_UNLOAD=y
24	24	CONFIG_MODVERSIONS=y
25	25	# CONFIG_BLK_DEV_BSG is not set
26		-CONFIG_P2040_RDB=y
	26	+CONFIG_P2041_RDB=y
27	27	CONFIG_P3041_DS=y
28	28	CONFIG_P4080_DS=y
29	29	CONFIG_P5020_DS=y
...	...	@@ -171,8 +171,8 @@
171	171	help
172	172	This option enables support for the Wind River SBC8560 board
173	173
174		-config P2040_RDB
175		- bool "Freescale P2040 RDB"
	174	+config P2041_RDB
	175	+ bool "Freescale P2041 RDB"
176	176	select DEFAULT_UIMAGE
177	177	select PPC_E500MC
178	178	select PHYS_64BIT
...	...	@@ -182,7 +182,7 @@
182	182	select HAS_RAPIDIO
183	183	select PPC_EPAPR_HV_PIC
184	184	help
185		- This option enables support for the P2040 RDB board
	185	+ This option enables support for the P2041 RDB board
186	186
187	187	config P3041_DS
188	188	bool "Freescale P3041 DS"
...	...	@@ -13,7 +13,7 @@
13	13	obj-$(CONFIG_P1010_RDB) += p1010rdb.o
14	14	obj-$(CONFIG_P1022_DS) += p1022_ds.o
15	15	obj-$(CONFIG_P1023_RDS) += p1023_rds.o
16		-obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
	16	+obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
17	17	obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
18	18	obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
19	19	obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
1		-/*
2		- * P2040 RDB Setup
3		- *
4		- * Copyright 2011 Freescale Semiconductor Inc.
5		- *
6		- * This program is free software; you can redistribute it and/or modify it
7		- * under the terms of the GNU General Public License as published by the
8		- * Free Software Foundation; either version 2 of the License, or (at your
9		- * option) any later version.
10		- */
11		-
12		-#include <linux/kernel.h>
13		-#include <linux/pci.h>
14		-#include <linux/kdev_t.h>
15		-#include <linux/delay.h>
16		-#include <linux/interrupt.h>
17		-#include <linux/phy.h>
18		-
19		-#include <asm/system.h>
20		-#include <asm/time.h>
21		-#include <asm/machdep.h>
22		-#include <asm/pci-bridge.h>
23		-#include <mm/mmu_decl.h>
24		-#include <asm/prom.h>
25		-#include <asm/udbg.h>
26		-#include <asm/mpic.h>
27		-
28		-#include <linux/of_platform.h>
29		-#include <sysdev/fsl_soc.h>
30		-#include <sysdev/fsl_pci.h>
31		-#include <asm/ehv_pic.h>
32		-
33		-#include "corenet_ds.h"
34		-
35		-/*
36		- * Called very early, device-tree isn't unflattened
37		- */
38		-static int __init p2040_rdb_probe(void)
39		-{
40		- unsigned long root = of_get_flat_dt_root();
41		-#ifdef CONFIG_SMP
42		- extern struct smp_ops_t smp_85xx_ops;
43		-#endif
44		-
45		- if (of_flat_dt_is_compatible(root, "fsl,P2040RDB"))
46		- return 1;
47		-
48		- /* Check if we're running under the Freescale hypervisor */
49		- if (of_flat_dt_is_compatible(root, "fsl,P2040RDB-hv")) {
50		- ppc_md.init_IRQ = ehv_pic_init;
51		- ppc_md.get_irq = ehv_pic_get_irq;
52		- ppc_md.restart = fsl_hv_restart;
53		- ppc_md.power_off = fsl_hv_halt;
54		- ppc_md.halt = fsl_hv_halt;
55		-#ifdef CONFIG_SMP
56		- /*
57		- * Disable the timebase sync operations because we can't write
58		- * to the timebase registers under the hypervisor.
59		- */
60		- smp_85xx_ops.give_timebase = NULL;
61		- smp_85xx_ops.take_timebase = NULL;
62		-#endif
63		- return 1;
64		- }
65		-
66		- return 0;
67		-}
68		-
69		-define_machine(p2040_rdb) {
70		- .name = "P2040 RDB",
71		- .probe = p2040_rdb_probe,
72		- .setup_arch = corenet_ds_setup_arch,
73		- .init_IRQ = corenet_ds_pic_init,
74		-#ifdef CONFIG_PCI
75		- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
76		-#endif
77		- .get_irq = mpic_get_coreint_irq,
78		- .restart = fsl_rstcr_restart,
79		- .calibrate_decr = generic_calibrate_decr,
80		- .progress = udbg_progress,
81		- .power_save = e500_idle,
82		-};
83		-
84		-machine_device_initcall(p2040_rdb, corenet_ds_publish_devices);
85		-
86		-#ifdef CONFIG_SWIOTLB
87		-machine_arch_initcall(p2040_rdb, swiotlb_setup_bus_notifier);
88		-#endif
	1	+/*
	2	+ * P2041 RDB Setup
	3	+ *
	4	+ * Copyright 2011 Freescale Semiconductor Inc.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify it
	7	+ * under the terms of the GNU General Public License as published by the
	8	+ * Free Software Foundation; either version 2 of the License, or (at your
	9	+ * option) any later version.
	10	+ */
	11	+
	12	+#include <linux/kernel.h>
	13	+#include <linux/pci.h>
	14	+#include <linux/kdev_t.h>
	15	+#include <linux/delay.h>
	16	+#include <linux/interrupt.h>
	17	+#include <linux/phy.h>
	18	+
	19	+#include <asm/system.h>
	20	+#include <asm/time.h>
	21	+#include <asm/machdep.h>
	22	+#include <asm/pci-bridge.h>
	23	+#include <mm/mmu_decl.h>
	24	+#include <asm/prom.h>
	25	+#include <asm/udbg.h>
	26	+#include <asm/mpic.h>
	27	+
	28	+#include <linux/of_platform.h>
	29	+#include <sysdev/fsl_soc.h>
	30	+#include <sysdev/fsl_pci.h>
	31	+#include <asm/ehv_pic.h>
	32	+
	33	+#include "corenet_ds.h"
	34	+
	35	+/*
	36	+ * Called very early, device-tree isn't unflattened
	37	+ */
	38	+static int __init p2041_rdb_probe(void)
	39	+{
	40	+ unsigned long root = of_get_flat_dt_root();
	41	+#ifdef CONFIG_SMP
	42	+ extern struct smp_ops_t smp_85xx_ops;
	43	+#endif
	44	+
	45	+ if (of_flat_dt_is_compatible(root, "fsl,P2041RDB"))
	46	+ return 1;
	47	+
	48	+ /* Check if we're running under the Freescale hypervisor */
	49	+ if (of_flat_dt_is_compatible(root, "fsl,P2041RDB-hv")) {
	50	+ ppc_md.init_IRQ = ehv_pic_init;
	51	+ ppc_md.get_irq = ehv_pic_get_irq;
	52	+ ppc_md.restart = fsl_hv_restart;
	53	+ ppc_md.power_off = fsl_hv_halt;
	54	+ ppc_md.halt = fsl_hv_halt;
	55	+#ifdef CONFIG_SMP
	56	+ /*
	57	+ * Disable the timebase sync operations because we can't write
	58	+ * to the timebase registers under the hypervisor.
	59	+ */
	60	+ smp_85xx_ops.give_timebase = NULL;
	61	+ smp_85xx_ops.take_timebase = NULL;
	62	+#endif
	63	+ return 1;
	64	+ }
	65	+
	66	+ return 0;
	67	+}
	68	+
	69	+define_machine(p2041_rdb) {
	70	+ .name = "P2041 RDB",
	71	+ .probe = p2041_rdb_probe,
	72	+ .setup_arch = corenet_ds_setup_arch,
	73	+ .init_IRQ = corenet_ds_pic_init,
	74	+#ifdef CONFIG_PCI
	75	+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	76	+#endif
	77	+ .get_irq = mpic_get_coreint_irq,
	78	+ .restart = fsl_rstcr_restart,
	79	+ .calibrate_decr = generic_calibrate_decr,
	80	+ .progress = udbg_progress,
	81	+ .power_save = e500_idle,
	82	+};
	83	+
	84	+machine_device_initcall(p2041_rdb, corenet_ds_publish_devices);
	85	+
	86	+#ifdef CONFIG_SWIOTLB
	87	+machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
	88	+#endif