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Commit d50240a5f6ceaf690a77b0fccb17be51cfa151c2

Authored by Will Deacon
Committed by Catalin Marinas
1 parent 909e3ee411
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

arm64: mm: permit use of tagged pointers at EL0 

TCR.TBI0 can be used to cause hardware address translation to ignore the
top byte of userspace virtual addresses. Whilst not especially useful in
standard C programs, this can be used by JITs to `tag' pointers with
various pieces of metadata.

This patch enables this bit for AArch64 Linux, and adds a new file to
Documentation/arm64/ which describes some potential caveats when using
tagged virtual addresses.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Showing 4 changed files with 37 additions and 1 deletions Side-by-side Diff

Documentation/arm64/tagged-pointers.txt
Diff comments   View file @ d50240a
  1 + Tagged virtual addresses in AArch64 Linux
  2 + =========================================
  3 +
  4 +Author: Will Deacon <will.deacon@arm.com>
  5 +Date : 12 June 2013
  6 +
  7 +This document briefly describes the provision of tagged virtual
  8 +addresses in the AArch64 translation system and their potential uses
  9 +in AArch64 Linux.
  10 +
  11 +The kernel configures the translation tables so that translations made
  12 +via TTBR0 (i.e. userspace mappings) have the top byte (bits 63:56) of
  13 +the virtual address ignored by the translation hardware. This frees up
  14 +this byte for application use, with the following caveats:
  15 +
  16 + (1) The kernel requires that all user addresses passed to EL1
  17 + are tagged with tag 0x00. This means that any syscall
  18 + parameters containing user virtual addresses *must* have
  19 + their top byte cleared before trapping to the kernel.
  20 +
  21 + (2) Tags are not guaranteed to be preserved when delivering
  22 + signals. This means that signal handlers in applications
  23 + making use of tags cannot rely on the tag information for
  24 + user virtual addresses being maintained for fields inside
  25 + siginfo_t. One exception to this rule is for signals raised
  26 + in response to debug exceptions, where the tag information
  27 + will be preserved.
  28 +
  29 + (3) Special care should be taken when using tagged pointers,
  30 + since it is likely that C compilers will not hazard two
  31 + addresses differing only in the upper bits.
  32 +
  33 +The architecture prevents the use of a tagged PC, so the upper byte will
  34 +be set to a sign-extension of bit 55 on exception return.
arch/arm64/include/asm/pgtable-hwdef.h
Diff comments   View file @ d50240a
... ... @@ -122,6 +122,7 @@
122 122 #define TCR_TG1_64K (UL(1) << 30)
123 123 #define TCR_IPS_40BIT (UL(2) << 32)
124 124 #define TCR_ASID16 (UL(1) << 36)
  125 +#define TCR_TBI0 (UL(1) << 37)
125 126  
126 127 #endif
arch/arm64/kernel/entry.S
Diff comments   View file @ d50240a
... ... @@ -423,6 +423,7 @@
423 423 * Data abort handling
424 424 */
425 425 mrs x0, far_el1
  426 + bic x0, x0, #(0xff << 56)
426 427 disable_step x1
427 428 isb
428 429 enable_dbg
arch/arm64/mm/proc.S
Diff comments   View file @ d50240a
... ... @@ -147,7 +147,7 @@
147 147 * both user and kernel.
148 148 */
149 149 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
150   - TCR_ASID16 | (1 << 31)
  150 + TCR_ASID16 | TCR_TBI0 | (1 << 31)
151 151 #ifdef CONFIG_ARM64_64K_PAGES
152 152 orr x10, x10, TCR_TG0_64K
153 153 orr x10, x10, TCR_TG1_64K