mfd: Support AB9540 ab8500 variant

The AB9540 variant of the AB8500 is basically close enough to use the same driver. This adds the new registers and deviations for this new chip variant. Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@stericsson.com> Signed-off-by: Alex Macro <alex.macro@stericsson.com> Signed-off-by: Michel Jaouen <michel.jaouen@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

mfd: Support AB9540 ab8500 variant
The AB9540 variant of the AB8500 is basically close enough to use the same driver. This adds the new registers and deviations for this new chip variant. Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@stericsson.com> Signed-off-by: Alex Macro <alex.macro@stericsson.com> Signed-off-by: Michel Jaouen <michel.jaouen@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Linus Walleij · Samuel Ortiz
1 parent 2ced445e2d
Showing 6 changed files with 331 additions and 25 deletions Side-by-side Diff
arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
drivers/mfd/ab8500-core.c
include/linux/mfd/abx500/ab8500-gpio.h
include/linux/mfd/abx500/ab8500-sysctrl.h
include/linux/mfd/abx500/ab8500.h
include/linux/regulator/ab8500.h
@@ -13,7 +13,7 @@
  
 #define MOP500_AB8500_IRQ_BASE		IRQ_BOARD_START
 #define MOP500_AB8500_IRQ_END		(MOP500_AB8500_IRQ_BASE \
-					 + AB8500_NR_IRQS)
+					 + AB8500_MAX_NR_IRQS)
  
 /* TC35892 */
 #define TC35892_NR_INTERNAL_IRQS	8
@@ -32,6 +32,7 @@
 #define AB8500_IT_SOURCE6_REG		0x05
 #define AB8500_IT_SOURCE7_REG		0x06
 #define AB8500_IT_SOURCE8_REG		0x07
+#define AB9540_IT_SOURCE13_REG		0x0C
 #define AB8500_IT_SOURCE19_REG		0x12
 #define AB8500_IT_SOURCE20_REG		0x13
 #define AB8500_IT_SOURCE21_REG		0x14
@@ -53,6 +54,7 @@
 #define AB8500_IT_LATCH9_REG		0x28
 #define AB8500_IT_LATCH10_REG		0x29
 #define AB8500_IT_LATCH12_REG		0x2B
+#define AB9540_IT_LATCH13_REG		0x2C
 #define AB8500_IT_LATCH19_REG		0x32
 #define AB8500_IT_LATCH20_REG		0x33
 #define AB8500_IT_LATCH21_REG		0x34
@@ -95,6 +97,9 @@
  
 #define AB8500_TURN_ON_STATUS		0x00
  
+#define AB9540_MODEM_CTRL2_REG			0x23
+#define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT	BIT(2)
+
 /*
  * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
  * numbers are indexed into this array with (num / 8). The interupts are
@@ -108,6 +113,11 @@
 	0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
 };
  
+/* AB9540 support */
+static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
+	0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24,
+};
+
 static const char ab8500_version_str[][7] = {
 	[AB8500_VERSION_AB8500] = "AB8500",
 	[AB8500_VERSION_AB8505] = "AB8505",
@@ -354,7 +364,10 @@
 	int irq;
 	int num_irqs;
  
-	num_irqs = AB8500_NR_IRQS;
+	if (is_ab9540(ab8500))
+		num_irqs = AB9540_NR_IRQS;
+	else
+		num_irqs = AB8500_NR_IRQS;
  
 	for (irq = base; irq < base + num_irqs; irq++) {
 		irq_set_chip_data(irq, ab8500);
@@ -377,7 +390,10 @@
 	int irq;
 	int num_irqs;
  
-	num_irqs = AB8500_NR_IRQS;
+	if (is_ab9540(ab8500))
+		num_irqs = AB9540_NR_IRQS;
+	else
+		num_irqs = AB8500_NR_IRQS;
  
 	for (irq = base; irq < base + num_irqs; irq++) {
 #ifdef CONFIG_ARM
@@ -388,6 +404,7 @@
 	}
 }
  
+/* AB8500 GPIO Resources */
 static struct resource __devinitdata ab8500_gpio_resources[] = {
 	{
 		.name	= "GPIO_INT6",
@@ -397,6 +414,28 @@
 	}
 };
  
+/* AB9540 GPIO Resources */
+static struct resource __devinitdata ab9540_gpio_resources[] = {
+	{
+		.name	= "GPIO_INT6",
+		.start	= AB8500_INT_GPIO6R,
+		.end	= AB8500_INT_GPIO41F,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "GPIO_INT14",
+		.start	= AB9540_INT_GPIO50R,
+		.end	= AB9540_INT_GPIO54R,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "GPIO_INT15",
+		.start	= AB9540_INT_GPIO50F,
+		.end	= AB9540_INT_GPIO54F,
+		.flags	= IORESOURCE_IRQ,
+	}
+};
+
 static struct resource __devinitdata ab8500_gpadc_resources[] = {
 	{
 		.name	= "HW_CONV_END",
@@ -713,7 +752,7 @@
 	},
 };
  
-static struct mfd_cell __devinitdata ab8500_devs[] = {
+static struct mfd_cell __devinitdata abx500_common_devs[] = {
 #ifdef CONFIG_DEBUG_FS
 	{
 		.name = "ab8500-debug",
@@ -728,11 +767,6 @@
 		.name = "ab8500-regulator",
 	},
 	{
-		.name = "ab8500-gpio",
-		.num_resources = ARRAY_SIZE(ab8500_gpio_resources),
-		.resources = ab8500_gpio_resources,
-	},
-	{
 		.name = "ab8500-gpadc",
 		.num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
 		.resources = ab8500_gpadc_resources,
  
@@ -770,12 +804,8 @@
 	{
 		.name = "ab8500-codec",
 	},
+
 	{
-		.name = "ab8500-usb",
-		.num_resources = ARRAY_SIZE(ab8500_usb_resources),
-		.resources = ab8500_usb_resources,
-	},
-	{
 		.name = "ab8500-poweron-key",
 		.num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
 		.resources = ab8500_poweronkey_db_resources,
@@ -803,6 +833,32 @@
 	},
 };
  
+static struct mfd_cell __devinitdata ab8500_devs[] = {
+	{
+		.name = "ab8500-gpio",
+		.num_resources = ARRAY_SIZE(ab8500_gpio_resources),
+		.resources = ab8500_gpio_resources,
+	},
+	{
+		.name = "ab8500-usb",
+		.num_resources = ARRAY_SIZE(ab8500_usb_resources),
+		.resources = ab8500_usb_resources,
+	},
+};
+
+static struct mfd_cell __devinitdata ab9540_devs[] = {
+	{
+		.name = "ab8500-gpio",
+		.num_resources = ARRAY_SIZE(ab9540_gpio_resources),
+		.resources = ab9540_gpio_resources,
+	},
+	{
+		.name = "ab9540-usb",
+		.num_resources = ARRAY_SIZE(ab8500_usb_resources),
+		.resources = ab8500_usb_resources,
+	},
+};
+
 static ssize_t show_chip_id(struct device *dev,
 				struct device_attribute *attr, char *buf)
 {
  
@@ -864,9 +920,64 @@
 	return sprintf(buf, "%#x\n", value);
 }
  
+static ssize_t show_ab9540_dbbrstn(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct ab8500 *ab8500;
+	int ret;
+	u8 value;
+
+	ab8500 = dev_get_drvdata(dev);
+
+	ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
+		AB9540_MODEM_CTRL2_REG, &value);
+	if (ret < 0)
+		return ret;
+
+	return sprintf(buf, "%d\n",
+			(value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
+}
+
+static ssize_t store_ab9540_dbbrstn(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ab8500 *ab8500;
+	int ret = count;
+	int err;
+	u8 bitvalues;
+
+	ab8500 = dev_get_drvdata(dev);
+
+	if (count > 0) {
+		switch (buf[0]) {
+		case '0':
+			bitvalues = 0;
+			break;
+		case '1':
+			bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
+			break;
+		default:
+			goto exit;
+		}
+
+		err = mask_and_set_register_interruptible(ab8500,
+			AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
+			AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
+		if (err)
+			dev_info(ab8500->dev,
+				"Failed to set DBBRSTN %c, err %#x\n",
+				buf[0], err);
+	}
+
+exit:
+	return ret;
+}
+
 static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
 static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
 static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
+static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR,
+			show_ab9540_dbbrstn, store_ab9540_dbbrstn);
  
 static struct attribute *ab8500_sysfs_entries[] = {
 	&dev_attr_chip_id.attr,
  
@@ -875,10 +986,22 @@
 	NULL,
 };
  
+static struct attribute *ab9540_sysfs_entries[] = {
+	&dev_attr_chip_id.attr,
+	&dev_attr_switch_off_status.attr,
+	&dev_attr_turn_on_status.attr,
+	&dev_attr_dbbrstn.attr,
+	NULL,
+};
+
 static struct attribute_group ab8500_attr_group = {
 	.attrs	= ab8500_sysfs_entries,
 };
  
+static struct attribute_group ab9540_attr_group = {
+	.attrs	= ab9540_sysfs_entries,
+};
+
 int __devinit ab8500_init(struct ab8500 *ab8500, enum ab8500_version version)
 {
 	struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
@@ -915,8 +1038,14 @@
 			ab8500->chip_id >> 4,
 			ab8500->chip_id & 0x0F);
  
-	ab8500->mask_size = AB8500_NUM_IRQ_REGS;
-	ab8500->irq_reg_offset = ab8500_irq_regoffset;
+	/* Configure AB8500 or AB9540 IRQ */
+	if (is_ab9540(ab8500)) {
+		ab8500->mask_size = AB9540_NUM_IRQ_REGS;
+		ab8500->irq_reg_offset = ab9540_irq_regoffset;
+	} else {
+		ab8500->mask_size = AB8500_NUM_IRQ_REGS;
+		ab8500->irq_reg_offset = ab8500_irq_regoffset;
+	}
 	ab8500->mask = kzalloc(ab8500->mask_size, GFP_KERNEL);
 	if (!ab8500->mask)
 		return -ENOMEM;
  
  
  
  
  
@@ -982,18 +1111,35 @@
 			goto out_removeirq;
 	}
  
-	ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
-			      ARRAY_SIZE(ab8500_devs), NULL,
+	ret = mfd_add_devices(ab8500->dev, 0, abx500_common_devs,
+			      ARRAY_SIZE(abx500_common_devs), NULL,
 			      ab8500->irq_base);
+
 	if (ret)
 		goto out_freeirq;
  
-	ret = sysfs_create_group(&ab8500->dev->kobj, &ab8500_attr_group);
+	if (is_ab9540(ab8500))
+		ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
+			      ARRAY_SIZE(ab9540_devs), NULL,
+			      ab8500->irq_base);
+	else
+		ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
+			      ARRAY_SIZE(ab9540_devs), NULL,
+			      ab8500->irq_base);
 	if (ret)
+		goto out_freeirq;
+
+	if (is_ab9540(ab8500))
+		ret = sysfs_create_group(&ab8500->dev->kobj,
+					&ab9540_attr_group);
+	else
+		ret = sysfs_create_group(&ab8500->dev->kobj,
+					&ab8500_attr_group);
+	if (ret)
 		dev_err(ab8500->dev, "error creating sysfs entries\n");
+	else
+		return ret;
  
-	return ret;
-
 out_freeirq:
 	if (ab8500->irq_base)
 		free_irq(ab8500->irq, ab8500);
@@ -1010,7 +1156,10 @@
  
 int __devexit ab8500_exit(struct ab8500 *ab8500)
 {
-	sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
+	if (is_ab9540(ab8500))
+		sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group);
+	else
+		sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
 	mfd_remove_devices(ab8500->dev);
 	if (ab8500->irq_base) {
 		free_irq(ab8500->irq, ab8500);
@@ -10,12 +10,14 @@
  
 /*
  * Platform data to register a block: only the initial gpio/irq number.
+ * Array sizes are large enough to contain all AB8500 and AB9540 GPIO
+ * registers.
  */
  
 struct ab8500_gpio_platform_data {
 	int gpio_base;
 	u32 irq_base;
-	u8  config_reg[7];
+	u8  config_reg[8];
 };
  
 #endif /* _AB8500_GPIO_H */
@@ -71,6 +71,13 @@
 #define AB8500_SWATCTRL			0x230
 #define AB8500_HIQCLKCTRL		0x232
 #define AB8500_VSIMSYSCLKCTRL		0x233
+#define AB9540_SYSCLK12BUFCTRL		0x234
+#define AB9540_SYSCLK12CONFCTRL		0x235
+#define AB9540_SYSCLK12BUFCTRL2		0x236
+#define AB9540_SYSCLK12BUF1VALID	0x237
+#define AB9540_SYSCLK12BUF2VALID	0x238
+#define AB9540_SYSCLK12BUF3VALID	0x239
+#define AB9540_SYSCLK12BUF4VALID	0x23A
  
 /* Bits */
 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
@@ -250,6 +257,42 @@
 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
+
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
+
+#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
+
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
+
+#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
+
+#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
+
+#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
+
+#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
  
 #endif /* __AB8500_SYSCTRL_H */
@@ -57,8 +57,11 @@
  
 /*
  * Interrupts
+ * Values used to index into array ab8500_irq_regoffset[] defined in
+ * drivers/mdf/ab8500-core.c
  */
-
+/* Definitions for AB8500 and AB9540 */
+/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
 #define AB8500_INT_MAIN_EXT_CH_NOT_OK	0
 #define AB8500_INT_UN_PLUG_TV_DET	1
 #define AB8500_INT_PLUG_TV_DET		2
@@ -67,6 +70,7 @@
 #define AB8500_INT_PON_KEY2DB_R		5
 #define AB8500_INT_PON_KEY1DB_F		6
 #define AB8500_INT_PON_KEY1DB_R		7
+/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
 #define AB8500_INT_BATT_OVV		8
 #define AB8500_INT_MAIN_CH_UNPLUG_DET	10
 #define AB8500_INT_MAIN_CH_PLUG_DET	11
@@ -74,6 +78,7 @@
 #define AB8500_INT_USB_ID_DET_R		13
 #define AB8500_INT_VBUS_DET_F		14
 #define AB8500_INT_VBUS_DET_R		15
+/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
 #define AB8500_INT_VBUS_CH_DROP_END	16
 #define AB8500_INT_RTC_60S		17
 #define AB8500_INT_RTC_ALARM		18
@@ -81,6 +86,7 @@
 #define AB8500_INT_CH_WD_EXP		21
 #define AB8500_INT_VBUS_OVV		22
 #define AB8500_INT_MAIN_CH_DROP_END	23
+/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
 #define AB8500_INT_CCN_CONV_ACC		24
 #define AB8500_INT_INT_AUD		25
 #define AB8500_INT_CCEOC		26
@@ -89,6 +95,7 @@
 #define AB8500_INT_LOW_BAT_R		29
 #define AB8500_INT_BUP_CHG_NOT_OK	30
 #define AB8500_INT_BUP_CHG_OK		31
+/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
 #define AB8500_INT_GP_HW_ADC_CONV_END	32
 #define AB8500_INT_ACC_DETECT_1DB_F	33
 #define AB8500_INT_ACC_DETECT_1DB_R	34
@@ -97,6 +104,7 @@
 #define AB8500_INT_ACC_DETECT_21DB_F	37
 #define AB8500_INT_ACC_DETECT_21DB_R	38
 #define AB8500_INT_GP_SW_ADC_CONV_END	39
+/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
 #define AB8500_INT_GPIO6R		40
 #define AB8500_INT_GPIO7R		41
 #define AB8500_INT_GPIO8R		42
@@ -105,6 +113,7 @@
 #define AB8500_INT_GPIO11R		45
 #define AB8500_INT_GPIO12R		46
 #define AB8500_INT_GPIO13R		47
+/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
 #define AB8500_INT_GPIO24R		48
 #define AB8500_INT_GPIO25R		49
 #define AB8500_INT_GPIO36R		50
@@ -113,6 +122,7 @@
 #define AB8500_INT_GPIO39R		53
 #define AB8500_INT_GPIO40R		54
 #define AB8500_INT_GPIO41R		55
+/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
 #define AB8500_INT_GPIO6F		56
 #define AB8500_INT_GPIO7F		57
 #define AB8500_INT_GPIO8F		58
@@ -121,6 +131,7 @@
 #define AB8500_INT_GPIO11F		61
 #define AB8500_INT_GPIO12F		62
 #define AB8500_INT_GPIO13F		63
+/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
 #define AB8500_INT_GPIO24F		64
 #define AB8500_INT_GPIO25F		65
 #define AB8500_INT_GPIO36F		66
@@ -129,6 +140,7 @@
 #define AB8500_INT_GPIO39F		69
 #define AB8500_INT_GPIO40F		70
 #define AB8500_INT_GPIO41F		71
+/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
 #define AB8500_INT_ADP_SOURCE_ERROR	72
 #define AB8500_INT_ADP_SINK_ERROR	73
 #define AB8500_INT_ADP_PROBE_PLUG	74
  
  
  
  
  
  
@@ -136,30 +148,62 @@
 #define AB8500_INT_ADP_SENSE_OFF	76
 #define AB8500_INT_USB_PHY_POWER_ERR	78
 #define AB8500_INT_USB_LINK_STATUS	79
+/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
 #define AB8500_INT_BTEMP_LOW		80
 #define AB8500_INT_BTEMP_LOW_MEDIUM	81
 #define AB8500_INT_BTEMP_MEDIUM_HIGH	82
 #define AB8500_INT_BTEMP_HIGH		83
+/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
 #define AB8500_INT_USB_CHARGER_NOT_OK	89
 #define AB8500_INT_ID_WAKEUP_R		90
 #define AB8500_INT_ID_DET_R1R		92
 #define AB8500_INT_ID_DET_R2R		93
 #define AB8500_INT_ID_DET_R3R		94
 #define AB8500_INT_ID_DET_R4R		95
+/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
 #define AB8500_INT_ID_WAKEUP_F		96
 #define AB8500_INT_ID_DET_R1F		98
 #define AB8500_INT_ID_DET_R2F		99
 #define AB8500_INT_ID_DET_R3F		100
 #define AB8500_INT_ID_DET_R4F		101
 #define AB8500_INT_USB_CHG_DET_DONE	102
+/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
 #define AB8500_INT_USB_CH_TH_PROT_F	104
 #define AB8500_INT_USB_CH_TH_PROT_R    105
 #define AB8500_INT_MAIN_CH_TH_PROT_F   106
 #define AB8500_INT_MAIN_CH_TH_PROT_R	107
 #define AB8500_INT_USB_CHARGER_NOT_OKF	111
  
+/* Definitions for AB9540 */
+/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
+#define AB9540_INT_GPIO50R		113
+#define AB9540_INT_GPIO51R		114
+#define AB9540_INT_GPIO52R		115
+#define AB9540_INT_GPIO53R		116
+#define AB9540_INT_GPIO54R		117
+#define AB9540_INT_IEXT_CH_RF_BFN_R	118
+#define AB9540_INT_IEXT_CH_RF_BFN_F	119
+/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
+#define AB9540_INT_GPIO50F		121
+#define AB9540_INT_GPIO51F		122
+#define AB9540_INT_GPIO52F		123
+#define AB9540_INT_GPIO53F		124
+#define AB9540_INT_GPIO54F		125
+
+/*
+ * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
+ * entire platform. This is a "compile time" constant so this must be set to
+ * the largest possible value that may be encountered with different AB SOCs.
+ * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
+ * which is larger.
+ */
 #define AB8500_NR_IRQS			112
+#define AB9540_NR_IRQS			128
+/* This is set to the roof of any AB8500 chip variant IRQ counts */
+#define AB8500_MAX_NR_IRQS		AB9540_NR_IRQS
+
 #define AB8500_NUM_IRQ_REGS		14
+#define AB9540_NUM_IRQ_REGS		17
  
 /**
  * struct ab8500 - ab8500 internal structure
@@ -26,7 +26,26 @@
 	AB8500_NUM_REGULATORS,
 };
  
-/* AB8500 register initialization */
+/* AB9450 regulators */
+enum ab9540_regulator_id {
+	AB9540_LDO_AUX1,
+	AB9540_LDO_AUX2,
+	AB9540_LDO_AUX3,
+	AB9540_LDO_AUX4,
+	AB9540_LDO_INTCORE,
+	AB9540_LDO_TVOUT,
+	AB9540_LDO_USB,
+	AB9540_LDO_AUDIO,
+	AB9540_LDO_ANAMIC1,
+	AB9540_LDO_ANAMIC2,
+	AB9540_LDO_DMIC,
+	AB9540_LDO_ANA,
+	AB9540_SYSCLKREQ_2,
+	AB9540_SYSCLKREQ_4,
+	AB9540_NUM_REGULATORS,
+};
+
+/* AB8500 and AB9540 register initialization */
 struct ab8500_regulator_reg_init {
 	int id;
 	u8 value;
@@ -69,6 +88,55 @@
 	AB8500_REGUCTRLDISCH2,
 	AB8500_VSMPS1SEL1,
 	AB8500_NUM_REGULATOR_REGISTERS,
+};
+
+
+/* AB9540 registers */
+enum ab9540_regulator_reg {
+	AB9540_REGUREQUESTCTRL1,
+	AB9540_REGUREQUESTCTRL2,
+	AB9540_REGUREQUESTCTRL3,
+	AB9540_REGUREQUESTCTRL4,
+	AB9540_REGUSYSCLKREQ1HPVALID1,
+	AB9540_REGUSYSCLKREQ1HPVALID2,
+	AB9540_REGUHWHPREQ1VALID1,
+	AB9540_REGUHWHPREQ1VALID2,
+	AB9540_REGUHWHPREQ2VALID1,
+	AB9540_REGUHWHPREQ2VALID2,
+	AB9540_REGUSWHPREQVALID1,
+	AB9540_REGUSWHPREQVALID2,
+	AB9540_REGUSYSCLKREQVALID1,
+	AB9540_REGUSYSCLKREQVALID2,
+	AB9540_REGUVAUX4REQVALID,
+	AB9540_REGUMISC1,
+	AB9540_VAUDIOSUPPLY,
+	AB9540_REGUCTRL1VAMIC,
+	AB9540_VSMPS1REGU,
+	AB9540_VSMPS2REGU,
+	AB9540_VSMPS3REGU, /* NOTE! PRCMU register */
+	AB9540_VPLLVANAREGU,
+	AB9540_EXTSUPPLYREGU,
+	AB9540_VAUX12REGU,
+	AB9540_VRF1VAUX3REGU,
+	AB9540_VSMPS1SEL1,
+	AB9540_VSMPS1SEL2,
+	AB9540_VSMPS1SEL3,
+	AB9540_VSMPS2SEL1,
+	AB9540_VSMPS2SEL2,
+	AB9540_VSMPS2SEL3,
+	AB9540_VSMPS3SEL1, /* NOTE! PRCMU register */
+	AB9540_VSMPS3SEL2, /* NOTE! PRCMU register */
+	AB9540_VAUX1SEL,
+	AB9540_VAUX2SEL,
+	AB9540_VRF1VAUX3SEL,
+	AB9540_REGUCTRL2SPARE,
+	AB9540_VAUX4REQCTRL,
+	AB9540_VAUX4REGU,
+	AB9540_VAUX4SEL,
+	AB9540_REGUCTRLDISCH,
+	AB9540_REGUCTRLDISCH2,
+	AB9540_REGUCTRLDISCH3,
+	AB9540_NUM_REGULATOR_REGISTERS,
 };
  
 #endif
...	...	@@ -13,7 +13,7 @@
13	13
14	14	#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START
15	15	#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \
16		- + AB8500_NR_IRQS)
	16	+ + AB8500_MAX_NR_IRQS)
17	17
18	18	/* TC35892 */
19	19	#define TC35892_NR_INTERNAL_IRQS 8
...	...	@@ -32,6 +32,7 @@
32	32	#define AB8500_IT_SOURCE6_REG 0x05
33	33	#define AB8500_IT_SOURCE7_REG 0x06
34	34	#define AB8500_IT_SOURCE8_REG 0x07
	35	+#define AB9540_IT_SOURCE13_REG 0x0C
35	36	#define AB8500_IT_SOURCE19_REG 0x12
36	37	#define AB8500_IT_SOURCE20_REG 0x13
37	38	#define AB8500_IT_SOURCE21_REG 0x14
...	...	@@ -53,6 +54,7 @@
53	54	#define AB8500_IT_LATCH9_REG 0x28
54	55	#define AB8500_IT_LATCH10_REG 0x29
55	56	#define AB8500_IT_LATCH12_REG 0x2B
	57	+#define AB9540_IT_LATCH13_REG 0x2C
56	58	#define AB8500_IT_LATCH19_REG 0x32
57	59	#define AB8500_IT_LATCH20_REG 0x33
58	60	#define AB8500_IT_LATCH21_REG 0x34
...	...	@@ -95,6 +97,9 @@
95	97
96	98	#define AB8500_TURN_ON_STATUS 0x00
97	99
	100	+#define AB9540_MODEM_CTRL2_REG 0x23
	101	+#define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2)
	102	+
98	103	/*
99	104	* Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
100	105	* numbers are indexed into this array with (num / 8). The interupts are
...	...	@@ -108,6 +113,11 @@
108	113	0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
109	114	};
110	115
	116	+/* AB9540 support */
	117	+static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
	118	+ 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24,
	119	+};
	120	+
111	121	static const char ab8500_version_str[][7] = {
112	122	[AB8500_VERSION_AB8500] = "AB8500",
113	123	[AB8500_VERSION_AB8505] = "AB8505",
...	...	@@ -354,7 +364,10 @@
354	364	int irq;
355	365	int num_irqs;
356	366
357		- num_irqs = AB8500_NR_IRQS;
	367	+ if (is_ab9540(ab8500))
	368	+ num_irqs = AB9540_NR_IRQS;
	369	+ else
	370	+ num_irqs = AB8500_NR_IRQS;
358	371
359	372	for (irq = base; irq < base + num_irqs; irq++) {
360	373	irq_set_chip_data(irq, ab8500);
...	...	@@ -377,7 +390,10 @@
377	390	int irq;
378	391	int num_irqs;
379	392
380		- num_irqs = AB8500_NR_IRQS;
	393	+ if (is_ab9540(ab8500))
	394	+ num_irqs = AB9540_NR_IRQS;
	395	+ else
	396	+ num_irqs = AB8500_NR_IRQS;
381	397
382	398	for (irq = base; irq < base + num_irqs; irq++) {
383	399	#ifdef CONFIG_ARM
...	...	@@ -388,6 +404,7 @@
388	404	}
389	405	}
390	406
	407	+/* AB8500 GPIO Resources */
391	408	static struct resource __devinitdata ab8500_gpio_resources[] = {
392	409	{
393	410	.name = "GPIO_INT6",
...	...	@@ -397,6 +414,28 @@
397	414	}
398	415	};
399	416
	417	+/* AB9540 GPIO Resources */
	418	+static struct resource __devinitdata ab9540_gpio_resources[] = {
	419	+ {
	420	+ .name = "GPIO_INT6",
	421	+ .start = AB8500_INT_GPIO6R,
	422	+ .end = AB8500_INT_GPIO41F,
	423	+ .flags = IORESOURCE_IRQ,
	424	+ },
	425	+ {
	426	+ .name = "GPIO_INT14",
	427	+ .start = AB9540_INT_GPIO50R,
	428	+ .end = AB9540_INT_GPIO54R,
	429	+ .flags = IORESOURCE_IRQ,
	430	+ },
	431	+ {
	432	+ .name = "GPIO_INT15",
	433	+ .start = AB9540_INT_GPIO50F,
	434	+ .end = AB9540_INT_GPIO54F,
	435	+ .flags = IORESOURCE_IRQ,
	436	+ }
	437	+};
	438	+
400	439	static struct resource __devinitdata ab8500_gpadc_resources[] = {
401	440	{
402	441	.name = "HW_CONV_END",
...	...	@@ -713,7 +752,7 @@
713	752	},
714	753	};
715	754
716		-static struct mfd_cell __devinitdata ab8500_devs[] = {
	755	+static struct mfd_cell __devinitdata abx500_common_devs[] = {
717	756	#ifdef CONFIG_DEBUG_FS
718	757	{
719	758	.name = "ab8500-debug",
...	...	@@ -728,11 +767,6 @@
728	767	.name = "ab8500-regulator",
729	768	},
730	769	{
731		- .name = "ab8500-gpio",
732		- .num_resources = ARRAY_SIZE(ab8500_gpio_resources),
733		- .resources = ab8500_gpio_resources,
734		- },
735		- {
736	770	.name = "ab8500-gpadc",
737	771	.num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
738	772	.resources = ab8500_gpadc_resources,
739	773
...	...	@@ -770,12 +804,8 @@
770	804	{
771	805	.name = "ab8500-codec",
772	806	},
	807	+
773	808	{
774		- .name = "ab8500-usb",
775		- .num_resources = ARRAY_SIZE(ab8500_usb_resources),
776		- .resources = ab8500_usb_resources,
777		- },
778		- {
779	809	.name = "ab8500-poweron-key",
780	810	.num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
781	811	.resources = ab8500_poweronkey_db_resources,
...	...	@@ -803,6 +833,32 @@
803	833	},
804	834	};
805	835
	836	+static struct mfd_cell __devinitdata ab8500_devs[] = {
	837	+ {
	838	+ .name = "ab8500-gpio",
	839	+ .num_resources = ARRAY_SIZE(ab8500_gpio_resources),
	840	+ .resources = ab8500_gpio_resources,
	841	+ },
	842	+ {
	843	+ .name = "ab8500-usb",
	844	+ .num_resources = ARRAY_SIZE(ab8500_usb_resources),
	845	+ .resources = ab8500_usb_resources,
	846	+ },
	847	+};
	848	+
	849	+static struct mfd_cell __devinitdata ab9540_devs[] = {
	850	+ {
	851	+ .name = "ab8500-gpio",
	852	+ .num_resources = ARRAY_SIZE(ab9540_gpio_resources),
	853	+ .resources = ab9540_gpio_resources,
	854	+ },
	855	+ {
	856	+ .name = "ab9540-usb",
	857	+ .num_resources = ARRAY_SIZE(ab8500_usb_resources),
	858	+ .resources = ab8500_usb_resources,
	859	+ },
	860	+};
	861	+
806	862	static ssize_t show_chip_id(struct device *dev,
807	863	struct device_attribute attr, char buf)
808	864	{
809	865
...	...	@@ -864,9 +920,64 @@
864	920	return sprintf(buf, "%#x\n", value);
865	921	}
866	922
	923	+static ssize_t show_ab9540_dbbrstn(struct device *dev,
	924	+ struct device_attribute attr, char buf)
	925	+{
	926	+ struct ab8500 *ab8500;
	927	+ int ret;
	928	+ u8 value;
	929	+
	930	+ ab8500 = dev_get_drvdata(dev);
	931	+
	932	+ ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
	933	+ AB9540_MODEM_CTRL2_REG, &value);
	934	+ if (ret < 0)
	935	+ return ret;
	936	+
	937	+ return sprintf(buf, "%d\n",
	938	+ (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
	939	+}
	940	+
	941	+static ssize_t store_ab9540_dbbrstn(struct device *dev,
	942	+ struct device_attribute attr, const char buf, size_t count)
	943	+{
	944	+ struct ab8500 *ab8500;
	945	+ int ret = count;
	946	+ int err;
	947	+ u8 bitvalues;
	948	+
	949	+ ab8500 = dev_get_drvdata(dev);
	950	+
	951	+ if (count > 0) {
	952	+ switch (buf[0]) {
	953	+ case '0':
	954	+ bitvalues = 0;
	955	+ break;
	956	+ case '1':
	957	+ bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
	958	+ break;
	959	+ default:
	960	+ goto exit;
	961	+ }
	962	+
	963	+ err = mask_and_set_register_interruptible(ab8500,
	964	+ AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
	965	+ AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
	966	+ if (err)
	967	+ dev_info(ab8500->dev,
	968	+ "Failed to set DBBRSTN %c, err %#x\n",
	969	+ buf[0], err);
	970	+ }
	971	+
	972	+exit:
	973	+ return ret;
	974	+}
	975	+
867	976	static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
868	977	static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
869	978	static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
	979	+static DEVICE_ATTR(dbbrstn, S_IRUGO \| S_IWUSR,
	980	+ show_ab9540_dbbrstn, store_ab9540_dbbrstn);
870	981
871	982	static struct attribute *ab8500_sysfs_entries[] = {
872	983	&dev_attr_chip_id.attr,
873	984
...	...	@@ -875,10 +986,22 @@
875	986	NULL,
876	987	};
877	988
	989	+static struct attribute *ab9540_sysfs_entries[] = {
	990	+ &dev_attr_chip_id.attr,
	991	+ &dev_attr_switch_off_status.attr,
	992	+ &dev_attr_turn_on_status.attr,
	993	+ &dev_attr_dbbrstn.attr,
	994	+ NULL,
	995	+};
	996	+
878	997	static struct attribute_group ab8500_attr_group = {
879	998	.attrs = ab8500_sysfs_entries,
880	999	};
881	1000
	1001	+static struct attribute_group ab9540_attr_group = {
	1002	+ .attrs = ab9540_sysfs_entries,
	1003	+};
	1004	+
882	1005	int __devinit ab8500_init(struct ab8500 *ab8500, enum ab8500_version version)
883	1006	{
884	1007	struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
...	...	@@ -915,8 +1038,14 @@
915	1038	ab8500->chip_id >> 4,
916	1039	ab8500->chip_id & 0x0F);
917	1040
918		- ab8500->mask_size = AB8500_NUM_IRQ_REGS;
919		- ab8500->irq_reg_offset = ab8500_irq_regoffset;
	1041	+ /* Configure AB8500 or AB9540 IRQ */
	1042	+ if (is_ab9540(ab8500)) {
	1043	+ ab8500->mask_size = AB9540_NUM_IRQ_REGS;
	1044	+ ab8500->irq_reg_offset = ab9540_irq_regoffset;
	1045	+ } else {
	1046	+ ab8500->mask_size = AB8500_NUM_IRQ_REGS;
	1047	+ ab8500->irq_reg_offset = ab8500_irq_regoffset;
	1048	+ }
920	1049	ab8500->mask = kzalloc(ab8500->mask_size, GFP_KERNEL);
921	1050	if (!ab8500->mask)
922	1051	return -ENOMEM;
923	1052
924	1053
925	1054
926	1055
927	1056
...	...	@@ -982,18 +1111,35 @@
982	1111	goto out_removeirq;
983	1112	}
984	1113
985		- ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
986		- ARRAY_SIZE(ab8500_devs), NULL,
	1114	+ ret = mfd_add_devices(ab8500->dev, 0, abx500_common_devs,
	1115	+ ARRAY_SIZE(abx500_common_devs), NULL,
987	1116	ab8500->irq_base);
	1117	+
988	1118	if (ret)
989	1119	goto out_freeirq;
990	1120
991		- ret = sysfs_create_group(&ab8500->dev->kobj, &ab8500_attr_group);
	1121	+ if (is_ab9540(ab8500))
	1122	+ ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
	1123	+ ARRAY_SIZE(ab9540_devs), NULL,
	1124	+ ab8500->irq_base);
	1125	+ else
	1126	+ ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
	1127	+ ARRAY_SIZE(ab9540_devs), NULL,
	1128	+ ab8500->irq_base);
992	1129	if (ret)
	1130	+ goto out_freeirq;
	1131	+
	1132	+ if (is_ab9540(ab8500))
	1133	+ ret = sysfs_create_group(&ab8500->dev->kobj,
	1134	+ &ab9540_attr_group);
	1135	+ else
	1136	+ ret = sysfs_create_group(&ab8500->dev->kobj,
	1137	+ &ab8500_attr_group);
	1138	+ if (ret)
993	1139	dev_err(ab8500->dev, "error creating sysfs entries\n");
	1140	+ else
	1141	+ return ret;
994	1142
995		- return ret;
996		-
997	1143	out_freeirq:
998	1144	if (ab8500->irq_base)
999	1145	free_irq(ab8500->irq, ab8500);
...	...	@@ -1010,7 +1156,10 @@
1010	1156
1011	1157	int __devexit ab8500_exit(struct ab8500 *ab8500)
1012	1158	{
1013		- sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
	1159	+ if (is_ab9540(ab8500))
	1160	+ sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group);
	1161	+ else
	1162	+ sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
1014	1163	mfd_remove_devices(ab8500->dev);
1015	1164	if (ab8500->irq_base) {
1016	1165	free_irq(ab8500->irq, ab8500);
...	...	@@ -10,12 +10,14 @@
10	10
11	11	/*
12	12	* Platform data to register a block: only the initial gpio/irq number.
	13	+ * Array sizes are large enough to contain all AB8500 and AB9540 GPIO
	14	+ * registers.
13	15	*/
14	16
15	17	struct ab8500_gpio_platform_data {
16	18	int gpio_base;
17	19	u32 irq_base;
18		- u8 config_reg[7];
	20	+ u8 config_reg[8];
19	21	};
20	22
21	23	#endif /* _AB8500_GPIO_H */
...	...	@@ -71,6 +71,13 @@
71	71	#define AB8500_SWATCTRL 0x230
72	72	#define AB8500_HIQCLKCTRL 0x232
73	73	#define AB8500_VSIMSYSCLKCTRL 0x233
	74	+#define AB9540_SYSCLK12BUFCTRL 0x234
	75	+#define AB9540_SYSCLK12CONFCTRL 0x235
	76	+#define AB9540_SYSCLK12BUFCTRL2 0x236
	77	+#define AB9540_SYSCLK12BUF1VALID 0x237
	78	+#define AB9540_SYSCLK12BUF2VALID 0x238
	79	+#define AB9540_SYSCLK12BUF3VALID 0x239
	80	+#define AB9540_SYSCLK12BUF4VALID 0x23A
74	81
75	82	/* Bits */
76	83	#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
...	...	@@ -250,6 +257,42 @@
250	257	#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
251	258	#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
252	259	#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
	260	+
	261	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
	262	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
	263	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
	264	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
	265	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
	266	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
	267	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
	268	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
	269	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
	270	+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
	271	+
	272	+#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
	273	+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
	274	+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
	275	+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
	276	+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
	277	+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
	278	+#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
	279	+
	280	+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
	281	+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
	282	+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
	283	+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
	284	+
	285	+#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
	286	+#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
	287	+
	288	+#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
	289	+#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
	290	+
	291	+#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
	292	+#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
	293	+
	294	+#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
	295	+#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
253	296
254	297	#endif /* __AB8500_SYSCTRL_H */
...	...	@@ -57,8 +57,11 @@
57	57
58	58	/*
59	59	* Interrupts
	60	+ * Values used to index into array ab8500_irq_regoffset[] defined in
	61	+ * drivers/mdf/ab8500-core.c
60	62	*/
61		-
	63	+/* Definitions for AB8500 and AB9540 */
	64	+/* ab8500_irq_regoffset[0] -> IT[Source\|Latch\|Mask]1 */
62	65	#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
63	66	#define AB8500_INT_UN_PLUG_TV_DET 1
64	67	#define AB8500_INT_PLUG_TV_DET 2
...	...	@@ -67,6 +70,7 @@
67	70	#define AB8500_INT_PON_KEY2DB_R 5
68	71	#define AB8500_INT_PON_KEY1DB_F 6
69	72	#define AB8500_INT_PON_KEY1DB_R 7
	73	+/* ab8500_irq_regoffset[1] -> IT[Source\|Latch\|Mask]2 */
70	74	#define AB8500_INT_BATT_OVV 8
71	75	#define AB8500_INT_MAIN_CH_UNPLUG_DET 10
72	76	#define AB8500_INT_MAIN_CH_PLUG_DET 11
...	...	@@ -74,6 +78,7 @@
74	78	#define AB8500_INT_USB_ID_DET_R 13
75	79	#define AB8500_INT_VBUS_DET_F 14
76	80	#define AB8500_INT_VBUS_DET_R 15
	81	+/* ab8500_irq_regoffset[2] -> IT[Source\|Latch\|Mask]3 */
77	82	#define AB8500_INT_VBUS_CH_DROP_END 16
78	83	#define AB8500_INT_RTC_60S 17
79	84	#define AB8500_INT_RTC_ALARM 18
...	...	@@ -81,6 +86,7 @@
81	86	#define AB8500_INT_CH_WD_EXP 21
82	87	#define AB8500_INT_VBUS_OVV 22
83	88	#define AB8500_INT_MAIN_CH_DROP_END 23
	89	+/* ab8500_irq_regoffset[3] -> IT[Source\|Latch\|Mask]4 */
84	90	#define AB8500_INT_CCN_CONV_ACC 24
85	91	#define AB8500_INT_INT_AUD 25
86	92	#define AB8500_INT_CCEOC 26
...	...	@@ -89,6 +95,7 @@
89	95	#define AB8500_INT_LOW_BAT_R 29
90	96	#define AB8500_INT_BUP_CHG_NOT_OK 30
91	97	#define AB8500_INT_BUP_CHG_OK 31
	98	+/* ab8500_irq_regoffset[4] -> IT[Source\|Latch\|Mask]5 */
92	99	#define AB8500_INT_GP_HW_ADC_CONV_END 32
93	100	#define AB8500_INT_ACC_DETECT_1DB_F 33
94	101	#define AB8500_INT_ACC_DETECT_1DB_R 34
...	...	@@ -97,6 +104,7 @@
97	104	#define AB8500_INT_ACC_DETECT_21DB_F 37
98	105	#define AB8500_INT_ACC_DETECT_21DB_R 38
99	106	#define AB8500_INT_GP_SW_ADC_CONV_END 39
	107	+/* ab8500_irq_regoffset[5] -> IT[Source\|Latch\|Mask]7 */
100	108	#define AB8500_INT_GPIO6R 40
101	109	#define AB8500_INT_GPIO7R 41
102	110	#define AB8500_INT_GPIO8R 42
...	...	@@ -105,6 +113,7 @@
105	113	#define AB8500_INT_GPIO11R 45
106	114	#define AB8500_INT_GPIO12R 46
107	115	#define AB8500_INT_GPIO13R 47
	116	+/* ab8500_irq_regoffset[6] -> IT[Source\|Latch\|Mask]8 */
108	117	#define AB8500_INT_GPIO24R 48
109	118	#define AB8500_INT_GPIO25R 49
110	119	#define AB8500_INT_GPIO36R 50
...	...	@@ -113,6 +122,7 @@
113	122	#define AB8500_INT_GPIO39R 53
114	123	#define AB8500_INT_GPIO40R 54
115	124	#define AB8500_INT_GPIO41R 55
	125	+/* ab8500_irq_regoffset[7] -> IT[Source\|Latch\|Mask]9 */
116	126	#define AB8500_INT_GPIO6F 56
117	127	#define AB8500_INT_GPIO7F 57
118	128	#define AB8500_INT_GPIO8F 58
...	...	@@ -121,6 +131,7 @@
121	131	#define AB8500_INT_GPIO11F 61
122	132	#define AB8500_INT_GPIO12F 62
123	133	#define AB8500_INT_GPIO13F 63
	134	+/* ab8500_irq_regoffset[8] -> IT[Source\|Latch\|Mask]10 */
124	135	#define AB8500_INT_GPIO24F 64
125	136	#define AB8500_INT_GPIO25F 65
126	137	#define AB8500_INT_GPIO36F 66
...	...	@@ -129,6 +140,7 @@
129	140	#define AB8500_INT_GPIO39F 69
130	141	#define AB8500_INT_GPIO40F 70
131	142	#define AB8500_INT_GPIO41F 71
	143	+/* ab8500_irq_regoffset[9] -> IT[Source\|Latch\|Mask]12 */
132	144	#define AB8500_INT_ADP_SOURCE_ERROR 72
133	145	#define AB8500_INT_ADP_SINK_ERROR 73
134	146	#define AB8500_INT_ADP_PROBE_PLUG 74
135	147
136	148
137	149
138	150
139	151
140	152
...	...	@@ -136,30 +148,62 @@
136	148	#define AB8500_INT_ADP_SENSE_OFF 76
137	149	#define AB8500_INT_USB_PHY_POWER_ERR 78
138	150	#define AB8500_INT_USB_LINK_STATUS 79
	151	+/* ab8500_irq_regoffset[10] -> IT[Source\|Latch\|Mask]19 */
139	152	#define AB8500_INT_BTEMP_LOW 80
140	153	#define AB8500_INT_BTEMP_LOW_MEDIUM 81
141	154	#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
142	155	#define AB8500_INT_BTEMP_HIGH 83
	156	+/* ab8500_irq_regoffset[11] -> IT[Source\|Latch\|Mask]20 */
143	157	#define AB8500_INT_USB_CHARGER_NOT_OK 89
144	158	#define AB8500_INT_ID_WAKEUP_R 90
145	159	#define AB8500_INT_ID_DET_R1R 92
146	160	#define AB8500_INT_ID_DET_R2R 93
147	161	#define AB8500_INT_ID_DET_R3R 94
148	162	#define AB8500_INT_ID_DET_R4R 95
	163	+/* ab8500_irq_regoffset[12] -> IT[Source\|Latch\|Mask]21 */
149	164	#define AB8500_INT_ID_WAKEUP_F 96
150	165	#define AB8500_INT_ID_DET_R1F 98
151	166	#define AB8500_INT_ID_DET_R2F 99
152	167	#define AB8500_INT_ID_DET_R3F 100
153	168	#define AB8500_INT_ID_DET_R4F 101
154	169	#define AB8500_INT_USB_CHG_DET_DONE 102
	170	+/* ab8500_irq_regoffset[13] -> IT[Source\|Latch\|Mask]22 */
155	171	#define AB8500_INT_USB_CH_TH_PROT_F 104
156	172	#define AB8500_INT_USB_CH_TH_PROT_R 105
157	173	#define AB8500_INT_MAIN_CH_TH_PROT_F 106
158	174	#define AB8500_INT_MAIN_CH_TH_PROT_R 107
159	175	#define AB8500_INT_USB_CHARGER_NOT_OKF 111
160	176
	177	+/* Definitions for AB9540 */
	178	+/* ab8500_irq_regoffset[14] -> IT[Source\|Latch\|Mask]13 */
	179	+#define AB9540_INT_GPIO50R 113
	180	+#define AB9540_INT_GPIO51R 114
	181	+#define AB9540_INT_GPIO52R 115
	182	+#define AB9540_INT_GPIO53R 116
	183	+#define AB9540_INT_GPIO54R 117
	184	+#define AB9540_INT_IEXT_CH_RF_BFN_R 118
	185	+#define AB9540_INT_IEXT_CH_RF_BFN_F 119
	186	+/* ab8500_irq_regoffset[15] -> IT[Source\|Latch\|Mask]14 */
	187	+#define AB9540_INT_GPIO50F 121
	188	+#define AB9540_INT_GPIO51F 122
	189	+#define AB9540_INT_GPIO52F 123
	190	+#define AB9540_INT_GPIO53F 124
	191	+#define AB9540_INT_GPIO54F 125
	192	+
	193	+/*
	194	+ * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
	195	+ * entire platform. This is a "compile time" constant so this must be set to
	196	+ * the largest possible value that may be encountered with different AB SOCs.
	197	+ * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
	198	+ * which is larger.
	199	+ */
161	200	#define AB8500_NR_IRQS 112
	201	+#define AB9540_NR_IRQS 128
	202	+/* This is set to the roof of any AB8500 chip variant IRQ counts */
	203	+#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
	204	+
162	205	#define AB8500_NUM_IRQ_REGS 14
	206	+#define AB9540_NUM_IRQ_REGS 17
163	207
164	208	/**
165	209	* struct ab8500 - ab8500 internal structure
...	...	@@ -26,7 +26,26 @@
26	26	AB8500_NUM_REGULATORS,
27	27	};
28	28
29		-/* AB8500 register initialization */
	29	+/* AB9450 regulators */
	30	+enum ab9540_regulator_id {
	31	+ AB9540_LDO_AUX1,
	32	+ AB9540_LDO_AUX2,
	33	+ AB9540_LDO_AUX3,
	34	+ AB9540_LDO_AUX4,
	35	+ AB9540_LDO_INTCORE,
	36	+ AB9540_LDO_TVOUT,
	37	+ AB9540_LDO_USB,
	38	+ AB9540_LDO_AUDIO,
	39	+ AB9540_LDO_ANAMIC1,
	40	+ AB9540_LDO_ANAMIC2,
	41	+ AB9540_LDO_DMIC,
	42	+ AB9540_LDO_ANA,
	43	+ AB9540_SYSCLKREQ_2,
	44	+ AB9540_SYSCLKREQ_4,
	45	+ AB9540_NUM_REGULATORS,
	46	+};
	47	+
	48	+/* AB8500 and AB9540 register initialization */
30	49	struct ab8500_regulator_reg_init {
31	50	int id;
32	51	u8 value;
...	...	@@ -69,6 +88,55 @@
69	88	AB8500_REGUCTRLDISCH2,
70	89	AB8500_VSMPS1SEL1,
71	90	AB8500_NUM_REGULATOR_REGISTERS,
	91	+};
	92	+
	93	+
	94	+/* AB9540 registers */
	95	+enum ab9540_regulator_reg {
	96	+ AB9540_REGUREQUESTCTRL1,
	97	+ AB9540_REGUREQUESTCTRL2,
	98	+ AB9540_REGUREQUESTCTRL3,
	99	+ AB9540_REGUREQUESTCTRL4,
	100	+ AB9540_REGUSYSCLKREQ1HPVALID1,
	101	+ AB9540_REGUSYSCLKREQ1HPVALID2,
	102	+ AB9540_REGUHWHPREQ1VALID1,
	103	+ AB9540_REGUHWHPREQ1VALID2,
	104	+ AB9540_REGUHWHPREQ2VALID1,
	105	+ AB9540_REGUHWHPREQ2VALID2,
	106	+ AB9540_REGUSWHPREQVALID1,
	107	+ AB9540_REGUSWHPREQVALID2,
	108	+ AB9540_REGUSYSCLKREQVALID1,
	109	+ AB9540_REGUSYSCLKREQVALID2,
	110	+ AB9540_REGUVAUX4REQVALID,
	111	+ AB9540_REGUMISC1,
	112	+ AB9540_VAUDIOSUPPLY,
	113	+ AB9540_REGUCTRL1VAMIC,
	114	+ AB9540_VSMPS1REGU,
	115	+ AB9540_VSMPS2REGU,
	116	+ AB9540_VSMPS3REGU, /* NOTE! PRCMU register */
	117	+ AB9540_VPLLVANAREGU,
	118	+ AB9540_EXTSUPPLYREGU,
	119	+ AB9540_VAUX12REGU,
	120	+ AB9540_VRF1VAUX3REGU,
	121	+ AB9540_VSMPS1SEL1,
	122	+ AB9540_VSMPS1SEL2,
	123	+ AB9540_VSMPS1SEL3,
	124	+ AB9540_VSMPS2SEL1,
	125	+ AB9540_VSMPS2SEL2,
	126	+ AB9540_VSMPS2SEL3,
	127	+ AB9540_VSMPS3SEL1, /* NOTE! PRCMU register */
	128	+ AB9540_VSMPS3SEL2, /* NOTE! PRCMU register */
	129	+ AB9540_VAUX1SEL,
	130	+ AB9540_VAUX2SEL,
	131	+ AB9540_VRF1VAUX3SEL,
	132	+ AB9540_REGUCTRL2SPARE,
	133	+ AB9540_VAUX4REQCTRL,
	134	+ AB9540_VAUX4REGU,
	135	+ AB9540_VAUX4SEL,
	136	+ AB9540_REGUCTRLDISCH,
	137	+ AB9540_REGUCTRLDISCH2,
	138	+ AB9540_REGUCTRLDISCH3,
	139	+ AB9540_NUM_REGULATOR_REGISTERS,
72	140	};
73	141
74	142	#endif