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Commit d6e15eefcb334deac3e877fce80ace3b91b0ab69

Authored by Magnus Damm
Committed by Paul Mundt
1 parent ab61a68572
Exists in master and in 6 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

ARM: mach-shmobile: Break out INTC IRQ code 

Add INTC_IRQ_PINS_16() and INTC_IRQ_PINS_32() to mach/intc.h.
These macros define 16 or 32 external IRQ pins on a certain
memory base address. Can be used with INTCA or INTCS.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 1 changed file with 195 additions and 0 deletions Side-by-side Diff

arch/arm/mach-shmobile/include/mach/intc.h
Diff comments   View file @ d6e15ee
  1 +#ifndef __ASM_MACH_INTC_H
  2 +#define __ASM_MACH_INTC_H
  3 +#include <linux/sh_intc.h>
  4 +
  5 +#define INTC_IRQ_PINS_ENUM_16L(p) \
  6 + p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
  7 + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \
  8 + p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
  9 + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15
  10 +
  11 +#define INTC_IRQ_PINS_ENUM_16H(p) \
  12 + p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
  13 + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \
  14 + p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
  15 + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31
  16 +
  17 +#define INTC_IRQ_PINS_VECT_16L(p, vect) \
  18 + vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \
  19 + vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \
  20 + vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \
  21 + vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \
  22 + vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \
  23 + vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \
  24 + vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \
  25 + vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0)
  26 +
  27 +#define INTC_IRQ_PINS_VECT_16H(p, vect) \
  28 + vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \
  29 + vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \
  30 + vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \
  31 + vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \
  32 + vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \
  33 + vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \
  34 + vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \
  35 + vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0)
  36 +
  37 +#define INTC_IRQ_PINS_MASK_16L(p, base) \
  38 + { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \
  39 + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
  40 + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
  41 + { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \
  42 + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
  43 + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
  44 +
  45 +#define INTC_IRQ_PINS_MASK_16H(p, base) \
  46 + { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \
  47 + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
  48 + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
  49 + { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \
  50 + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
  51 + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
  52 +
  53 +#define INTC_IRQ_PINS_PRIO_16L(p, base) \
  54 + { base + 0x10, 0, 32, 4, /* INTPRI00A */ \
  55 + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
  56 + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
  57 + { base + 0x14, 0, 32, 4, /* INTPRI10A */ \
  58 + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
  59 + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
  60 +
  61 +#define INTC_IRQ_PINS_PRIO_16H(p, base) \
  62 + { base + 0x18, 0, 32, 4, /* INTPRI20A */ \
  63 + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
  64 + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
  65 + { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \
  66 + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
  67 + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
  68 +
  69 +#define INTC_IRQ_PINS_SENSE_16L(p, base) \
  70 + { base + 0x00, 32, 4, /* ICR1A */ \
  71 + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
  72 + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
  73 + { base + 0x04, 32, 4, /* ICR2A */ \
  74 + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
  75 + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
  76 +
  77 +#define INTC_IRQ_PINS_SENSE_16H(p, base) \
  78 + { base + 0x08, 32, 4, /* ICR3A */ \
  79 + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
  80 + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
  81 + { base + 0x0c, 32, 4, /* ICR4A */ \
  82 + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
  83 + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
  84 +
  85 +#define INTC_IRQ_PINS_ACK_16L(p, base) \
  86 + { base + 0x20, 0, 8, /* INTREQ00A */ \
  87 + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
  88 + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
  89 + { base + 0x24, 0, 8, /* INTREQ10A */ \
  90 + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
  91 + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
  92 +
  93 +#define INTC_IRQ_PINS_ACK_16H(p, base) \
  94 + { base + 0x28, 0, 8, /* INTREQ20A */ \
  95 + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
  96 + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
  97 + { base + 0x2c, 0, 8, /* INTREQ30A */ \
  98 + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
  99 + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
  100 +
  101 +#define INTC_IRQ_PINS_16(p, base, vect, str) \
  102 + \
  103 +static struct resource p ## _resources[] __initdata = { \
  104 + [0] = { \
  105 + .start = base, \
  106 + .end = base + 0x64, \
  107 + .flags = IORESOURCE_MEM, \
  108 + }, \
  109 +}; \
  110 + \
  111 +enum { \
  112 + p ## _UNUSED = 0, \
  113 + INTC_IRQ_PINS_ENUM_16L(p), \
  114 +}; \
  115 + \
  116 +static struct intc_vect p ## _vectors[] __initdata = { \
  117 + INTC_IRQ_PINS_VECT_16L(p, vect), \
  118 +}; \
  119 + \
  120 +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
  121 + INTC_IRQ_PINS_MASK_16L(p, base), \
  122 +}; \
  123 + \
  124 +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
  125 + INTC_IRQ_PINS_PRIO_16L(p, base), \
  126 +}; \
  127 + \
  128 +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
  129 + INTC_IRQ_PINS_SENSE_16L(p, base), \
  130 +}; \
  131 + \
  132 +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
  133 + INTC_IRQ_PINS_ACK_16L(p, base), \
  134 +}; \
  135 + \
  136 +static struct intc_desc p ## _desc __initdata = { \
  137 + .name = str, \
  138 + .resource = p ## _resources, \
  139 + .num_resources = ARRAY_SIZE(p ## _resources), \
  140 + .hw = INTC_HW_DESC(p ## _vectors, NULL, \
  141 + p ## _mask_registers, p ## _prio_registers, \
  142 + p ## _sense_registers, p ## _ack_registers) \
  143 +}
  144 +
  145 +#define INTC_IRQ_PINS_32(p, base, vect, str) \
  146 + \
  147 +static struct resource p ## _resources[] __initdata = { \
  148 + [0] = { \
  149 + .start = base, \
  150 + .end = base + 0x6c, \
  151 + .flags = IORESOURCE_MEM, \
  152 + }, \
  153 +}; \
  154 + \
  155 +enum { \
  156 + p ## _UNUSED = 0, \
  157 + INTC_IRQ_PINS_ENUM_16L(p), \
  158 + INTC_IRQ_PINS_ENUM_16H(p), \
  159 +}; \
  160 + \
  161 +static struct intc_vect p ## _vectors[] __initdata = { \
  162 + INTC_IRQ_PINS_VECT_16L(p, vect), \
  163 + INTC_IRQ_PINS_VECT_16H(p, vect), \
  164 +}; \
  165 + \
  166 +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
  167 + INTC_IRQ_PINS_MASK_16L(p, base), \
  168 + INTC_IRQ_PINS_MASK_16H(p, base), \
  169 +}; \
  170 + \
  171 +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
  172 + INTC_IRQ_PINS_PRIO_16L(p, base), \
  173 + INTC_IRQ_PINS_PRIO_16H(p, base), \
  174 +}; \
  175 + \
  176 +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
  177 + INTC_IRQ_PINS_SENSE_16L(p, base), \
  178 + INTC_IRQ_PINS_SENSE_16H(p, base), \
  179 +}; \
  180 + \
  181 +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
  182 + INTC_IRQ_PINS_ACK_16L(p, base), \
  183 + INTC_IRQ_PINS_ACK_16H(p, base), \
  184 +}; \
  185 + \
  186 +static struct intc_desc p ## _desc __initdata = { \
  187 + .name = str, \
  188 + .resource = p ## _resources, \
  189 + .num_resources = ARRAY_SIZE(p ## _resources), \
  190 + .hw = INTC_HW_DESC(p ## _vectors, NULL, \
  191 + p ## _mask_registers, p ## _prio_registers, \
  192 + p ## _sense_registers, p ## _ack_registers) \
  193 +}
  194 +
  195 +#endif /* __ASM_MACH_INTC_H */