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Commit d73d8011779292788def2cd2520d6f39d9b406de

Authored by Dan Williams
Committed by Russell King
1 parent e702a7155d
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files 

WARNING: arch/arm/mach-iop13xx/built-in.o - Section mismatch: reference to
.init.text:iop13xx_pcie_map_irq from .text between 'iop13xx_pci_setup' (at
offset 0x7fc) and 'iop13xx_map_pci_memory'

While fixing this warning I also recalled Adrian Bunk's recommendation to
not use inline in .c files, as 'iop13xx_map_pci_memory' is needlessly
inlined.

Removing 'inline' uncovered some dead code so that is cleaned up as well.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 12 changed files with 38 additions and 74 deletions Side-by-side Diff

arch/arm/mach-iop13xx/irq.c
Diff comments   View file @ d73d801
... ... @@ -30,77 +30,65 @@
30 30  
31 31 /* INTCTL0 CP6 R0 Page 4
32 32 */
33   -static inline u32 read_intctl_0(void)
  33 +static u32 read_intctl_0(void)
34 34 {
35 35 u32 val;
36 36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
37 37 return val;
38 38 }
39   -static inline void write_intctl_0(u32 val)
  39 +static void write_intctl_0(u32 val)
40 40 {
41 41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
42 42 }
43 43  
44 44 /* INTCTL1 CP6 R1 Page 4
45 45 */
46   -static inline u32 read_intctl_1(void)
  46 +static u32 read_intctl_1(void)
47 47 {
48 48 u32 val;
49 49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
50 50 return val;
51 51 }
52   -static inline void write_intctl_1(u32 val)
  52 +static void write_intctl_1(u32 val)
53 53 {
54 54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
55 55 }
56 56  
57 57 /* INTCTL2 CP6 R2 Page 4
58 58 */
59   -static inline u32 read_intctl_2(void)
  59 +static u32 read_intctl_2(void)
60 60 {
61 61 u32 val;
62 62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
63 63 return val;
64 64 }
65   -static inline void write_intctl_2(u32 val)
  65 +static void write_intctl_2(u32 val)
66 66 {
67 67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
68 68 }
69 69  
70 70 /* INTCTL3 CP6 R3 Page 4
71 71 */
72   -static inline u32 read_intctl_3(void)
  72 +static u32 read_intctl_3(void)
73 73 {
74 74 u32 val;
75 75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
76 76 return val;
77 77 }
78   -static inline void write_intctl_3(u32 val)
  78 +static void write_intctl_3(u32 val)
79 79 {
80 80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
81 81 }
82 82  
83 83 /* INTSTR0 CP6 R0 Page 5
84 84 */
85   -static inline u32 read_intstr_0(void)
  85 +static void write_intstr_0(u32 val)
86 86 {
87   - u32 val;
88   - asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
89   - return val;
90   -}
91   -static inline void write_intstr_0(u32 val)
92   -{
93 87 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
94 88 }
95 89  
96 90 /* INTSTR1 CP6 R1 Page 5
97 91 */
98   -static inline u32 read_intstr_1(void)
99   -{
100   - u32 val;
101   - asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
102   - return val;
103   -}
104 92 static void write_intstr_1(u32 val)
105 93 {
106 94 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
... ... @@ -108,12 +96,6 @@
108 96  
109 97 /* INTSTR2 CP6 R2 Page 5
110 98 */
111   -static inline u32 read_intstr_2(void)
112   -{
113   - u32 val;
114   - asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
115   - return val;
116   -}
117 99 static void write_intstr_2(u32 val)
118 100 {
119 101 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
... ... @@ -121,12 +103,6 @@
121 103  
122 104 /* INTSTR3 CP6 R3 Page 5
123 105 */
124   -static inline u32 read_intstr_3(void)
125   -{
126   - u32 val;
127   - asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
128   - return val;
129   -}
130 106 static void write_intstr_3(u32 val)
131 107 {
132 108 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
... ... @@ -134,12 +110,6 @@
134 110  
135 111 /* INTBASE CP6 R0 Page 2
136 112 */
137   -static inline u32 read_intbase(void)
138   -{
139   - u32 val;
140   - asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
141   - return val;
142   -}
143 113 static void write_intbase(u32 val)
144 114 {
145 115 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
... ... @@ -147,12 +117,6 @@
147 117  
148 118 /* INTSIZE CP6 R2 Page 2
149 119 */
150   -static inline u32 read_intsize(void)
151   -{
152   - u32 val;
153   - asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
154   - return val;
155   -}
156 120 static void write_intsize(u32 val)
157 121 {
158 122 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
arch/arm/mach-iop13xx/msi.c
Diff comments   View file @ d73d801
... ... @@ -30,52 +30,52 @@
30 30  
31 31 /* IMIPR0 CP6 R8 Page 1
32 32 */
33   -static inline u32 read_imipr_0(void)
  33 +static u32 read_imipr_0(void)
34 34 {
35 35 u32 val;
36 36 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
37 37 return val;
38 38 }
39   -static inline void write_imipr_0(u32 val)
  39 +static void write_imipr_0(u32 val)
40 40 {
41 41 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
42 42 }
43 43  
44 44 /* IMIPR1 CP6 R9 Page 1
45 45 */
46   -static inline u32 read_imipr_1(void)
  46 +static u32 read_imipr_1(void)
47 47 {
48 48 u32 val;
49 49 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
50 50 return val;
51 51 }
52   -static inline void write_imipr_1(u32 val)
  52 +static void write_imipr_1(u32 val)
53 53 {
54 54 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
55 55 }
56 56  
57 57 /* IMIPR2 CP6 R10 Page 1
58 58 */
59   -static inline u32 read_imipr_2(void)
  59 +static u32 read_imipr_2(void)
60 60 {
61 61 u32 val;
62 62 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
63 63 return val;
64 64 }
65   -static inline void write_imipr_2(u32 val)
  65 +static void write_imipr_2(u32 val)
66 66 {
67 67 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
68 68 }
69 69  
70 70 /* IMIPR3 CP6 R11 Page 1
71 71 */
72   -static inline u32 read_imipr_3(void)
  72 +static u32 read_imipr_3(void)
73 73 {
74 74 u32 val;
75 75 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
76 76 return val;
77 77 }
78   -static inline void write_imipr_3(u32 val)
  78 +static void write_imipr_3(u32 val)
79 79 {
80 80 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
81 81 }
arch/arm/mach-iop13xx/pci.c
Diff comments   View file @ d73d801
... ... @@ -144,7 +144,7 @@
144 144 }
145 145 }
146 146  
147   -static inline int iop13xx_atu_function(int atu)
  147 +static int iop13xx_atu_function(int atu)
148 148 {
149 149 int func = 0;
150 150 /* the function number depends on the value of the
... ... @@ -259,7 +259,7 @@
259 259 * data. Note that the data dependency on %0 encourages an abort
260 260 * to be detected before we return.
261 261 */
262   -static inline u32 iop13xx_atux_read(unsigned long addr)
  262 +static u32 iop13xx_atux_read(unsigned long addr)
263 263 {
264 264 u32 val;
265 265  
... ... @@ -387,7 +387,7 @@
387 387 return err;
388 388 }
389 389  
390   -static inline int __init
  390 +static int
391 391 iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
392 392 {
393 393 WARN_ON(idsel != 0);
... ... @@ -401,7 +401,7 @@
401 401 }
402 402 }
403 403  
404   -static inline u32 iop13xx_atue_read(unsigned long addr)
  404 +static u32 iop13xx_atue_read(unsigned long addr)
405 405 {
406 406 u32 val;
407 407  
arch/arm/mach-iop32x/glantank.c
Diff comments   View file @ d73d801
... ... @@ -75,7 +75,7 @@
75 75 #define INTC IRQ_IOP32X_XINT2
76 76 #define INTD IRQ_IOP32X_XINT3
77 77  
78   -static inline int __init
  78 +static int __init
79 79 glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
80 80 {
81 81 static int pci_irq_table[][4] = {
arch/arm/mach-iop32x/iq31244.c
Diff comments   View file @ d73d801
... ... @@ -104,7 +104,7 @@
104 104 /*
105 105 * EP80219/IQ31244 PCI.
106 106 */
107   -static inline int __init
  107 +static int __init
108 108 ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
109 109 {
110 110 int irq;
... ... @@ -140,7 +140,7 @@
140 140 .map_irq = ep80219_pci_map_irq,
141 141 };
142 142  
143   -static inline int __init
  143 +static int __init
144 144 iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
145 145 {
146 146 int irq;
arch/arm/mach-iop32x/iq80321.c
Diff comments   View file @ d73d801
... ... @@ -72,7 +72,7 @@
72 72 /*
73 73 * IQ80321 PCI.
74 74 */
75   -static inline int __init
  75 +static int __init
76 76 iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
77 77 {
78 78 int irq;
arch/arm/mach-iop32x/irq.c
Diff comments   View file @ d73d801
... ... @@ -21,12 +21,12 @@
21 21  
22 22 static u32 iop32x_mask;
23 23  
24   -static inline void intctl_write(u32 val)
  24 +static void intctl_write(u32 val)
25 25 {
26 26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
27 27 }
28 28  
29   -static inline void intstr_write(u32 val)
  29 +static void intstr_write(u32 val)
30 30 {
31 31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
32 32 }
arch/arm/mach-iop32x/n2100.c
Diff comments   View file @ d73d801
... ... @@ -76,7 +76,7 @@
76 76 /*
77 77 * N2100 PCI.
78 78 */
79   -static inline int __init
  79 +static int __init
80 80 n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
81 81 {
82 82 int irq;
arch/arm/mach-iop33x/iq80331.c
Diff comments   View file @ d73d801
... ... @@ -55,7 +55,7 @@
55 55 /*
56 56 * IQ80331 PCI.
57 57 */
58   -static inline int __init
  58 +static int __init
59 59 iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
60 60 {
61 61 int irq;
arch/arm/mach-iop33x/iq80332.c
Diff comments   View file @ d73d801
... ... @@ -55,7 +55,7 @@
55 55 /*
56 56 * IQ80332 PCI.
57 57 */
58   -static inline int __init
  58 +static int __init
59 59 iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
60 60 {
61 61 int irq;
arch/arm/mach-iop33x/irq.c
Diff comments   View file @ d73d801
... ... @@ -22,32 +22,32 @@
22 22 static u32 iop33x_mask0;
23 23 static u32 iop33x_mask1;
24 24  
25   -static inline void intctl0_write(u32 val)
  25 +static void intctl0_write(u32 val)
26 26 {
27 27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
28 28 }
29 29  
30   -static inline void intctl1_write(u32 val)
  30 +static void intctl1_write(u32 val)
31 31 {
32 32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
33 33 }
34 34  
35   -static inline void intstr0_write(u32 val)
  35 +static void intstr0_write(u32 val)
36 36 {
37 37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
38 38 }
39 39  
40   -static inline void intstr1_write(u32 val)
  40 +static void intstr1_write(u32 val)
41 41 {
42 42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
43 43 }
44 44  
45   -static inline void intbase_write(u32 val)
  45 +static void intbase_write(u32 val)
46 46 {
47 47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
48 48 }
49 49  
50   -static inline void intsize_write(u32 val)
  50 +static void intsize_write(u32 val)
51 51 {
52 52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
53 53 }
arch/arm/plat-iop/pci.c
Diff comments   View file @ d73d801
... ... @@ -88,7 +88,7 @@
88 88 * data. Note that the 4 nop's ensure that we are able to handle
89 89 * a delayed abort (in theory.)
90 90 */
91   -static inline u32 iop3xx_read(unsigned long addr)
  91 +static u32 iop3xx_read(unsigned long addr)
92 92 {
93 93 u32 val;
94 94  
... ... @@ -321,7 +321,7 @@
321 321 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
322 322 int init_atu;
323 323  
324   -void iop3xx_pci_preinit(void)
  324 +void __init iop3xx_pci_preinit(void)
325 325 {
326 326 if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
327 327 iop3xx_atu_disable();