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Commit d77fe6354d5b67f4d4eb62a47621da2b3ee3539e

Authored by Julian Stecklina
Committed by Avi Kivity
1 parent 60f9a9ef54
Exists in master and in 6 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

KVM: Allow aligned byte and word writes to IOAPIC registers. 

This fixes byte accesses to IOAPIC_REG_SELECT as mandated by at least the
ICH10 and Intel Series 5 chipset specs. It also makes ioapic_mmio_write
consistent with ioapic_mmio_read, which also allows byte and word accesses.

Signed-off-by: Julian Stecklina <js@alien8.de>
Signed-off-by: Avi Kivity <avi@redhat.com>

Showing 1 changed file with 12 additions and 3 deletions Side-by-side Diff

... ... @@ -332,9 +332,18 @@
332 332 (void*)addr, len, val);
333 333 ASSERT(!(addr & 0xf)); /* check alignment */
334 334  
335   - if (len == 4 || len == 8)
  335 + switch (len) {
  336 + case 8:
  337 + case 4:
336 338 data = *(u32 *) val;
337   - else {
  339 + break;
  340 + case 2:
  341 + data = *(u16 *) val;
  342 + break;
  343 + case 1:
  344 + data = *(u8 *) val;
  345 + break;
  346 + default:
338 347 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
339 348 return 0;
340 349 }
... ... @@ -343,7 +352,7 @@
343 352 spin_lock(&ioapic->lock);
344 353 switch (addr) {
345 354 case IOAPIC_REG_SELECT:
346   - ioapic->ioregsel = data;
  355 + ioapic->ioregsel = data & 0xFF; /* 8-bit register */
347 356 break;
348 357  
349 358 case IOAPIC_REG_WINDOW: