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Commit d9eda0fae1394ea1e1c59c94d4a120ad9c06e64a

Authored by Linus Torvalds
2 parents 418a95bc0e f8ab658b5d
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 "Two straggling fixes that I had missed as they were posted a couple of
  weeks ago, causing problems with interrupts (breaking them completely)
  on the CSR SiRF platforms"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm: prima2: drop nr_irqs in mach as we moved to linear irqdomain
  irqchip: sirf: move from legacy mode to linear irqdomain

Showing 2 changed files Side-by-side Diff

arch/arm/mach-prima2/common.c
Diff comments   View file @ d9eda0f
... ... @@ -42,7 +42,6 @@
42 42  
43 43 DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
44 44 /* Maintainer: Barry Song <baohua.song@csr.com> */
45   - .nr_irqs = 128,
46 45 .map_io = sirfsoc_map_io,
47 46 .init_time = sirfsoc_init_time,
48 47 .init_late = sirfsoc_init_late,
... ... @@ -59,7 +58,6 @@
59 58  
60 59 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
61 60 /* Maintainer: Barry Song <baohua.song@csr.com> */
62   - .nr_irqs = 128,
63 61 .map_io = sirfsoc_map_io,
64 62 .init_time = sirfsoc_init_time,
65 63 .dma_zone_size = SZ_256M,
drivers/irqchip/irq-sirfsoc.c
Diff comments   View file @ d9eda0f
... ... @@ -23,7 +23,7 @@
23 23 #define SIRFSOC_INT_RISC_LEVEL1 0x0024
24 24 #define SIRFSOC_INIT_IRQ_ID 0x0038
25 25  
26   -#define SIRFSOC_NUM_IRQS 128
  26 +#define SIRFSOC_NUM_IRQS 64
27 27  
28 28 static struct irq_domain *sirfsoc_irqdomain;
29 29  
30 30  
31 31  
32 32  
... ... @@ -32,15 +32,18 @@
32 32 {
33 33 struct irq_chip_generic *gc;
34 34 struct irq_chip_type *ct;
  35 + int ret;
  36 + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
35 37  
36   - gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
37   - ct = gc->chip_types;
  38 + ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
  39 + handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
38 40  
  41 + gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
  42 + gc->reg_base = base;
  43 + ct = gc->chip_types;
39 44 ct->chip.irq_mask = irq_gc_mask_clr_bit;
40 45 ct->chip.irq_unmask = irq_gc_mask_set_bit;
41 46 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
42   -
43   - irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
44 47 }
45 48  
46 49 static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
... ... @@ -60,9 +63,8 @@
60 63 if (!base)
61 64 panic("unable to map intc cpu registers\n");
62 65  
63   - /* using legacy because irqchip_generic does not work with linear */
64   - sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
65   - &irq_domain_simple_ops, base);
  66 + sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
  67 + &irq_generic_chip_ops, base);
66 68  
67 69 sirfsoc_alloc_gc(base, 0, 32);
68 70 sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);