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Commit da109897a142dd017172c0ce7abf0be8646f7109

Authored by Lennert Buytenhek
Committed by Nicolas Pitre
1 parent b8c15a6084
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] Orion: clean up addr-map.c after window setting code purge 

This patch cleans up Orion's addr-map.c a bit after all peripheral
window programming code has been moved out into the relevant drivers.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

Showing 1 changed file with 3 additions and 16 deletions Side-by-side Diff

arch/arm/mach-orion5x/addr-map.c
Diff comments   View file @ da10989
... ... @@ -34,11 +34,7 @@
34 34 * Non-CPU Masters address decoding --
35 35 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
36 36 * banks only (the typical use case).
37   - * Setup access for each master to DDR is issued by common.c.
38   - *
39   - * Note: although orion_setbits() and orion_clrbits() are not atomic
40   - * no locking is necessary here since code in this file is only called
41   - * at boot time when there is no concurrency issues.
  37 + * Setup access for each master to DDR is issued by platform device setup.
42 38 */
43 39  
44 40 /*
... ... @@ -48,10 +44,6 @@
48 44 #define TARGET_DEV_BUS 1
49 45 #define TARGET_PCI 3
50 46 #define TARGET_PCIE 4
51   -#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
52   - ((n) == 1) ? 0xd : \
53   - ((n) == 2) ? 0xb : \
54   - ((n) == 3) ? 0x7 : 0xf)
55 47 #define ATTR_PCIE_MEM 0x59
56 48 #define ATTR_PCIE_IO 0x51
57 49 #define ATTR_PCIE_WA 0x79
58 50  
... ... @@ -61,17 +53,12 @@
61 53 #define ATTR_DEV_CS1 0x1d
62 54 #define ATTR_DEV_CS2 0x1b
63 55 #define ATTR_DEV_BOOT 0xf
64   -#define WIN_EN 1
65 56  
66 57 /*
67 58 * Helpers to get DDR bank info
68 59 */
69   -#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8))
70   -#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8))
71   -#define DDR_MAX_CS 4
72   -#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
73   -#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
74   -#define DDR_BANK_EN 1
  60 +#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
  61 +#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
75 62  
76 63 /*
77 64 * CPU Address Decode Windows registers