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Commit dc36abf34e13aabbe06cdd060c434b3cdd80e7da

Authored by Paolo 'Blaisorblade' Giarrusso
Committed by Linus Torvalds
1 parent 546fe1cbf9
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[PATCH] uml: fix condition in tlb flush 

Avoid setting w = 0 twice.  Spotted this (trivial) thing which is needed for
another patch.

Signed-off-by: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
Cc: Jeff Dike <jdike@addtoit.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 1 changed file with 6 additions and 6 deletions Side-by-side Diff

arch/um/kernel/tlb.c
Diff comments   View file @ dc36abf
... ... @@ -193,12 +193,12 @@
193 193 r = pte_read(*npte);
194 194 w = pte_write(*npte);
195 195 x = pte_exec(*npte);
196   - if(!pte_dirty(*npte))
197   - w = 0;
198   - if(!pte_young(*npte)){
199   - r = 0;
200   - w = 0;
201   - }
  196 + if (!pte_young(*npte)) {
  197 + r = 0;
  198 + w = 0;
  199 + } else if (!pte_dirty(*npte)) {
  200 + w = 0;
  201 + }
202 202 if(force || pte_newpage(*npte)){
203 203 if(pte_present(*npte))
204 204 ret = add_mmap(addr,