MIPS: Refactor GIC clocksource code.

Reorganize some of the GIC clocksource driver code. Below is a list of the various changes. * No longer select CSRC_GIC by default for Malta platform. * Limit choice for either the GIC or R4K clocksource, not both. * Change location in Makefile. * Created new 'gic_read_count' function in common 'irq-gic.c' file. * Change 'git_hpt_read' function in 'csrc-gic.c' to use new function. * Surround GIC specific code in Malta platform code with #ifdef's. * Only initialize the GIC clocksource if it was selected. Original code called it unconditionally if a GIC was found. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>

MIPS: Refactor GIC clocksource code.
Reorganize some of the GIC clocksource driver code. Below is a list of the various changes. * No longer select CSRC_GIC by default for Malta platform. * Limit choice for either the GIC or R4K clocksource, not both. * Change location in Makefile. * Created new 'gic_read_count' function in common 'irq-gic.c' file. * Change 'git_hpt_read' function in 'csrc-gic.c' to use new function. * Surround GIC specific code in Malta platform code with #ifdef's. * Only initialize the GIC clocksource if it was selected. Original code called it unconditionally if a GIC was found. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Steven J. Hill · Ralf Baechle
1 parent 28ea215186
Showing 6 changed files with 48 additions and 25 deletions Side-by-side Diff
arch/mips/Kconfig
arch/mips/include/asm/gic.h
arch/mips/kernel/Makefile
arch/mips/kernel/csrc-gic.c
arch/mips/kernel/irq-gic.c
arch/mips/mti-malta/malta-time.c
@@ -337,6 +337,7 @@
 	select BOOT_RAW
 	select CEVT_R4K
 	select CSRC_R4K
+	select CSRC_GIC
 	select CPU_MIPSR2_IRQ_VI
 	select CPU_MIPSR2_IRQ_EI
 	select DMA_NONCOHERENT
@@ -359,6 +359,9 @@
 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
 #define GIC_PIN_TO_VEC_OFFSET	(1)
  
+#include <linux/clocksource.h>
+#include <linux/irq.h>
+
 extern unsigned int gic_present;
 extern unsigned int gic_frequency;
 extern unsigned long _gic_base;
@@ -372,6 +375,7 @@
  
 extern void gic_clocksource_init(unsigned int);
 extern unsigned int gic_get_int(void);
+extern cycle_t gic_read_count(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
@@ -23,11 +23,11 @@
 obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
 obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o
 obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o
+obj-$(CONFIG_CSRC_GIC)		+= csrc-gic.o
 obj-$(CONFIG_CSRC_IOASIC)	+= csrc-ioasic.o
 obj-$(CONFIG_CSRC_POWERTV)	+= csrc-powertv.o
 obj-$(CONFIG_CSRC_R4K)		+= csrc-r4k.o
 obj-$(CONFIG_CSRC_SB1250)	+= csrc-sb1250.o
-obj-$(CONFIG_CSRC_GIC)		+= csrc-gic.o
 obj-$(CONFIG_SYNC_R4K)		+= sync-r4k.o
  
 obj-$(CONFIG_STACKTRACE)	+= stacktrace.o
@@ -5,23 +5,14 @@
  *
  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  */
-#include <linux/clocksource.h>
 #include <linux/init.h>
+#include <linux/time.h>
  
-#include <asm/time.h>
 #include <asm/gic.h>
  
 static cycle_t gic_hpt_read(struct clocksource *cs)
 {
-	unsigned int hi, hi2, lo;
-
-	do {
-		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
-		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
-		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
-	} while (hi2 != hi);
-
-	return (((cycle_t) hi) << 32) + lo;
+	return gic_read_count();
 }
  
 static struct clocksource gic_clocksource = {
@@ -10,6 +10,7 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/irq.h>
+#include <linux/clocksource.h>
  
 #include <asm/io.h>
 #include <asm/gic.h>
@@ -31,6 +32,21 @@
 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static struct gic_pending_regs pending_regs[NR_CPUS];
 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
+
+#ifdef CONFIG_CSRC_GIC
+cycle_t gic_read_count(void)
+{
+	unsigned int hi, hi2, lo;
+
+	do {
+		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
+		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
+		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
+	} while (hi2 != hi);
+
+	return (((cycle_t) hi) << 32) + lo;
+}
+#endif
  
 unsigned int gic_get_timer_pending(void)
 {
@@ -71,7 +71,9 @@
 {
 	unsigned long flags;
 	unsigned int count, start;
+#ifdef CONFIG_IRQ_GIC
 	unsigned int giccount = 0, gicstart = 0;
+#endif
  
 	local_irq_save(flags);
  
  
  
  
  
  
  
@@ -81,26 +83,32 @@
  
 	/* Initialize counters. */
 	start = read_c0_count();
+#ifdef CONFIG_IRQ_GIC
 	if (gic_present)
 		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
+#endif
  
 	/* Read counter exactly on falling edge of update flag. */
 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 	while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  
 	count = read_c0_count();
+#ifdef CONFIG_IRQ_GIC
 	if (gic_present)
 		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
+#endif
  
 	local_irq_restore(flags);
  
 	count -= start;
-	if (gic_present)
-		giccount -= gicstart;
-
 	mips_hpt_frequency = count;
-	if (gic_present)
+
+#ifdef CONFIG_IRQ_GIC
+	if (gic_present) {
+		giccount -= gicstart;
 		gic_frequency = giccount;
+	}
+#endif
 }
  
 void read_persistent_clock(struct timespec *ts)
  
  
@@ -156,24 +164,27 @@
 	    (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 		freq *= 2;
 	freq = freqround(freq, 5000);
-	pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
+	printk("CPU frequency %d.%02d MHz\n", freq/1000000,
 	       (freq%1000000)*100/1000000);
 	cpu_khz = freq / 1000;
  
-	if (gic_present) {
-		freq = freqround(gic_frequency, 5000);
-		pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
-		       (freq%1000000)*100/1000000);
-		gic_clocksource_init(gic_frequency);
-	} else
-		init_r4k_clocksource();
+	mips_scroll_message();
  
 #ifdef CONFIG_I8253
 	/* Only Malta has a PIT. */
 	setup_pit_timer();
 #endif
  
-	mips_scroll_message();
+#ifdef CONFIG_IRQ_GIC
+	if (gic_present) {
+		freq = freqround(gic_frequency, 5000);
+		printk("GIC frequency %d.%02d MHz\n", freq/1000000,
+		       (freq%1000000)*100/1000000);
+#ifdef CONFIG_CSRC_GIC
+		gic_clocksource_init(gic_frequency);
+#endif
+	}
+#endif
  
 	plat_perf_setup();
 }
...	...	@@ -337,6 +337,7 @@
337	337	select BOOT_RAW
338	338	select CEVT_R4K
339	339	select CSRC_R4K
	340	+ select CSRC_GIC
340	341	select CPU_MIPSR2_IRQ_VI
341	342	select CPU_MIPSR2_IRQ_EI
342	343	select DMA_NONCOHERENT
...	...	@@ -359,6 +359,9 @@
359	359	/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
360	360	#define GIC_PIN_TO_VEC_OFFSET (1)
361	361
	362	+#include <linux/clocksource.h>
	363	+#include <linux/irq.h>
	364	+
362	365	extern unsigned int gic_present;
363	366	extern unsigned int gic_frequency;
364	367	extern unsigned long _gic_base;
...	...	@@ -372,6 +375,7 @@
372	375
373	376	extern void gic_clocksource_init(unsigned int);
374	377	extern unsigned int gic_get_int(void);
	378	+extern cycle_t gic_read_count(void);
375	379	extern void gic_send_ipi(unsigned int intr);
376	380	extern unsigned int plat_ipi_call_int_xlate(unsigned int);
377	381	extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
...	...	@@ -23,11 +23,11 @@
23	23	obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
24	24	obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
25	25	obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
	26	+obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
26	27	obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
27	28	obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
28	29	obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
29	30	obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
30		-obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
31	31	obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
32	32
33	33	obj-$(CONFIG_STACKTRACE) += stacktrace.o
...	...	@@ -5,23 +5,14 @@
5	5	*
6	6	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7	7	*/
8		-#include <linux/clocksource.h>
9	8	#include <linux/init.h>
	9	+#include <linux/time.h>
10	10
11		-#include <asm/time.h>
12	11	#include <asm/gic.h>
13	12
14	13	static cycle_t gic_hpt_read(struct clocksource *cs)
15	14	{
16		- unsigned int hi, hi2, lo;
17		-
18		- do {
19		- GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
20		- GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
21		- GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
22		- } while (hi2 != hi);
23		-
24		- return (((cycle_t) hi) << 32) + lo;
	15	+ return gic_read_count();
25	16	}
26	17
27	18	static struct clocksource gic_clocksource = {
...	...	@@ -10,6 +10,7 @@
10	10	#include <linux/init.h>
11	11	#include <linux/smp.h>
12	12	#include <linux/irq.h>
	13	+#include <linux/clocksource.h>
13	14
14	15	#include <asm/io.h>
15	16	#include <asm/gic.h>
...	...	@@ -31,6 +32,21 @@
31	32	static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
32	33	static struct gic_pending_regs pending_regs[NR_CPUS];
33	34	static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
	35	+
	36	+#ifdef CONFIG_CSRC_GIC
	37	+cycle_t gic_read_count(void)
	38	+{
	39	+ unsigned int hi, hi2, lo;
	40	+
	41	+ do {
	42	+ GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
	43	+ GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
	44	+ GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
	45	+ } while (hi2 != hi);
	46	+
	47	+ return (((cycle_t) hi) << 32) + lo;
	48	+}
	49	+#endif
34	50
35	51	unsigned int gic_get_timer_pending(void)
36	52	{
...	...	@@ -71,7 +71,9 @@
71	71	{
72	72	unsigned long flags;
73	73	unsigned int count, start;
	74	+#ifdef CONFIG_IRQ_GIC
74	75	unsigned int giccount = 0, gicstart = 0;
	76	+#endif
75	77
76	78	local_irq_save(flags);
77	79
78	80
79	81
80	82
81	83
82	84
83	85
...	...	@@ -81,26 +83,32 @@
81	83
82	84	/* Initialize counters. */
83	85	start = read_c0_count();
	86	+#ifdef CONFIG_IRQ_GIC
84	87	if (gic_present)
85	88	GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
	89	+#endif
86	90
87	91	/* Read counter exactly on falling edge of update flag. */
88	92	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
89	93	while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
90	94
91	95	count = read_c0_count();
	96	+#ifdef CONFIG_IRQ_GIC
92	97	if (gic_present)
93	98	GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
	99	+#endif
94	100
95	101	local_irq_restore(flags);
96	102
97	103	count -= start;
98		- if (gic_present)
99		- giccount -= gicstart;
100		-
101	104	mips_hpt_frequency = count;
102		- if (gic_present)
	105	+
	106	+#ifdef CONFIG_IRQ_GIC
	107	+ if (gic_present) {
	108	+ giccount -= gicstart;
103	109	gic_frequency = giccount;
	110	+ }
	111	+#endif
104	112	}
105	113
106	114	void read_persistent_clock(struct timespec *ts)
107	115
108	116
...	...	@@ -156,24 +164,27 @@
156	164	(prid != (PRID_COMP_MIPS \| PRID_IMP_25KF)))
157	165	freq *= 2;
158	166	freq = freqround(freq, 5000);
159		- pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
	167	+ printk("CPU frequency %d.%02d MHz\n", freq/1000000,
160	168	(freq%1000000)*100/1000000);
161	169	cpu_khz = freq / 1000;
162	170
163		- if (gic_present) {
164		- freq = freqround(gic_frequency, 5000);
165		- pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
166		- (freq%1000000)*100/1000000);
167		- gic_clocksource_init(gic_frequency);
168		- } else
169		- init_r4k_clocksource();
	171	+ mips_scroll_message();
170	172
171	173	#ifdef CONFIG_I8253
172	174	/* Only Malta has a PIT. */
173	175	setup_pit_timer();
174	176	#endif
175	177
176		- mips_scroll_message();
	178	+#ifdef CONFIG_IRQ_GIC
	179	+ if (gic_present) {
	180	+ freq = freqround(gic_frequency, 5000);
	181	+ printk("GIC frequency %d.%02d MHz\n", freq/1000000,
	182	+ (freq%1000000)*100/1000000);
	183	+#ifdef CONFIG_CSRC_GIC
	184	+ gic_clocksource_init(gic_frequency);
	185	+#endif
	186	+ }
	187	+#endif
177	188
178	189	plat_perf_setup();
179	190	}