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Commit e14cbee401cd00779a5267128371506b22c77bc9

Authored by Michel Dänzer
Committed by Dave Airlie
1 parent b1e3a6d1c4
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

drm: Fix shifts which were miscalculated when converting from bitfields. 

Looks like I managed to mess up most shifts when converting from bitfields. :(

The patch below works on my Thinkpad T500 (as well as on my PowerBook,
where the previous change worked as well, maybe out of luck...). I'd
appreciate more testing and eyes looking over it though.

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Tested-by: Michael Pyne <mpyne@kde.org>
Signed-off-by: Dave Airlie <airlied@linux.ie>

Showing 2 changed files with 25 additions and 25 deletions Side-by-side Diff

drivers/gpu/drm/drm_edid.c
Diff comments   View file @ e14cbee
... ... @@ -294,10 +294,10 @@
294 294 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
295 295 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
296 296 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
297   - unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 8 | pt->hsync_offset_lo;
298   - unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 6 | pt->hsync_pulse_width_lo;
299   - unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) | (pt->vsync_offset_pulse_width_lo & 0xf);
300   - unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
  297 + unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
  298 + unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
  299 + unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
  300 + unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
301 301  
302 302 /* ignore tiny modes */
303 303 if (hactive < 64 || vactive < 64)
... ... @@ -347,8 +347,8 @@
347 347 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
348 348 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
349 349  
350   - mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
351   - mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
  350 + mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
  351 + mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
352 352  
353 353 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
354 354 mode->width_mm *= 10;
include/drm/drm_edid.h
Diff comments   View file @ e14cbee
... ... @@ -35,11 +35,11 @@
35 35 } __attribute__((packed));
36 36  
37 37 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
38   -#define EDID_TIMING_ASPECT_SHIFT 0
  38 +#define EDID_TIMING_ASPECT_SHIFT 6
39 39 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
40 40  
41 41 /* need to add 60 */
42   -#define EDID_TIMING_VFREQ_SHIFT 2
  42 +#define EDID_TIMING_VFREQ_SHIFT 0
43 43 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
44 44  
45 45 struct std_timing {
46 46  
... ... @@ -47,11 +47,11 @@
47 47 u8 vfreq_aspect;
48 48 } __attribute__((packed));
49 49  
50   -#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 6)
51   -#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 5)
  50 +#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
  51 +#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
52 52 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
53   -#define DRM_EDID_PT_STEREO (1 << 2)
54   -#define DRM_EDID_PT_INTERLACED (1 << 1)
  53 +#define DRM_EDID_PT_STEREO (1 << 5)
  54 +#define DRM_EDID_PT_INTERLACED (1 << 7)
55 55  
56 56 /* If detailed data is pixel timing */
57 57 struct detailed_pixel_timing {
... ... @@ -93,7 +93,7 @@
93 93 } __attribute__((packed));
94 94  
95 95 struct detailed_data_wpindex {
96   - u8 white_xy_lo; /* Upper 2 bits each */
  96 + u8 white_yx_lo; /* Lower 2 bits each */
97 97 u8 white_x_hi;
98 98 u8 white_y_hi;
99 99 u8 gamma; /* need to divide by 100 then add 1 */
100 100  
101 101  
102 102  
... ... @@ -135,21 +135,21 @@
135 135 } data;
136 136 } __attribute__((packed));
137 137  
138   -#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 7)
139   -#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 5)
140   -#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 4)
  138 +#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
  139 +#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
  140 +#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
141 141 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
142   -#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 2)
143   -#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 1)
144   -#define DRM_EDID_INPUT_DIGITAL (1 << 0) /* bits above must be zero if set */
  142 +#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
  143 +#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
  144 +#define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */
145 145  
146   -#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 7)
147   -#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 6)
148   -#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 5)
  146 +#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
  147 +#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
  148 +#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
149 149 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
150   -#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 2)
151   -#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 1)
152   -#define DRM_EDID_FEATURE_PM_STANDBY (1 << 0)
  150 +#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
  151 +#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
  152 +#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
153 153  
154 154 struct edid {
155 155 u8 header[8];