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Commit e2823299cdc140cccd40484d690ab1d90d75b099

Authored by Linus Torvalds
2 parents 240c3c3424 de4772c621
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

Merge branch 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac 

Pull edac fixes from Mauro Carvalho Chehab:
 "Two edac fixes:

   - i7300_edac currently reports a wrong number of DIMMs when the
     memory controller is in single channel mode

   - on some Sandy Bridge machines, the EDAC driver bails out as one of
     the PCI IDs used by the driver is hidden by BIOS.  As the driver
     uses it only to detect the type of memory, make it optional at the
     driver"

* 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac:
  edac: sb_edac.c should not require prescence of IMC_DDRIO device
  i7300_edac: Fix memory detection in single mode

Showing 2 changed files Side-by-side Diff

drivers/edac/i7300_edac.c
Diff comments   View file @ e282329
... ... @@ -750,15 +750,23 @@
750 750 struct i7300_dimm_info *dinfo;
751 751 int rc = -ENODEV;
752 752 int mtr;
753   - int ch, branch, slot, channel;
  753 + int ch, branch, slot, channel, max_channel, max_branch;
754 754 struct dimm_info *dimm;
755 755  
756 756 pvt = mci->pvt_info;
757 757  
758 758 edac_dbg(2, "Memory Technology Registers:\n");
759 759  
  760 + if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
  761 + max_branch = 1;
  762 + max_channel = 1;
  763 + } else {
  764 + max_branch = MAX_BRANCHES;
  765 + max_channel = MAX_CH_PER_BRANCH;
  766 + }
  767 +
760 768 /* Get the AMB present registers for the four channels */
761   - for (branch = 0; branch < MAX_BRANCHES; branch++) {
  769 + for (branch = 0; branch < max_branch; branch++) {
762 770 /* Read and dump branch 0's MTRs */
763 771 channel = to_channel(0, branch);
764 772 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
... ... @@ -767,6 +775,9 @@
767 775 edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
768 776 channel, pvt->ambpresent[channel]);
769 777  
  778 + if (max_channel == 1)
  779 + continue;
  780 +
770 781 channel = to_channel(1, branch);
771 782 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
772 783 AMBPRESENT_1,
773 784  
... ... @@ -778,11 +789,11 @@
778 789 /* Get the set of MTR[0-7] regs by each branch */
779 790 for (slot = 0; slot < MAX_SLOTS; slot++) {
780 791 int where = mtr_regs[slot];
781   - for (branch = 0; branch < MAX_BRANCHES; branch++) {
  792 + for (branch = 0; branch < max_branch; branch++) {
782 793 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
783 794 where,
784 795 &pvt->mtr[slot][branch]);
785   - for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) {
  796 + for (ch = 0; ch < max_channel; ch++) {
786 797 int channel = to_channel(ch, branch);
787 798  
788 799 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
drivers/edac/sb_edac.c
Diff comments   View file @ e282329
... ... @@ -331,30 +331,31 @@
331 331 u64 tolm, tohm;
332 332 };
333 333  
334   -#define PCI_DESCR(device, function, device_id) \
335   - .dev = (device), \
336   - .func = (function), \
337   - .dev_id = (device_id)
  334 +#define PCI_DESCR(device, function, device_id, opt) \
  335 + .dev = (device), \
  336 + .func = (function), \
  337 + .dev_id = (device_id), \
  338 + .optional = opt
338 339  
339 340 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
340 341 /* Processor Home Agent */
341   - { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) },
  342 + { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
342 343  
343 344 /* Memory controller */
344   - { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) },
345   - { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) },
346   - { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) },
347   - { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) },
348   - { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) },
349   - { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) },
350   - { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) },
  345 + { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
  346 + { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
  347 + { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
  348 + { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
  349 + { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
  350 + { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
  351 + { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
351 352  
352 353 /* System Address Decoder */
353   - { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) },
354   - { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) },
  354 + { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
  355 + { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
355 356  
356 357 /* Broadcast Registers */
357   - { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) },
  358 + { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
358 359 };
359 360  
360 361 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
361 362  
... ... @@ -556,14 +557,19 @@
556 557 pvt->is_close_pg = false;
557 558 }
558 559  
559   - pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, &reg);
560   - if (IS_RDIMM_ENABLED(reg)) {
561   - /* FIXME: Can also be LRDIMM */
562   - edac_dbg(0, "Memory is registered\n");
563   - mtype = MEM_RDDR3;
  560 + if (pvt->pci_ddrio) {
  561 + pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, &reg);
  562 + if (IS_RDIMM_ENABLED(reg)) {
  563 + /* FIXME: Can also be LRDIMM */
  564 + edac_dbg(0, "Memory is registered\n");
  565 + mtype = MEM_RDDR3;
  566 + } else {
  567 + edac_dbg(0, "Memory is unregistered\n");
  568 + mtype = MEM_DDR3;
  569 + }
564 570 } else {
565   - edac_dbg(0, "Memory is unregistered\n");
566   - mtype = MEM_DDR3;
  571 + edac_dbg(0, "Cannot determine memory type\n");
  572 + mtype = MEM_UNKNOWN;
567 573 }
568 574  
569 575 /* On all supported DDR3 DIMM types, there are 8 banks available */
... ... @@ -1303,8 +1309,7 @@
1303 1309  
1304 1310 /* Check if everything were registered */
1305 1311 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1306   - !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta ||
1307   - !pvt->pci_ddrio)
  1312 + !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
1308 1313 goto enodev;
1309 1314  
1310 1315 for (i = 0; i < NUM_CHANNELS; i++) {