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Commit e58f6f4fb4eada7867014bfaec898f03afbce5c2

Authored by Aida Mynzhasova
Committed by David S. Miller
1 parent 3f3f0960af
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file 

Currently IEEE 1588 timer reference clock source is determined through
hard-coded value in gianfar_ptp driver. This patch allows to select ptp
clock source by means of device tree file node.

For instance:

	fsl,cksel = <0>;

for using external (TSEC_TMR_CLK input) high precision timer
reference clock.

Other acceptable values:

	<1> : eTSEC system clock
	<2> : eTSEC1 transmit clock
	<3> : RTC clock input

When this attribute isn't used, eTSEC system clock will serve as
IEEE 1588 timer reference clock.

Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 2 changed files with 20 additions and 2 deletions Side-by-side Diff

Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
Diff comments   View file @ e58f6f4
... ... @@ -86,6 +86,7 @@
86 86  
87 87 Clock Properties:
88 88  
  89 + - fsl,cksel Timer reference clock source.
89 90 - fsl,tclk-period Timer reference clock period in nanoseconds.
90 91 - fsl,tmr-prsc Prescaler, divides the output clock.
91 92 - fsl,tmr-add Frequency compensation value.
... ... @@ -97,7 +98,7 @@
97 98 clock. You must choose these carefully for the clock to work right.
98 99 Here is how to figure good values:
99 100  
100   - TimerOsc = system clock MHz
  101 + TimerOsc = selected reference clock MHz
101 102 tclk_period = desired clock period nanoseconds
102 103 NominalFreq = 1000 / tclk_period MHz
103 104 FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
... ... @@ -114,6 +115,20 @@
114 115 Pulse Per Second (PPS) signal, since this will be offered to the PPS
115 116 subsystem to synchronize the Linux clock.
116 117  
  118 + Reference clock source is determined by the value, which is holded
  119 + in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
  120 + value, which will be directly written in those bits, that is why,
  121 + according to reference manual, the next clock sources can be used:
  122 +
  123 + <0> - external high precision timer reference clock (TSEC_TMR_CLK
  124 + input is used for this purpose);
  125 + <1> - eTSEC system clock;
  126 + <2> - eTSEC1 transmit clock;
  127 + <3> - RTC clock input.
  128 +
  129 + When this attribute is not used, eTSEC system clock will serve as
  130 + IEEE 1588 timer reference clock.
  131 +
117 132 Example:
118 133  
119 134 ptp_clock@24E00 {
... ... @@ -121,6 +136,7 @@
121 136 reg = <0x24E00 0xB0>;
122 137 interrupts = <12 0x8 13 0x8>;
123 138 interrupt-parent = < &ipic >;
  139 + fsl,cksel = <1>;
124 140 fsl,tclk-period = <10>;
125 141 fsl,tmr-prsc = <100>;
126 142 fsl,tmr-add = <0x999999A4>;
drivers/net/ethernet/freescale/gianfar_ptp.c
Diff comments   View file @ e58f6f4
... ... @@ -452,7 +452,9 @@
452 452 err = -ENODEV;
453 453  
454 454 etsects->caps = ptp_gianfar_caps;
455   - etsects->cksel = DEFAULT_CKSEL;
  455 +
  456 + if (get_of_u32(node, "fsl,cksel", &etsects->cksel))
  457 + etsects->cksel = DEFAULT_CKSEL;
456 458  
457 459 if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
458 460 get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||