Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit e5abf78b57199a417eb01ff922a5ea6ff9e10b61

Authored by GuanXuetao
1 parent 4517366d87
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

unicore32 io: redefine __REG(x) and re-use readl/writel funcs 

-- by advice of Arnd Bergmann

Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>

Showing 13 changed files with 171 additions and 164 deletions Side-by-side Diff

arch/unicore32/include/asm/gpio.h
Diff comments   View file @ e5abf78
... ... @@ -13,6 +13,7 @@
13 13 #ifndef __UNICORE_GPIO_H__
14 14 #define __UNICORE_GPIO_H__
15 15  
  16 +#include <linux/io.h>
16 17 #include <asm/irq.h>
17 18 #include <mach/hardware.h>
18 19 #include <asm-generic/gpio.h>
... ... @@ -66,7 +67,7 @@
66 67 static inline int gpio_get_value(unsigned gpio)
67 68 {
68 69 if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
69   - return GPIO_GPLR & GPIO_GPIO(gpio);
  70 + return readl(GPIO_GPLR) & GPIO_GPIO(gpio);
70 71 else
71 72 return __gpio_get_value(gpio);
72 73 }
73 74  
... ... @@ -75,9 +76,9 @@
75 76 {
76 77 if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
77 78 if (value)
78   - GPIO_GPSR = GPIO_GPIO(gpio);
  79 + writel(GPIO_GPIO(gpio), GPIO_GPSR);
79 80 else
80   - GPIO_GPCR = GPIO_GPIO(gpio);
  81 + writel(GPIO_GPIO(gpio), GPIO_GPCR);
81 82 else
82 83 __gpio_set_value(gpio, value);
83 84 }
... ... @@ -86,7 +87,7 @@
86 87  
87 88 static inline unsigned gpio_to_irq(unsigned gpio)
88 89 {
89   - if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & GPIO_GPIR))
  90 + if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & readl(GPIO_GPIR)))
90 91 return IRQ_GPIOLOW0 + gpio;
91 92 else
92 93 return IRQ_GPIO0 + gpio;
arch/unicore32/include/mach/dma.h
Diff comments   View file @ e5abf78
... ... @@ -35,8 +35,15 @@
35 35  
36 36 extern void puv3_free_dma(int dma_ch);
37 37  
38   -#define puv3_stop_dma(ch) (DMAC_CONFIG(ch) &= ~DMAC_CONFIG_EN)
39   -#define puv3_resume_dma(ch) (DMAC_CONFIG(ch) |= DMAC_CONFIG_EN)
  38 +static inline void puv3_stop_dma(int ch)
  39 +{
  40 + writel(readl(DMAC_CONFIG(ch)) & ~DMAC_CONFIG_EN, DMAC_CONFIG(ch));
  41 +}
  42 +
  43 +static inline void puv3_resume_dma(int ch)
  44 +{
  45 + writel(readl(DMAC_CONFIG(ch)) | DMAC_CONFIG_EN, DMAC_CONFIG(ch));
  46 +}
40 47  
41 48 #endif /* __MACH_PUV3_DMA_H__ */
arch/unicore32/include/mach/hardware.h
Diff comments   View file @ e5abf78
... ... @@ -22,13 +22,7 @@
22 22  
23 23 #ifndef __ASSEMBLY__
24 24  
25   -# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
26   -# define __PREG(x) (io_v2p((unsigned long)&(x)))
27   -
28   -#else
29   -
30   -# define __REG(x) io_p2v(x)
31   -# define __PREG(x) io_v2p(x)
  25 +# define __REG(x) (void __iomem *)io_p2v(x)
32 26  
33 27 #endif
34 28  
arch/unicore32/kernel/clock.c
Diff comments   View file @ e5abf78
... ... @@ -20,6 +20,7 @@
20 20 #include <linux/clk.h>
21 21 #include <linux/mutex.h>
22 22 #include <linux/delay.h>
  23 +#include <linux/io.h>
23 24  
24 25 #include <mach/hardware.h>
25 26  
26 27  
27 28  
28 29  
29 30  
30 31  
31 32  
... ... @@ -152,28 +153,29 @@
152 153 if (ret)
153 154 return ret;
154 155  
155   - if (PM_PLLVGACFG == pll_vgacfg)
  156 + if (readl(PM_PLLVGACFG) == pll_vgacfg)
156 157 return 0;
157 158  
158 159 /* set pll vga cfg reg. */
159   - PM_PLLVGACFG = pll_vgacfg;
  160 + writel(pll_vgacfg, PM_PLLVGACFG);
160 161  
161   - PM_PMCR = PM_PMCR_CFBVGA;
162   - while ((PM_PLLDFCDONE & PM_PLLDFCDONE_VGADFC)
  162 + writel(PM_PMCR_CFBVGA, PM_PMCR);
  163 + while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC)
163 164 != PM_PLLDFCDONE_VGADFC)
164 165 udelay(100); /* about 1ms */
165 166  
166 167 /* set div cfg reg. */
167   - PM_PCGR |= PM_PCGR_VGACLK;
  168 + writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR);
168 169  
169   - PM_DIVCFG = (PM_DIVCFG & ~PM_DIVCFG_VGACLK_MASK)
170   - | PM_DIVCFG_VGACLK(pll_vgadiv);
  170 + writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK)
  171 + | PM_DIVCFG_VGACLK(pll_vgadiv), PM_DIVCFG);
171 172  
172   - PM_SWRESET |= PM_SWRESET_VGADIV;
173   - while ((PM_SWRESET & PM_SWRESET_VGADIV) == PM_SWRESET_VGADIV)
  173 + writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET);
  174 + while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV)
  175 + == PM_SWRESET_VGADIV)
174 176 udelay(100); /* 65536 bclk32, about 320us */
175 177  
176   - PM_PCGR &= ~PM_PCGR_VGACLK;
  178 + writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR);
177 179 }
178 180 #ifdef CONFIG_CPU_FREQ
179 181 if (clk == &clk_mclk_clk) {
180 182  
181 183  
... ... @@ -323,15 +325,15 @@
323 325 static int __init clk_init(void)
324 326 {
325 327 #ifdef CONFIG_PUV3_PM
326   - u32 pllrate, divstatus = PM_DIVSTATUS;
327   - u32 pcgr_val = PM_PCGR;
  328 + u32 pllrate, divstatus = readl(PM_DIVSTATUS);
  329 + u32 pcgr_val = readl(PM_PCGR);
328 330 int i;
329 331  
330 332 pcgr_val |= PM_PCGR_BCLKMME | PM_PCGR_BCLKH264E | PM_PCGR_BCLKH264D
331 333 | PM_PCGR_HECLK | PM_PCGR_HDCLK;
332   - PM_PCGR = pcgr_val;
  334 + writel(pcgr_val, PM_PCGR);
333 335  
334   - pllrate = PM_PLLSYSSTATUS;
  336 + pllrate = readl(PM_PLLSYSSTATUS);
335 337  
336 338 /* lookup pmclk_table */
337 339 clk_mclk_clk.rate = 0;
... ... @@ -346,7 +348,7 @@
346 348 clk_bclk32_clk.rate = clk_mclk_clk.rate /
347 349 (((divstatus & 0x0000f000) >> 12) + 1);
348 350  
349   - pllrate = PM_PLLDDRSTATUS;
  351 + pllrate = readl(PM_PLLDDRSTATUS);
350 352  
351 353 /* lookup pddr_table */
352 354 clk_ddr_clk.rate = 0;
... ... @@ -357,7 +359,7 @@
357 359 }
358 360 }
359 361  
360   - pllrate = PM_PLLVGASTATUS;
  362 + pllrate = readl(PM_PLLVGASTATUS);
361 363  
362 364 /* lookup pvga_table */
363 365 clk_vga_clk.rate = 0;
arch/unicore32/kernel/dma.c
Diff comments   View file @ e5abf78
... ... @@ -16,6 +16,7 @@
16 16 #include <linux/kernel.h>
17 17 #include <linux/interrupt.h>
18 18 #include <linux/errno.h>
  19 +#include <linux/io.h>
19 20  
20 21 #include <asm/system.h>
21 22 #include <asm/irq.h>
22 23  
23 24  
... ... @@ -94,15 +95,16 @@
94 95  
95 96 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
96 97 {
97   - int i, dint = DMAC_ITCSR;
  98 + int i, dint;
98 99  
  100 + dint = readl(DMAC_ITCSR);
99 101 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
100 102 if (dint & DMAC_CHANNEL(i)) {
101 103 struct dma_channel *channel = &dma_channels[i];
102 104  
103 105 /* Clear TC interrupt of channel i */
104   - DMAC_ITCCR = DMAC_CHANNEL(i);
105   - DMAC_ITCCR = 0;
  106 + writel(DMAC_CHANNEL(i), DMAC_ITCCR);
  107 + writel(0, DMAC_ITCCR);
106 108  
107 109 if (channel->name && channel->irq_handler) {
108 110 channel->irq_handler(i, channel->data);
109 111  
110 112  
... ... @@ -121,15 +123,16 @@
121 123  
122 124 static irqreturn_t dma_err_handler(int irq, void *dev_id)
123 125 {
124   - int i, dint = DMAC_IESR;
  126 + int i, dint;
125 127  
  128 + dint = readl(DMAC_IESR);
126 129 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
127 130 if (dint & DMAC_CHANNEL(i)) {
128 131 struct dma_channel *channel = &dma_channels[i];
129 132  
130 133 /* Clear Err interrupt of channel i */
131   - DMAC_IECR = DMAC_CHANNEL(i);
132   - DMAC_IECR = 0;
  134 + writel(DMAC_CHANNEL(i), DMAC_IECR);
  135 + writel(0, DMAC_IECR);
133 136  
134 137 if (channel->name && channel->err_handler) {
135 138 channel->err_handler(i, channel->data);
arch/unicore32/kernel/gpio.c
Diff comments   View file @ e5abf78
... ... @@ -52,15 +52,15 @@
52 52  
53 53 static int puv3_gpio_get(struct gpio_chip *chip, unsigned offset)
54 54 {
55   - return GPIO_GPLR & GPIO_GPIO(offset);
  55 + return readl(GPIO_GPLR) & GPIO_GPIO(offset);
56 56 }
57 57  
58 58 static void puv3_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
59 59 {
60 60 if (value)
61   - GPIO_GPSR = GPIO_GPIO(offset);
  61 + writel(GPIO_GPIO(offset), GPIO_GPSR);
62 62 else
63   - GPIO_GPCR = GPIO_GPIO(offset);
  63 + writel(GPIO_GPIO(offset), GPIO_GPCR);
64 64 }
65 65  
66 66 static int puv3_direction_input(struct gpio_chip *chip, unsigned offset)
... ... @@ -68,7 +68,7 @@
68 68 unsigned long flags;
69 69  
70 70 local_irq_save(flags);
71   - GPIO_GPDR &= ~GPIO_GPIO(offset);
  71 + writel(readl(GPIO_GPDR) & ~GPIO_GPIO(offset), GPIO_GPDR);
72 72 local_irq_restore(flags);
73 73 return 0;
74 74 }
... ... @@ -80,7 +80,7 @@
80 80  
81 81 local_irq_save(flags);
82 82 puv3_gpio_set(chip, offset, value);
83   - GPIO_GPDR |= GPIO_GPIO(offset);
  83 + writel(readl(GPIO_GPDR) | GPIO_GPIO(offset), GPIO_GPDR);
84 84 local_irq_restore(flags);
85 85 return 0;
86 86 }
... ... @@ -97,7 +97,7 @@
97 97  
98 98 void __init puv3_init_gpio(void)
99 99 {
100   - GPIO_GPDR = GPIO_DIR;
  100 + writel(GPIO_DIR, GPIO_GPDR);
101 101 #if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919) \
102 102 || defined(CONFIG_PUV3_DB0913)
103 103 gpio_set_value(GPO_WIFI_EN, 1);
arch/unicore32/kernel/irq.c
Diff comments   View file @ e5abf78
... ... @@ -66,8 +66,8 @@
66 66 else
67 67 GPIO_IRQ_falling_edge &= ~mask;
68 68  
69   - GPIO_GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
70   - GPIO_GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  69 + writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
  70 + writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
71 71  
72 72 return 0;
73 73 }
74 74  
75 75  
76 76  
77 77  
... ... @@ -77,25 +77,25 @@
77 77 */
78 78 static void puv3_low_gpio_ack(struct irq_data *d)
79 79 {
80   - GPIO_GEDR = (1 << d->irq);
  80 + writel((1 << d->irq), GPIO_GEDR);
81 81 }
82 82  
83 83 static void puv3_low_gpio_mask(struct irq_data *d)
84 84 {
85   - INTC_ICMR &= ~(1 << d->irq);
  85 + writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
86 86 }
87 87  
88 88 static void puv3_low_gpio_unmask(struct irq_data *d)
89 89 {
90   - INTC_ICMR |= 1 << d->irq;
  90 + writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
91 91 }
92 92  
93 93 static int puv3_low_gpio_wake(struct irq_data *d, unsigned int on)
94 94 {
95 95 if (on)
96   - PM_PWER |= 1 << d->irq;
  96 + writel(readl(PM_PWER) | (1 << d->irq), PM_PWER);
97 97 else
98   - PM_PWER &= ~(1 << d->irq);
  98 + writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER);
99 99 return 0;
100 100 }
101 101  
102 102  
... ... @@ -118,13 +118,13 @@
118 118 {
119 119 unsigned int mask;
120 120  
121   - mask = GPIO_GEDR;
  121 + mask = readl(GPIO_GEDR);
122 122 do {
123 123 /*
124 124 * clear down all currently active IRQ sources.
125 125 * We will be processing them all.
126 126 */
127   - GPIO_GEDR = mask;
  127 + writel(mask, GPIO_GEDR);
128 128  
129 129 irq = IRQ_GPIO0;
130 130 do {
... ... @@ -133,7 +133,7 @@
133 133 mask >>= 1;
134 134 irq++;
135 135 } while (mask);
136   - mask = GPIO_GEDR;
  136 + mask = readl(GPIO_GEDR);
137 137 } while (mask);
138 138 }
139 139  
... ... @@ -146,7 +146,7 @@
146 146 {
147 147 unsigned int mask = GPIO_MASK(d->irq);
148 148  
149   - GPIO_GEDR = mask;
  149 + writel(mask, GPIO_GEDR);
150 150 }
151 151  
152 152 static void puv3_high_gpio_mask(struct irq_data *d)
... ... @@ -155,8 +155,8 @@
155 155  
156 156 GPIO_IRQ_mask &= ~mask;
157 157  
158   - GPIO_GRER &= ~mask;
159   - GPIO_GFER &= ~mask;
  158 + writel(readl(GPIO_GRER) & ~mask, GPIO_GRER);
  159 + writel(readl(GPIO_GFER) & ~mask, GPIO_GFER);
160 160 }
161 161  
162 162 static void puv3_high_gpio_unmask(struct irq_data *d)
163 163  
164 164  
... ... @@ -165,16 +165,16 @@
165 165  
166 166 GPIO_IRQ_mask |= mask;
167 167  
168   - GPIO_GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
169   - GPIO_GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  168 + writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
  169 + writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
170 170 }
171 171  
172 172 static int puv3_high_gpio_wake(struct irq_data *d, unsigned int on)
173 173 {
174 174 if (on)
175   - PM_PWER |= PM_PWER_GPIOHIGH;
  175 + writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER);
176 176 else
177   - PM_PWER &= ~PM_PWER_GPIOHIGH;
  177 + writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER);
178 178 return 0;
179 179 }
180 180  
181 181  
... ... @@ -193,12 +193,12 @@
193 193 */
194 194 static void puv3_mask_irq(struct irq_data *d)
195 195 {
196   - INTC_ICMR &= ~(1 << d->irq);
  196 + writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
197 197 }
198 198  
199 199 static void puv3_unmask_irq(struct irq_data *d)
200 200 {
201   - INTC_ICMR |= (1 << d->irq);
  201 + writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
202 202 }
203 203  
204 204 /*
205 205  
... ... @@ -208,9 +208,9 @@
208 208 {
209 209 if (d->irq == IRQ_RTCAlarm) {
210 210 if (on)
211   - PM_PWER |= PM_PWER_RTC;
  211 + writel(readl(PM_PWER) | PM_PWER_RTC, PM_PWER);
212 212 else
213   - PM_PWER &= ~PM_PWER_RTC;
  213 + writel(readl(PM_PWER) & ~PM_PWER_RTC, PM_PWER);
214 214 return 0;
215 215 }
216 216 return -EINVAL;
217 217  
218 218  
219 219  
... ... @@ -242,25 +242,25 @@
242 242 struct puv3_irq_state *st = &puv3_irq_state;
243 243  
244 244 st->saved = 1;
245   - st->icmr = INTC_ICMR;
246   - st->iclr = INTC_ICLR;
247   - st->iccr = INTC_ICCR;
  245 + st->icmr = readl(INTC_ICMR);
  246 + st->iclr = readl(INTC_ICLR);
  247 + st->iccr = readl(INTC_ICCR);
248 248  
249 249 /*
250 250 * Disable all GPIO-based interrupts.
251 251 */
252   - INTC_ICMR &= ~(0x1ff);
  252 + writel(readl(INTC_ICMR) & ~(0x1ff), INTC_ICMR);
253 253  
254 254 /*
255 255 * Set the appropriate edges for wakeup.
256 256 */
257   - GPIO_GRER = PM_PWER & GPIO_IRQ_rising_edge;
258   - GPIO_GFER = PM_PWER & GPIO_IRQ_falling_edge;
  257 + writel(readl(PM_PWER) & GPIO_IRQ_rising_edge, GPIO_GRER);
  258 + writel(readl(PM_PWER) & GPIO_IRQ_falling_edge, GPIO_GFER);
259 259  
260 260 /*
261 261 * Clear any pending GPIO interrupts.
262 262 */
263   - GPIO_GEDR = GPIO_GEDR;
  263 + writel(readl(GPIO_GEDR), GPIO_GEDR);
264 264  
265 265 return 0;
266 266 }
267 267  
268 268  
... ... @@ -270,13 +270,13 @@
270 270 struct puv3_irq_state *st = &puv3_irq_state;
271 271  
272 272 if (st->saved) {
273   - INTC_ICCR = st->iccr;
274   - INTC_ICLR = st->iclr;
  273 + writel(st->iccr, INTC_ICCR);
  274 + writel(st->iclr, INTC_ICLR);
275 275  
276   - GPIO_GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
277   - GPIO_GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  276 + writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
  277 + writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
278 278  
279   - INTC_ICMR = st->icmr;
  279 + writel(st->icmr, INTC_ICMR);
280 280 }
281 281 return 0;
282 282 }
283 283  
284 284  
285 285  
... ... @@ -307,18 +307,18 @@
307 307 request_resource(&iomem_resource, &irq_resource);
308 308  
309 309 /* disable all IRQs */
310   - INTC_ICMR = 0;
  310 + writel(0, INTC_ICMR);
311 311  
312 312 /* all IRQs are IRQ, not REAL */
313   - INTC_ICLR = 0;
  313 + writel(0, INTC_ICLR);
314 314  
315 315 /* clear all GPIO edge detects */
316   - GPIO_GPIR = FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ);
317   - GPIO_GFER = 0;
318   - GPIO_GRER = 0;
319   - GPIO_GEDR = 0x0FFFFFFF;
  316 + writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR);
  317 + writel(0, GPIO_GFER);
  318 + writel(0, GPIO_GRER);
  319 + writel(0x0FFFFFFF, GPIO_GEDR);
320 320  
321   - INTC_ICCR = 1;
  321 + writel(1, INTC_ICCR);
322 322  
323 323 for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
324 324 set_irq_chip(irq, &puv3_low_gpio_chip);
arch/unicore32/kernel/pci.c
Diff comments   View file @ e5abf78
... ... @@ -30,16 +30,16 @@
30 30 puv3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
31 31 int size, u32 *value)
32 32 {
33   - PCICFG_ADDR = CONFIG_CMD(bus, devfn, where);
  33 + writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
34 34 switch (size) {
35 35 case 1:
36   - *value = (PCICFG_DATA >> ((where & 3) * 8)) & 0xFF;
  36 + *value = (readl(PCICFG_DATA) >> ((where & 3) * 8)) & 0xFF;
37 37 break;
38 38 case 2:
39   - *value = (PCICFG_DATA >> ((where & 2) * 8)) & 0xFFFF;
  39 + *value = (readl(PCICFG_DATA) >> ((where & 2) * 8)) & 0xFFFF;
40 40 break;
41 41 case 4:
42   - *value = PCICFG_DATA;
  42 + *value = readl(PCICFG_DATA);
43 43 break;
44 44 }
45 45 return PCIBIOS_SUCCESSFUL;
46 46  
47 47  
48 48  
... ... @@ -49,18 +49,18 @@
49 49 puv3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
50 50 int size, u32 value)
51 51 {
52   - PCICFG_ADDR = CONFIG_CMD(bus, devfn, where);
  52 + writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
53 53 switch (size) {
54 54 case 1:
55   - PCICFG_DATA = (PCICFG_DATA & ~FMASK(8, (where&3)*8))
56   - | FIELD(value, 8, (where&3)*8);
  55 + writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8))
  56 + | FIELD(value, 8, (where&3)*8), PCICFG_DATA);
57 57 break;
58 58 case 2:
59   - PCICFG_DATA = (PCICFG_DATA & ~FMASK(16, (where&2)*8))
60   - | FIELD(value, 16, (where&2)*8);
  59 + writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8))
  60 + | FIELD(value, 16, (where&2)*8), PCICFG_DATA);
61 61 break;
62 62 case 4:
63   - PCICFG_DATA = value;
  63 + writel(value, PCICFG_DATA);
64 64 break;
65 65 }
66 66 return PCIBIOS_SUCCESSFUL;
67 67  
68 68  
69 69  
70 70  
71 71  
72 72  
... ... @@ -75,31 +75,31 @@
75 75 {
76 76 printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n");
77 77 /* config PCI bridge base */
78   - PCICFG_BRIBASE = PKUNITY_PCIBRI_BASE;
  78 + writel(PKUNITY_PCIBRI_BASE, PCICFG_BRIBASE);
79 79  
80   - PCIBRI_AHBCTL0 = 0;
81   - PCIBRI_AHBBAR0 = PKUNITY_PCIBRI_BASE | PCIBRI_BARx_MEM;
82   - PCIBRI_AHBAMR0 = 0xFFFF0000;
83   - PCIBRI_AHBTAR0 = 0;
  80 + writel(0, PCIBRI_AHBCTL0);
  81 + writel(PKUNITY_PCIBRI_BASE | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0);
  82 + writel(0xFFFF0000, PCIBRI_AHBAMR0);
  83 + writel(0, PCIBRI_AHBTAR0);
84 84  
85   - PCIBRI_AHBCTL1 = PCIBRI_CTLx_AT;
86   - PCIBRI_AHBBAR1 = PKUNITY_PCILIO_BASE | PCIBRI_BARx_IO;
87   - PCIBRI_AHBAMR1 = 0xFFFF0000;
88   - PCIBRI_AHBTAR1 = 0x00000000;
  85 + writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1);
  86 + writel(PKUNITY_PCILIO_BASE | PCIBRI_BARx_IO, PCIBRI_AHBBAR1);
  87 + writel(0xFFFF0000, PCIBRI_AHBAMR1);
  88 + writel(0x00000000, PCIBRI_AHBTAR1);
89 89  
90   - PCIBRI_AHBCTL2 = PCIBRI_CTLx_PREF;
91   - PCIBRI_AHBBAR2 = PKUNITY_PCIMEM_BASE | PCIBRI_BARx_MEM;
92   - PCIBRI_AHBAMR2 = 0xF8000000;
93   - PCIBRI_AHBTAR2 = 0;
  90 + writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2);
  91 + writel(PKUNITY_PCIMEM_BASE | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2);
  92 + writel(0xF8000000, PCIBRI_AHBAMR2);
  93 + writel(0, PCIBRI_AHBTAR2);
94 94  
95   - PCIBRI_BAR1 = PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM;
  95 + writel(PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM, PCIBRI_BAR1);
96 96  
97   - PCIBRI_PCICTL0 = PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF;
98   - PCIBRI_PCIBAR0 = PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM;
99   - PCIBRI_PCIAMR0 = 0xF8000000;
100   - PCIBRI_PCITAR0 = PKUNITY_SDRAM_BASE;
  97 + writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0);
  98 + writel(PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0);
  99 + writel(0xF8000000, PCIBRI_PCIAMR0);
  100 + writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0);
101 101  
102   - PCIBRI_CMD = PCIBRI_CMD | PCIBRI_CMD_IO | PCIBRI_CMD_MEM;
  102 + writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD);
103 103 }
104 104  
105 105 static int __init pci_puv3_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
arch/unicore32/kernel/process.c
Diff comments   View file @ e5abf78
... ... @@ -125,9 +125,9 @@
125 125 /* Jump into ROM at address 0xffff0000 */
126 126 cpu_reset(VECTORS_BASE);
127 127 } else {
128   - PM_PLLSYSCFG = 0x00002001; /* cpu clk = 250M */
129   - PM_PLLDDRCFG = 0x00100800; /* ddr clk = 44M */
130   - PM_PLLVGACFG = 0x00002001; /* vga clk = 250M */
  128 + writel(0x00002001, PM_PLLSYSCFG); /* cpu clk = 250M */
  129 + writel(0x00100800, PM_PLLDDRCFG); /* ddr clk = 44M */
  130 + writel(0x00002001, PM_PLLVGACFG); /* vga clk = 250M */
131 131  
132 132 /* Use on-chip reset capability */
133 133 /* following instructions must be in one icache line */
134 134  
... ... @@ -141,10 +141,10 @@
141 141 " nop; nop; nop\n\t"
142 142 /* prefetch 3 instructions at most */
143 143 :
144   - : "r" ((unsigned long)&PM_PMCR),
  144 + : "r" (PM_PMCR),
145 145 "r" (PM_PMCR_CFBSYS | PM_PMCR_CFBDDR
146 146 | PM_PMCR_CFBVGA),
147   - "r" ((unsigned long)&RESETC_SWRR),
  147 + "r" (RESETC_SWRR),
148 148 "r" (RESETC_SWRR_SRB)
149 149 : "r0", "memory");
150 150 }
arch/unicore32/kernel/puv3-core.c
Diff comments   View file @ e5abf78
... ... @@ -36,7 +36,7 @@
36 36 */
37 37 unsigned long long sched_clock(void)
38 38 {
39   - unsigned long long v = cnt32_to_63(OST_OSCR);
  39 + unsigned long long v = cnt32_to_63(readl(OST_OSCR));
40 40  
41 41 /* original conservative method, but overflow frequently
42 42 * v *= NSEC_PER_SEC >> 12;
43 43  
... ... @@ -187,15 +187,15 @@
187 187 static int puv3_cpu_pm_prepare(void)
188 188 {
189 189 /* set resume return address */
190   - PM_DIVCFG = virt_to_phys(puv3_cpu_resume);
  190 + writel(virt_to_phys(puv3_cpu_resume), PM_DIVCFG);
191 191 return 0;
192 192 }
193 193  
194 194 static void puv3_cpu_pm_enter(suspend_state_t state)
195 195 {
196 196 /* Clear reset status */
197   - RESETC_RSSR = RESETC_RSSR_HWR | RESETC_RSSR_WDR
198   - | RESETC_RSSR_SMR | RESETC_RSSR_SWR;
  197 + writel(RESETC_RSSR_HWR | RESETC_RSSR_WDR
  198 + | RESETC_RSSR_SMR | RESETC_RSSR_SWR, RESETC_RSSR);
199 199  
200 200 switch (state) {
201 201 /* case PM_SUSPEND_ON:
... ... @@ -242,7 +242,7 @@
242 242 struct clk *bclk32;
243 243  
244 244 bclk32 = clk_get(NULL, "BUS32_CLK");
245   - PS2_CNT = clk_get_rate(bclk32) / 200000; /* should > 5us */
  245 + writel(clk_get_rate(bclk32) / 200000, PS2_CNT); /* should > 5us */
246 246 }
247 247  
248 248 void __init puv3_core_init(void)
arch/unicore32/kernel/rtc.c
Diff comments   View file @ e5abf78
... ... @@ -41,7 +41,7 @@
41 41 {
42 42 struct rtc_device *rdev = id;
43 43  
44   - RTC_RTSR |= RTC_RTSR_AL;
  44 + writel(readl(RTC_RTSR) | RTC_RTSR_AL, RTC_RTSR);
45 45 rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
46 46 return IRQ_HANDLED;
47 47 }
... ... @@ -50,7 +50,7 @@
50 50 {
51 51 struct rtc_device *rdev = id;
52 52  
53   - RTC_RTSR |= RTC_RTSR_HZ;
  53 + writel(readl(RTC_RTSR) | RTC_RTSR_HZ, RTC_RTSR);
54 54 rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
55 55 return IRQ_HANDLED;
56 56 }
57 57  
... ... @@ -62,12 +62,12 @@
62 62  
63 63 pr_debug("%s: aie=%d\n", __func__, to);
64 64  
65   - tmp = RTC_RTSR & ~RTC_RTSR_ALE;
  65 + tmp = readl(RTC_RTSR) & ~RTC_RTSR_ALE;
66 66  
67 67 if (to)
68 68 tmp |= RTC_RTSR_ALE;
69 69  
70   - RTC_RTSR = tmp;
  70 + writel(tmp, RTC_RTSR);
71 71 }
72 72  
73 73 static int puv3_rtc_setpie(struct device *dev, int enabled)
74 74  
... ... @@ -77,12 +77,12 @@
77 77 pr_debug("%s: pie=%d\n", __func__, enabled);
78 78  
79 79 spin_lock_irq(&puv3_rtc_pie_lock);
80   - tmp = RTC_RTSR & ~RTC_RTSR_HZE;
  80 + tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE;
81 81  
82 82 if (enabled)
83 83 tmp |= RTC_RTSR_HZE;
84 84  
85   - RTC_RTSR = tmp;
  85 + writel(tmp, RTC_RTSR);
86 86 spin_unlock_irq(&puv3_rtc_pie_lock);
87 87  
88 88 return 0;
... ... @@ -97,7 +97,7 @@
97 97  
98 98 static int puv3_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
99 99 {
100   - rtc_time_to_tm(RTC_RCNR, rtc_tm);
  100 + rtc_time_to_tm(readl(RTC_RCNR), rtc_tm);
101 101  
102 102 pr_debug("read time %02x.%02x.%02x %02x/%02x/%02x\n",
103 103 rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
... ... @@ -115,7 +115,7 @@
115 115 tm->tm_hour, tm->tm_min, tm->tm_sec);
116 116  
117 117 rtc_tm_to_time(tm, &rtc_count);
118   - RTC_RCNR = rtc_count;
  118 + writel(rtc_count, RTC_RCNR);
119 119  
120 120 return 0;
121 121 }
122 122  
... ... @@ -124,9 +124,9 @@
124 124 {
125 125 struct rtc_time *alm_tm = &alrm->time;
126 126  
127   - rtc_time_to_tm(RTC_RTAR, alm_tm);
  127 + rtc_time_to_tm(readl(RTC_RTAR), alm_tm);
128 128  
129   - alrm->enabled = RTC_RTSR & RTC_RTSR_ALE;
  129 + alrm->enabled = readl(RTC_RTSR) & RTC_RTSR_ALE;
130 130  
131 131 pr_debug("read alarm %02x %02x.%02x.%02x %02x/%02x/%02x\n",
132 132 alrm->enabled,
... ... @@ -147,7 +147,7 @@
147 147 tm->tm_hour & 0xff, tm->tm_min & 0xff, tm->tm_sec);
148 148  
149 149 rtc_tm_to_time(tm, &rtcalarm_count);
150   - RTC_RTAR = rtcalarm_count;
  150 + writel(rtcalarm_count, RTC_RTAR);
151 151  
152 152 puv3_rtc_setaie(alrm->enabled);
153 153  
... ... @@ -162,7 +162,7 @@
162 162 static int puv3_rtc_proc(struct device *dev, struct seq_file *seq)
163 163 {
164 164 seq_printf(seq, "periodic_IRQ\t: %s\n",
165   - (RTC_RTSR & RTC_RTSR_HZE) ? "yes" : "no");
  165 + (readl(RTC_RTSR) & RTC_RTSR_HZE) ? "yes" : "no");
166 166 return 0;
167 167 }
168 168  
169 169  
170 170  
... ... @@ -222,13 +222,13 @@
222 222 static void puv3_rtc_enable(struct platform_device *pdev, int en)
223 223 {
224 224 if (!en) {
225   - RTC_RTSR &= ~RTC_RTSR_HZE;
  225 + writel(readl(RTC_RTSR) & ~RTC_RTSR_HZE, RTC_RTSR);
226 226 } else {
227 227 /* re-enable the device, and check it is ok */
228 228  
229   - if ((RTC_RTSR & RTC_RTSR_HZE) == 0) {
  229 + if ((readl(RTC_RTSR) & RTC_RTSR_HZE) == 0) {
230 230 dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
231   - RTC_RTSR |= RTC_RTSR_HZE;
  231 + writel(readl(RTC_RTSR) | RTC_RTSR_HZE, RTC_RTSR);
232 232 }
233 233 }
234 234 }
... ... @@ -331,7 +331,7 @@
331 331 static int puv3_rtc_suspend(struct platform_device *pdev, pm_message_t state)
332 332 {
333 333 /* save RTAR for anyone using periodic interrupts */
334   - ticnt_save = RTC_RTAR;
  334 + ticnt_save = readl(RTC_RTAR);
335 335 puv3_rtc_enable(pdev, 0);
336 336 return 0;
337 337 }
... ... @@ -339,7 +339,7 @@
339 339 static int puv3_rtc_resume(struct platform_device *pdev)
340 340 {
341 341 puv3_rtc_enable(pdev, 1);
342   - RTC_RTAR = ticnt_save;
  342 + writel(ticnt_save, RTC_RTAR);
343 343 return 0;
344 344 }
345 345 #else
arch/unicore32/kernel/time.c
Diff comments   View file @ e5abf78
... ... @@ -26,8 +26,8 @@
26 26 struct clock_event_device *c = dev_id;
27 27  
28 28 /* Disarm the compare/match, signal the event. */
29   - OST_OIER &= ~OST_OIER_E0;
30   - OST_OSSR &= ~OST_OSSR_M0;
  29 + writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER);
  30 + writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR);
31 31 c->event_handler(c);
32 32  
33 33 return IRQ_HANDLED;
... ... @@ -38,10 +38,10 @@
38 38 {
39 39 unsigned long next, oscr;
40 40  
41   - OST_OIER |= OST_OIER_E0;
42   - next = OST_OSCR + delta;
43   - OST_OSMR0 = next;
44   - oscr = OST_OSCR;
  41 + writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER);
  42 + next = readl(OST_OSCR) + delta;
  43 + writel(next, OST_OSMR0);
  44 + oscr = readl(OST_OSCR);
45 45  
46 46 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
47 47 }
... ... @@ -53,8 +53,8 @@
53 53 case CLOCK_EVT_MODE_ONESHOT:
54 54 case CLOCK_EVT_MODE_UNUSED:
55 55 case CLOCK_EVT_MODE_SHUTDOWN:
56   - OST_OIER &= ~OST_OIER_E0;
57   - OST_OSSR &= ~OST_OSSR_M0;
  56 + writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER);
  57 + writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR);
58 58 break;
59 59  
60 60 case CLOCK_EVT_MODE_RESUME:
... ... @@ -73,7 +73,7 @@
73 73  
74 74 static cycle_t puv3_read_oscr(struct clocksource *cs)
75 75 {
76   - return OST_OSCR;
  76 + return readl(OST_OSCR);
77 77 }
78 78  
79 79 static struct clocksource cksrc_puv3_oscr = {
... ... @@ -93,8 +93,8 @@
93 93  
94 94 void __init time_init(void)
95 95 {
96   - OST_OIER = 0; /* disable any timer interrupts */
97   - OST_OSSR = 0; /* clear status on all timers */
  96 + writel(0, OST_OIER); /* disable any timer interrupts */
  97 + writel(0, OST_OSSR); /* clear status on all timers */
98 98  
99 99 clockevents_calc_mult_shift(&ckevt_puv3_osmr0, CLOCK_TICK_RATE, 5);
100 100  
101 101  
102 102  
... ... @@ -115,26 +115,26 @@
115 115  
116 116 void puv3_timer_suspend(void)
117 117 {
118   - osmr[0] = OST_OSMR0;
119   - osmr[1] = OST_OSMR1;
120   - osmr[2] = OST_OSMR2;
121   - osmr[3] = OST_OSMR3;
122   - oier = OST_OIER;
  118 + osmr[0] = readl(OST_OSMR0);
  119 + osmr[1] = readl(OST_OSMR1);
  120 + osmr[2] = readl(OST_OSMR2);
  121 + osmr[3] = readl(OST_OSMR3);
  122 + oier = readl(OST_OIER);
123 123 }
124 124  
125 125 void puv3_timer_resume(void)
126 126 {
127   - OST_OSSR = 0;
128   - OST_OSMR0 = osmr[0];
129   - OST_OSMR1 = osmr[1];
130   - OST_OSMR2 = osmr[2];
131   - OST_OSMR3 = osmr[3];
132   - OST_OIER = oier;
  127 + writel(0, OST_OSSR);
  128 + writel(osmr[0], OST_OSMR0);
  129 + writel(osmr[1], OST_OSMR1);
  130 + writel(osmr[2], OST_OSMR2);
  131 + writel(osmr[3], OST_OSMR3);
  132 + writel(oier, OST_OIER);
133 133  
134 134 /*
135 135 * OSMR0 is the system timer: make sure OSCR is sufficiently behind
136 136 */
137   - OST_OSCR = OST_OSMR0 - LATCH;
  137 + writel(readl(OST_OSMR0) - LATCH, OST_OSCR);
138 138 }
139 139 #else
140 140 void puv3_timer_suspend(void) { };
drivers/input/serio/i8042-unicore32io.h
Diff comments   View file @ e5abf78
... ... @@ -29,11 +29,11 @@
29 29 /*
30 30 * Register numbers.
31 31 */
32   -#define I8042_COMMAND_REG ((volatile void __iomem *)&PS2_COMMAND)
33   -#define I8042_STATUS_REG ((volatile void __iomem *)&PS2_STATUS)
34   -#define I8042_DATA_REG ((volatile void __iomem *)&PS2_DATA)
  32 +#define I8042_COMMAND_REG PS2_COMMAND
  33 +#define I8042_STATUS_REG PS2_STATUS
  34 +#define I8042_DATA_REG PS2_DATA
35 35  
36   -#define I8042_REGION_START (resource_size_t)(&PS2_DATA)
  36 +#define I8042_REGION_START (resource_size_t)(PS2_DATA)
37 37 #define I8042_REGION_SIZE (resource_size_t)(16)
38 38  
39 39 static inline int i8042_read_data(void)