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Commit e8788babe6ddb35ab041a146d6b3e18874513566

Authored by Andrew Victor
Committed by Russell King
1 parent ce813b97e5
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] 4351/1: AT91: Define rest of peripheral clocks 

Define and register the remaining peripheral clocks for the AT91
processors.

AT91SAM9261 clocks patch by Ivan Zhakov.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 4 changed files with 84 additions and 9 deletions Side-by-side Diff

arch/arm/mach-at91/at91rm9200.c
Diff comments   View file @ e8788ba
... ... @@ -117,6 +117,21 @@
117 117 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
118 118 .type = CLK_TYPE_PERIPHERAL,
119 119 };
  120 +static struct clk ssc0_clk = {
  121 + .name = "ssc0_clk",
  122 + .pmc_mask = 1 << AT91RM9200_ID_SSC0,
  123 + .type = CLK_TYPE_PERIPHERAL,
  124 +};
  125 +static struct clk ssc1_clk = {
  126 + .name = "ssc1_clk",
  127 + .pmc_mask = 1 << AT91RM9200_ID_SSC1,
  128 + .type = CLK_TYPE_PERIPHERAL,
  129 +};
  130 +static struct clk ssc2_clk = {
  131 + .name = "ssc2_clk",
  132 + .pmc_mask = 1 << AT91RM9200_ID_SSC2,
  133 + .type = CLK_TYPE_PERIPHERAL,
  134 +};
120 135 static struct clk tc0_clk = {
121 136 .name = "tc0_clk",
122 137 .pmc_mask = 1 << AT91RM9200_ID_TC0,
... ... @@ -161,7 +176,9 @@
161 176 &udc_clk,
162 177 &twi_clk,
163 178 &spi_clk,
164   - // ssc 0 .. ssc2
  179 + &ssc0_clk,
  180 + &ssc1_clk,
  181 + &ssc2_clk,
165 182 &tc0_clk,
166 183 &tc1_clk,
167 184 &tc2_clk,
arch/arm/mach-at91/at91sam9260.c
Diff comments   View file @ e8788ba
... ... @@ -119,6 +119,11 @@
119 119 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
120 120 .type = CLK_TYPE_PERIPHERAL,
121 121 };
  122 +static struct clk ssc_clk = {
  123 + .name = "ssc_clk",
  124 + .pmc_mask = 1 << AT91SAM9260_ID_SSC,
  125 + .type = CLK_TYPE_PERIPHERAL,
  126 +};
122 127 static struct clk tc0_clk = {
123 128 .name = "tc0_clk",
124 129 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
... ... @@ -193,7 +198,7 @@
193 198 &twi_clk,
194 199 &spi0_clk,
195 200 &spi1_clk,
196   - // ssc
  201 + &ssc_clk,
197 202 &tc0_clk,
198 203 &tc1_clk,
199 204 &tc2_clk,
arch/arm/mach-at91/at91sam9261.c
Diff comments   View file @ e8788ba
... ... @@ -97,6 +97,21 @@
97 97 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
98 98 .type = CLK_TYPE_PERIPHERAL,
99 99 };
  100 +static struct clk ssc0_clk = {
  101 + .name = "ssc0_clk",
  102 + .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
  103 + .type = CLK_TYPE_PERIPHERAL,
  104 +};
  105 +static struct clk ssc1_clk = {
  106 + .name = "ssc1_clk",
  107 + .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
  108 + .type = CLK_TYPE_PERIPHERAL,
  109 +};
  110 +static struct clk ssc2_clk = {
  111 + .name = "ssc2_clk",
  112 + .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
  113 + .type = CLK_TYPE_PERIPHERAL,
  114 +};
100 115 static struct clk tc0_clk = {
101 116 .name = "tc0_clk",
102 117 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
... ... @@ -135,7 +150,9 @@
135 150 &twi_clk,
136 151 &spi0_clk,
137 152 &spi1_clk,
138   - // ssc 0 .. ssc2
  153 + &ssc0_clk,
  154 + &ssc1_clk,
  155 + &ssc2_clk,
139 156 &tc0_clk,
140 157 &tc1_clk,
141 158 &tc2_clk,
arch/arm/mach-at91/at91sam9263.c
Diff comments   View file @ e8788ba
... ... @@ -87,6 +87,11 @@
87 87 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
88 88 .type = CLK_TYPE_PERIPHERAL,
89 89 };
  90 +static struct clk can_clk = {
  91 + .name = "can_clk",
  92 + .pmc_mask = 1 << AT91SAM9263_ID_CAN,
  93 + .type = CLK_TYPE_PERIPHERAL,
  94 +};
90 95 static struct clk twi_clk = {
91 96 .name = "twi_clk",
92 97 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
93 98  
94 99  
... ... @@ -102,16 +107,46 @@
102 107 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
103 108 .type = CLK_TYPE_PERIPHERAL,
104 109 };
  110 +static struct clk ssc0_clk = {
  111 + .name = "ssc0_clk",
  112 + .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
  113 + .type = CLK_TYPE_PERIPHERAL,
  114 +};
  115 +static struct clk ssc1_clk = {
  116 + .name = "ssc1_clk",
  117 + .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
  118 + .type = CLK_TYPE_PERIPHERAL,
  119 +};
  120 +static struct clk ac97_clk = {
  121 + .name = "ac97_clk",
  122 + .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
  123 + .type = CLK_TYPE_PERIPHERAL,
  124 +};
105 125 static struct clk tcb_clk = {
106 126 .name = "tcb_clk",
107 127 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
108 128 .type = CLK_TYPE_PERIPHERAL,
109 129 };
  130 +static struct clk pwmc_clk = {
  131 + .name = "pwmc_clk",
  132 + .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
  133 + .type = CLK_TYPE_PERIPHERAL,
  134 +};
110 135 static struct clk macb_clk = {
111 136 .name = "macb_clk",
112 137 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
113 138 .type = CLK_TYPE_PERIPHERAL,
114 139 };
  140 +static struct clk dma_clk = {
  141 + .name = "dma_clk",
  142 + .pmc_mask = 1 << AT91SAM9263_ID_DMA,
  143 + .type = CLK_TYPE_PERIPHERAL,
  144 +};
  145 +static struct clk twodge_clk = {
  146 + .name = "2dge_clk",
  147 + .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
  148 + .type = CLK_TYPE_PERIPHERAL,
  149 +};
115 150 static struct clk udc_clk = {
116 151 .name = "udc_clk",
117 152 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
118 153  
119 154  
120 155  
121 156  
... ... @@ -142,20 +177,21 @@
142 177 &usart2_clk,
143 178 &mmc0_clk,
144 179 &mmc1_clk,
145   - // can
  180 + &can_clk,
146 181 &twi_clk,
147 182 &spi0_clk,
148 183 &spi1_clk,
149   - // ssc0 .. ssc1
150   - // ac97
  184 + &ssc0_clk,
  185 + &ssc1_clk,
  186 + &ac97_clk,
151 187 &tcb_clk,
152   - // pwmc
  188 + &pwmc_clk,
153 189 &macb_clk,
154   - // 2dge
  190 + &twodge_clk,
155 191 &udc_clk,
156 192 &isi_clk,
157 193 &lcdc_clk,
158   - // dma
  194 + &dma_clk,
159 195 &ohci_clk,
160 196 // irq0 .. irq1
161 197 };