sh: sh775x/titan fixes for irq header changes.

The following moves the creation of IPR interupts into setup-7750.c and updates a few other things to make it all work after the "Drop CPU subtype IRQ headers" commit. It boots and runs fine on my titan board. - adds an ipr_idx to the ipr_data and uses a function in the subtype code to calculate the address of the IPR registers - adds a function to enable individual interrupt mode for externals in the subtype code and calls that from the titan board code instead of doing it directly. - I changed the shift in the ipr_data to be the actual # of bits to shift, instead of the numnber / 4 - made it easier to match with the manual. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>

sh: sh775x/titan fixes for irq header changes.
The following moves the creation of IPR interupts into setup-7750.c and updates a few other things to make it all work after the "Drop CPU subtype IRQ headers" commit. It boots and runs fine on my titan board. - adds an ipr_idx to the ipr_data and uses a function in the subtype code to calculate the address of the IPR registers - adds a function to enable individual interrupt mode for externals in the subtype code and calls that from the titan board code instead of doing it directly. - I changed the shift in the ipr_data to be the actual # of bits to shift, instead of the numnber / 4 - made it easier to match with the manual. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Jamie Lenehan · Paul Mundt
1 parent fe9687dec0
Showing 10 changed files with 165 additions and 159 deletions Side-by-side Diff
arch/sh/Kconfig
arch/sh/boards/titan/setup.c
arch/sh/drivers/pci/ops-titan.c
arch/sh/kernel/cpu/irq/Makefile
arch/sh/kernel/cpu/irq/ipr.c
arch/sh/kernel/cpu/sh4/setup-sh7750.c
arch/sh/kernel/irq.c
arch/sh/mm/Kconfig
include/asm-sh/irq.h
include/asm-sh/titan.h
@@ -375,6 +375,9 @@
 config CPU_HAS_INTC2_IRQ
 	bool
  
+config CPU_HAS_IPR_IRQ
+	bool
+
 config CPU_HAS_SR_RB
 	bool "CPU has SR.RB"
 	depends on CPU_SH3 || CPU_SH4
 /*
- *	Setup for Titan
+ * arch/sh/boards/titan/setup.c - Setup for Titan
+ *
+ *  Copyright (C) 2006  Jamie Lenehan
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  */
-
 #include <linux/init.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/titan.h>
 #include <asm/io.h>
  
-extern void __init pcibios_init_platform(void);
-
 static struct ipr_data titan_ipr_map[] = {
-	{ TITAN_IRQ_WAN,	IRL0_IPR_ADDR,	IRL0_IPR_POS,	IRL0_PRIORITY },
-	{ TITAN_IRQ_LAN,	IRL1_IPR_ADDR,	IRL1_IPR_POS,	IRL1_PRIORITY },
-	{ TITAN_IRQ_MPCIA,	IRL2_IPR_ADDR,	IRL2_IPR_POS,	IRL2_PRIORITY },
-	{ TITAN_IRQ_USB,	IRL3_IPR_ADDR,	IRL3_IPR_POS,	IRL3_PRIORITY },
+	/* IRQ, IPR idx, shift, prio */
+	{ TITAN_IRQ_WAN,   3, 12, 8 },	/* eth0 (WAN) */
+	{ TITAN_IRQ_LAN,   3,  8, 8 },	/* eth1 (LAN) */
+	{ TITAN_IRQ_MPCIA, 3,  4, 8 },	/* mPCI A (top) */
+	{ TITAN_IRQ_USB,   3,  0, 8 },	/* mPCI B (bottom), USB */
 };
  
 static void __init init_titan_irq(void)
 {
 	/* enable individual interrupt mode for externals */
-	ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
-
+	ipr_irq_enable_irlm();
+	/* register ipr irqs */
 	make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map));
 }
  
@@ -47,7 +51,6 @@
 	.mv_ioport_map = titan_ioport_map,
  
 	.mv_init_irq =	init_titan_irq,
-	.mv_init_pci =	pcibios_init_platform,
 };
 ALIAS_MV(titan)
@@ -15,25 +15,21 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/titan.h>
 #include "pci-sh4.h"
  
+static char titan_irq_tab[] __initdata = {
+	TITAN_IRQ_WAN,
+	TITAN_IRQ_LAN,
+	TITAN_IRQ_MPCIA,
+	TITAN_IRQ_MPCIB,
+	TITAN_IRQ_USB,
+};
+
 int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 {
-	int irq = -1;
-
-	switch (slot) {
-	case 0: irq = TITAN_IRQ_WAN;   break;	/* eth0 (WAN) */
-	case 1: irq = TITAN_IRQ_LAN;   break;	/* eth1 (LAN) */
-	case 2: irq = TITAN_IRQ_MPCIA; break;	/* mPCI A */
-	case 3: irq = TITAN_IRQ_MPCIB; break;	/* mPCI B */
-	case 4: irq = TITAN_IRQ_USB;   break;	/* USB */
-	default:
-		printk(KERN_INFO "PCI: Bad IRQ mapping "
-				 "request for slot %d\n", slot);
-		return -1;
-	}
+	int irq = titan_irq_tab[slot];
  
 	printk("PCI: Mapping TITAN IRQ for slot %d, pin %c to irq %d\n",
 		slot, pin - 1 + 'A', irq);
 #
 # Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
 #
-obj-y	+= ipr.o imask.o
+obj-y	+= imask.o
  
+obj-$(CONFIG_CPU_HAS_IPR_IRQ)		+= ipr.o
 obj-$(CONFIG_CPU_HAS_PINT_IRQ)		+= pint.o
 obj-$(CONFIG_CPU_HAS_MASKREG_IRQ)	+= maskreg.o
 obj-$(CONFIG_CPU_HAS_INTC2_IRQ)		+= intc2.o
@@ -25,17 +25,15 @@
 static void disable_ipr_irq(unsigned int irq)
 {
 	struct ipr_data *p = get_irq_chip_data(irq);
-	int shift = p->shift*4;
 	/* Set the priority in IPR to 0 */
-	ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
+	ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
 }
  
 static void enable_ipr_irq(unsigned int irq)
 {
 	struct ipr_data *p = get_irq_chip_data(irq);
-	int shift = p->shift*4;
 	/* Set priority in IPR back to original value */
-	ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr);
+	ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
 }
  
 static struct irq_chip ipr_irq_chip = {
@@ -51,6 +49,10 @@
  
 	for (i = 0; i < nr_irqs; i++) {
 		unsigned int irq = table[i].irq;
+		table[i].addr = map_ipridx_to_addr(table[i].ipr_idx);
+		/* could the IPR index be mapped, if not we ignore this */
+		if (table[i].addr == 0)
+			continue;
 		disable_irq_nosync(irq);
 		set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
 				      handle_level_irq, "level");
@@ -59,99 +61,6 @@
 	}
 }
 EXPORT_SYMBOL(make_ipr_irq);
-
-/*
- * XXX: Move this garbage in to the drivers, and kill off the ridiculous CPU
- * subtype checks.
- */
-static struct ipr_data sys_ipr_map[] = {
-#ifndef CONFIG_CPU_SUBTYPE_SH7780
-	{ TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
-	{ TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
-#ifdef RTC_IRQ
-	{ RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
-#endif
-#ifdef SCI_ERI_IRQ
-	{ SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
-	{ SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
-	{ SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
-#endif
-#ifdef SCIF1_ERI_IRQ
-	{ SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
-	{ SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
-	{ SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
-	{ SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
-#endif
-#ifdef SCIF2_ERI_IRQ
-	{ SCIF2_ERI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
-	{ SCIF2_RXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
-	{ SCIF2_BRI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
-	{ SCIF2_TXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
-#endif
-#ifdef SCIF3_ERI_IRQ
-	{ SCIF3_ERI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
-	{ SCIF3_RXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
-	{ SCIF3_BRI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
-	{ SCIF3_TXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
-	{ SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
-	{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
-	{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
-	{ VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
-#endif
-#ifdef SCIF_ERI_IRQ
-	{ SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
-	{ SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
-	{ SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
-	{ SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
-#endif
-#ifdef IRDA_ERI_IRQ
-	{ IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
-	{ IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
-	{ IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
-	{ IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7706) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
-	/*
-	 * Initialize the Interrupt Controller (INTC)
-	 * registers to their power on values
-	 */
-
-	/*
-	 * Enable external irq (INTC IRQ mode).
-	 * You should set corresponding bits of PFC to "00"
-	 * to enable these interrupts.
-	 */
-	{ IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
-	{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
-	{ IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
-	{ IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
-	{ IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
-	{ IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
-#endif
-#endif
-};
-
-void __init init_IRQ(void)
-{
-	make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
-
-#ifdef CONFIG_CPU_HAS_PINT_IRQ
-	init_IRQ_pint();
-#endif
-
-#ifdef CONFIG_CPU_HAS_INTC2_IRQ
-	init_IRQ_intc2();
-#endif
-	/* Perform the machine specific initialisation */
-	if (sh_mv.mv_init_irq != NULL)
-		sh_mv.mv_init_irq();
-
-	irq_ctx_init(smp_processor_id());
-}
  
 #if !defined(CONFIG_CPU_HAS_PINT_IRQ)
 int ipr_irq_demux(int irq)
@@ -2,6 +2,7 @@
  * SH7750/SH7751 Setup
  *
  *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2006  Jamie Lenehan
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -10,6 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/serial.h>
+#include <linux/io.h>
 #include <asm/sci.h>
  
 static struct plat_sci_port sci_platform_data[] = {
@@ -46,4 +48,72 @@
 				    ARRAY_SIZE(sh7750_devices));
 }
 __initcall(sh7750_devices_setup);
+
+static struct ipr_data sh7750_ipr_map[] = {
+	/* IRQ, IPR-idx, shift, priority */
+	{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
+	{ 17, 0, 12, 2 }, /* TMU1 TUNI */
+	{ 18, 0,  4, 2 }, /* TMU2 TUNI */
+	{ 19, 0,  4, 2 }, /* TMU2 TIPCI */
+	{ 27, 1, 12, 2 }, /* WDT ITI */
+	{ 20, 0,  0, 2 }, /* RTC ATI (alarm) */
+	{ 21, 0,  0, 2 }, /* RTC PRI (period) */
+	{ 22, 0,  0, 2 }, /* RTC CUI (carry) */
+	{ 23, 1,  4, 3 }, /* SCI ERI */
+	{ 24, 1,  4, 3 }, /* SCI RXI */
+	{ 25, 1,  4, 3 }, /* SCI TXI */
+	{ 40, 2,  4, 3 }, /* SCIF ERI */
+	{ 41, 2,  4, 3 }, /* SCIF RXI */
+	{ 42, 2,  4, 3 }, /* SCIF BRI */
+	{ 43, 2,  4, 3 }, /* SCIF TXI */
+	{ 34, 2,  8, 7 }, /* DMAC DMTE0 */
+	{ 35, 2,  8, 7 }, /* DMAC DMTE1 */
+	{ 36, 2,  8, 7 }, /* DMAC DMTE2 */
+	{ 37, 2,  8, 7 }, /* DMAC DMTE3 */
+	{ 28, 2,  8, 7 }, /* DMAC DMAE */
+};
+
+static struct ipr_data sh7751_ipr_map[] = {
+	{ 44, 2,  8, 7 }, /* DMAC DMTE4 */
+	{ 45, 2,  8, 7 }, /* DMAC DMTE5 */
+	{ 46, 2,  8, 7 }, /* DMAC DMTE6 */
+	{ 47, 2,  8, 7 }, /* DMAC DMTE7 */
+	/* The following use INTC_INPRI00 for masking, which is a 32-bit
+	   register, not a 16-bit register like the IPRx registers, so it
+	   would need special support */
+	/*{ 72, INTPRI00,  8, ? },*/ /* TMU3 TUNI */
+	/*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
+};
+
+static unsigned long ipr_offsets[] = {
+	0xffd00004UL,	/* 0: IPRA */
+	0xffd00008UL,	/* 1: IPRB */
+	0xffd0000cUL,	/* 2: IPRC */
+	0xffd00010UL,	/* 3: IPRD */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+	if (idx >= ARRAY_SIZE(ipr_offsets))
+		return 0;
+	return ipr_offsets[idx];
+}
+
+#define INTC_ICR	0xffd00000UL
+#define INTC_ICR_IRLM   (1<<7)
+
+/* enable individual interrupt mode for external interupts */
+void ipr_irq_enable_irlm(void)
+{
+	ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+}
+
+void __init init_IRQ_ipr()
+{
+	make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map));
+#ifdef CONFIG_CPU_SUBTYPE_SH7751
+	make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map));
+#endif
+}
@@ -12,7 +12,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/seq_file.h>
 #include <linux/io.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
 #include <asm/processor.h>
 #include <asm/uaccess.h>
 #include <asm/thread_info.h>
@@ -112,7 +112,7 @@
 #endif
  
 #ifdef CONFIG_CPU_HAS_INTEVT
-	irq = (ctrl_inl(INTEVT) >> 5) - 16;
+	irq = evt2irq(ctrl_inl(INTEVT));
 #else
 	irq = r4;
 #endif
@@ -261,4 +261,25 @@
 }
 EXPORT_SYMBOL(do_softirq);
 #endif
+
+void __init init_IRQ(void)
+{
+#ifdef CONFIG_CPU_HAS_PINT_IRQ
+	init_IRQ_pint();
+#endif
+
+#ifdef CONFIG_CPU_HAS_INTC2_IRQ
+	init_IRQ_intc2();
+#endif
+
+#ifdef CONFIG_CPU_HAS_IPR_IRQ
+	init_IRQ_ipr();
+#endif
+
+	/* Perform the machine specific initialisation */
+	if (sh_mv.mv_init_irq)
+		sh_mv.mv_init_irq();
+
+	irq_ctx_init(smp_processor_id());
+}
@@ -104,6 +104,7 @@
 config CPU_SUBTYPE_SH7750
 	bool "Support SH7750 processor"
 	select CPU_SH4
+	select CPU_HAS_IPR_IRQ
 	help
 	  Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
  
  
  
@@ -119,15 +120,18 @@
 	bool "Support SH7750R processor"
 	select CPU_SH4
 	select CPU_SUBTYPE_SH7750
+	select CPU_HAS_IPR_IRQ
  
 config CPU_SUBTYPE_SH7750S
 	bool "Support SH7750S processor"
 	select CPU_SH4
 	select CPU_SUBTYPE_SH7750
+	select CPU_HAS_IPR_IRQ
  
 config CPU_SUBTYPE_SH7751
 	bool "Support SH7751 processor"
 	select CPU_SH4
+	select CPU_HAS_IPR_IRQ
 	help
 	  Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
 	  or if you have a HD6417751R CPU.
@@ -136,6 +140,7 @@
 	bool "Support SH7751R processor"
 	select CPU_SH4
 	select CPU_SUBTYPE_SH7751
+	select CPU_HAS_IPR_IRQ
  
 config CPU_SUBTYPE_SH7760
 	bool "Support SH7760 processor"
@@ -93,6 +93,12 @@
 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
  
 /*
+ * Convert back and forth between INTEVT and IRQ values.
+ */
+#define evt2irq(evt)		(((evt) >> 5) - 16)
+#define irq2evt(irq)		(((irq) + 16) << 5)
+
+/*
  * Simple Mask Register Support
  */
 extern void make_maskreg_irq(unsigned int irq);
  
  
  
  
@@ -103,18 +109,36 @@
  */
 void init_IRQ_pint(void);
  
+/*
+ * The shift value is now the number of bits to shift, not the number of
+ * bits/4. This is to make it easier to read the value directly from the
+ * datasheets. The IPR address, addr, will be set from ipr_idx via the
+ * map_ipridx_to_addr function.
+ */
 struct ipr_data {
 	unsigned int irq;
-	unsigned int addr;	/* Address of Interrupt Priority Register */
-	int shift;		/* Shifts of the 16-bit data */
+	int ipr_idx;		/* Index for the IPR registered */
+	int shift;		/* Number of bits to shift the data */
 	int priority;		/* The priority */
+	unsigned int addr;	/* Address of Interrupt Priority Register */
 };
  
 /*
+ * Given an IPR IDX, map the value to an IPR register address.
+ */
+unsigned int map_ipridx_to_addr(int idx);
+
+/*
+ * Enable individual interrupt mode for external IPR IRQs.
+ */
+void ipr_irq_enable_irlm(void);
+
+/*
  * Function for "on chip support modules".
  */
-extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
-extern void make_imask_irq(unsigned int irq);
+void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
+void make_imask_irq(unsigned int irq);
+void init_IRQ_ipr(void);
  
 struct intc2_data {
 	unsigned short irq;
 /*
  * Platform defintions for Titan
  */
+#ifndef _ASM_SH_TITAN_H
+#define _ASM_SH_TITAN_H
  
-#ifndef _ASM_SH_TITAN_TITAN_H
-#define _ASM_SH_TITAN_TITAN_H
-
 #define __IO_PREFIX titan
 #include <asm/io_generic.h>
  
@@ -15,30 +14,5 @@
 #define TITAN_IRQ_MPCIB		11	/* mPCI B */
 #define TITAN_IRQ_USB		11	/* USB */
  
-/*
- * The external interrupt lines, these take up ints 0 - 15 inclusive
- * depending on the priority for the interrupt.  In fact the priority
- * is the interrupt :-)
- */
-#define IRL0_IRQ	0
-#define IRL0_IPR_ADDR	INTC_IPRD
-#define IRL0_IPR_POS	3
-#define IRL0_PRIORITY	8
-
-#define IRL1_IRQ	1
-#define IRL1_IPR_ADDR	INTC_IPRD
-#define IRL1_IPR_POS	2
-#define IRL1_PRIORITY	8
-
-#define IRL2_IRQ	2
-#define IRL2_IPR_ADDR	INTC_IPRD
-#define IRL2_IPR_POS	1
-#define IRL2_PRIORITY	8
-
-#define IRL3_IRQ	3
-#define IRL3_IPR_ADDR	INTC_IPRD
-#define IRL3_IPR_POS	0
-#define IRL3_PRIORITY	8
-
-#endif
+#endif /* __ASM_SH_TITAN_H */
...	...	@@ -375,6 +375,9 @@
375	375	config CPU_HAS_INTC2_IRQ
376	376	bool
377	377
	378	+config CPU_HAS_IPR_IRQ
	379	+ bool
	380	+
378	381	config CPU_HAS_SR_RB
379	382	bool "CPU has SR.RB"
380	383	depends on CPU_SH3 \|\| CPU_SH4
1	1	/*
2		- * Setup for Titan
	2	+ * arch/sh/boards/titan/setup.c - Setup for Titan
	3	+ *
	4	+ * Copyright (C) 2006 Jamie Lenehan
	5	+ *
	6	+ * This file is subject to the terms and conditions of the GNU General Public
	7	+ * License. See the file "COPYING" in the main directory of this archive
	8	+ * for more details.
3	9	*/
4		-
5	10	#include <linux/init.h>
6		-#include <asm/irq.h>
	11	+#include <linux/irq.h>
7	12	#include <asm/titan.h>
8	13	#include <asm/io.h>
9	14
10		-extern void __init pcibios_init_platform(void);
11		-
12	15	static struct ipr_data titan_ipr_map[] = {
13		- { TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY },
14		- { TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY },
15		- { TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY },
16		- { TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY },
	16	+ /* IRQ, IPR idx, shift, prio */
	17	+ { TITAN_IRQ_WAN, 3, 12, 8 }, /* eth0 (WAN) */
	18	+ { TITAN_IRQ_LAN, 3, 8, 8 }, /* eth1 (LAN) */
	19	+ { TITAN_IRQ_MPCIA, 3, 4, 8 }, /* mPCI A (top) */
	20	+ { TITAN_IRQ_USB, 3, 0, 8 }, /* mPCI B (bottom), USB */
17	21	};
18	22
19	23	static void __init init_titan_irq(void)
20	24	{
21	25	/* enable individual interrupt mode for externals */
22		- ctrl_outw(ctrl_inw(INTC_ICR) \| INTC_ICR_IRLM, INTC_ICR);
23		-
	26	+ ipr_irq_enable_irlm();
	27	+ /* register ipr irqs */
24	28	make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map));
25	29	}
26	30
...	...	@@ -47,7 +51,6 @@
47	51	.mv_ioport_map = titan_ioport_map,
48	52
49	53	.mv_init_irq = init_titan_irq,
50		- .mv_init_pci = pcibios_init_platform,
51	54	};
52	55	ALIAS_MV(titan)
...	...	@@ -15,25 +15,21 @@
15	15	#include <linux/types.h>
16	16	#include <linux/init.h>
17	17	#include <linux/pci.h>
18		-#include <asm/io.h>
	18	+#include <linux/io.h>
19	19	#include <asm/titan.h>
20	20	#include "pci-sh4.h"
21	21
	22	+static char titan_irq_tab[] __initdata = {
	23	+ TITAN_IRQ_WAN,
	24	+ TITAN_IRQ_LAN,
	25	+ TITAN_IRQ_MPCIA,
	26	+ TITAN_IRQ_MPCIB,
	27	+ TITAN_IRQ_USB,
	28	+};
	29	+
22	30	int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
23	31	{
24		- int irq = -1;
25		-
26		- switch (slot) {
27		- case 0: irq = TITAN_IRQ_WAN; break; /* eth0 (WAN) */
28		- case 1: irq = TITAN_IRQ_LAN; break; /* eth1 (LAN) */
29		- case 2: irq = TITAN_IRQ_MPCIA; break; /* mPCI A */
30		- case 3: irq = TITAN_IRQ_MPCIB; break; /* mPCI B */
31		- case 4: irq = TITAN_IRQ_USB; break; /* USB */
32		- default:
33		- printk(KERN_INFO "PCI: Bad IRQ mapping "
34		- "request for slot %d\n", slot);
35		- return -1;
36		- }
	32	+ int irq = titan_irq_tab[slot];
37	33
38	34	printk("PCI: Mapping TITAN IRQ for slot %d, pin %c to irq %d\n",
39	35	slot, pin - 1 + 'A', irq);
1	1	#
2	2	# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
3	3	#
4		-obj-y += ipr.o imask.o
	4	+obj-y += imask.o
5	5
	6	+obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
6	7	obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
7	8	obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
8	9	obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
...	...	@@ -25,17 +25,15 @@
25	25	static void disable_ipr_irq(unsigned int irq)
26	26	{
27	27	struct ipr_data *p = get_irq_chip_data(irq);
28		- int shift = p->shift*4;
29	28	/* Set the priority in IPR to 0 */
30		- ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
	29	+ ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
31	30	}
32	31
33	32	static void enable_ipr_irq(unsigned int irq)
34	33	{
35	34	struct ipr_data *p = get_irq_chip_data(irq);
36		- int shift = p->shift*4;
37	35	/* Set priority in IPR back to original value */
38		- ctrl_outw(ctrl_inw(p->addr) \| (p->priority << shift), p->addr);
	36	+ ctrl_outw(ctrl_inw(p->addr) \| (p->priority << p->shift), p->addr);
39	37	}
40	38
41	39	static struct irq_chip ipr_irq_chip = {
...	...	@@ -51,6 +49,10 @@
51	49
52	50	for (i = 0; i < nr_irqs; i++) {
53	51	unsigned int irq = table[i].irq;
	52	+ table[i].addr = map_ipridx_to_addr(table[i].ipr_idx);
	53	+ /* could the IPR index be mapped, if not we ignore this */
	54	+ if (table[i].addr == 0)
	55	+ continue;
54	56	disable_irq_nosync(irq);
55	57	set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
56	58	handle_level_irq, "level");
...	...	@@ -59,99 +61,6 @@
59	61	}
60	62	}
61	63	EXPORT_SYMBOL(make_ipr_irq);
62		-
63		-/*
64		- * XXX: Move this garbage in to the drivers, and kill off the ridiculous CPU
65		- * subtype checks.
66		- */
67		-static struct ipr_data sys_ipr_map[] = {
68		-#ifndef CONFIG_CPU_SUBTYPE_SH7780
69		- { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
70		- { TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
71		-#ifdef RTC_IRQ
72		- { RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
73		-#endif
74		-#ifdef SCI_ERI_IRQ
75		- { SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
76		- { SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
77		- { SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
78		-#endif
79		-#ifdef SCIF1_ERI_IRQ
80		- { SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
81		- { SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
82		- { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
83		- { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
84		-#endif
85		-#ifdef SCIF2_ERI_IRQ
86		- { SCIF2_ERI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
87		- { SCIF2_RXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
88		- { SCIF2_BRI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
89		- { SCIF2_TXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
90		-#endif
91		-#ifdef SCIF3_ERI_IRQ
92		- { SCIF3_ERI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
93		- { SCIF3_RXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
94		- { SCIF3_BRI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
95		- { SCIF3_TXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
96		-#endif
97		-#if defined(CONFIG_CPU_SUBTYPE_SH7300)
98		- { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
99		- { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
100		- { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
101		- { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
102		-#endif
103		-#ifdef SCIF_ERI_IRQ
104		- { SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
105		- { SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
106		- { SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
107		- { SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
108		-#endif
109		-#ifdef IRDA_ERI_IRQ
110		- { IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
111		- { IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
112		- { IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
113		- { IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
114		-#endif
115		-#if defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| defined(CONFIG_CPU_SUBTYPE_SH7709) \|\| \
116		- defined(CONFIG_CPU_SUBTYPE_SH7706) \|\| \
117		- defined(CONFIG_CPU_SUBTYPE_SH7300) \|\| defined(CONFIG_CPU_SUBTYPE_SH7705)
118		- /*
119		- * Initialize the Interrupt Controller (INTC)
120		- * registers to their power on values
121		- */
122		-
123		- /*
124		- * Enable external irq (INTC IRQ mode).
125		- * You should set corresponding bits of PFC to "00"
126		- * to enable these interrupts.
127		- */
128		- { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
129		- { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
130		- { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
131		- { IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
132		- { IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
133		- { IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
134		-#endif
135		-#endif
136		-};
137		-
138		-void __init init_IRQ(void)
139		-{
140		- make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
141		-
142		-#ifdef CONFIG_CPU_HAS_PINT_IRQ
143		- init_IRQ_pint();
144		-#endif
145		-
146		-#ifdef CONFIG_CPU_HAS_INTC2_IRQ
147		- init_IRQ_intc2();
148		-#endif
149		- /* Perform the machine specific initialisation */
150		- if (sh_mv.mv_init_irq != NULL)
151		- sh_mv.mv_init_irq();
152		-
153		- irq_ctx_init(smp_processor_id());
154		-}
155	64
156	65	#if !defined(CONFIG_CPU_HAS_PINT_IRQ)
157	66	int ipr_irq_demux(int irq)
...	...	@@ -2,6 +2,7 @@
2	2	* SH7750/SH7751 Setup
3	3	*
4	4	* Copyright (C) 2006 Paul Mundt
	5	+ * Copyright (C) 2006 Jamie Lenehan
5	6	*
6	7	* This file is subject to the terms and conditions of the GNU General Public
7	8	* License. See the file "COPYING" in the main directory of this archive
...	...	@@ -10,6 +11,7 @@
10	11	#include <linux/platform_device.h>
11	12	#include <linux/init.h>
12	13	#include <linux/serial.h>
	14	+#include <linux/io.h>
13	15	#include <asm/sci.h>
14	16
15	17	static struct plat_sci_port sci_platform_data[] = {
...	...	@@ -46,4 +48,72 @@
46	48	ARRAY_SIZE(sh7750_devices));
47	49	}
48	50	__initcall(sh7750_devices_setup);
	51	+
	52	+static struct ipr_data sh7750_ipr_map[] = {
	53	+ /* IRQ, IPR-idx, shift, priority */
	54	+ { 16, 0, 12, 2 }, /* TMU0 TUNI*/
	55	+ { 17, 0, 12, 2 }, /* TMU1 TUNI */
	56	+ { 18, 0, 4, 2 }, /* TMU2 TUNI */
	57	+ { 19, 0, 4, 2 }, /* TMU2 TIPCI */
	58	+ { 27, 1, 12, 2 }, /* WDT ITI */
	59	+ { 20, 0, 0, 2 }, /* RTC ATI (alarm) */
	60	+ { 21, 0, 0, 2 }, /* RTC PRI (period) */
	61	+ { 22, 0, 0, 2 }, /* RTC CUI (carry) */
	62	+ { 23, 1, 4, 3 }, /* SCI ERI */
	63	+ { 24, 1, 4, 3 }, /* SCI RXI */
	64	+ { 25, 1, 4, 3 }, /* SCI TXI */
	65	+ { 40, 2, 4, 3 }, /* SCIF ERI */
	66	+ { 41, 2, 4, 3 }, /* SCIF RXI */
	67	+ { 42, 2, 4, 3 }, /* SCIF BRI */
	68	+ { 43, 2, 4, 3 }, /* SCIF TXI */
	69	+ { 34, 2, 8, 7 }, /* DMAC DMTE0 */
	70	+ { 35, 2, 8, 7 }, /* DMAC DMTE1 */
	71	+ { 36, 2, 8, 7 }, /* DMAC DMTE2 */
	72	+ { 37, 2, 8, 7 }, /* DMAC DMTE3 */
	73	+ { 28, 2, 8, 7 }, /* DMAC DMAE */
	74	+};
	75	+
	76	+static struct ipr_data sh7751_ipr_map[] = {
	77	+ { 44, 2, 8, 7 }, /* DMAC DMTE4 */
	78	+ { 45, 2, 8, 7 }, /* DMAC DMTE5 */
	79	+ { 46, 2, 8, 7 }, /* DMAC DMTE6 */
	80	+ { 47, 2, 8, 7 }, /* DMAC DMTE7 */
	81	+ /* The following use INTC_INPRI00 for masking, which is a 32-bit
	82	+ register, not a 16-bit register like the IPRx registers, so it
	83	+ would need special support */
	84	+ /{ 72, INTPRI00, 8, ? },/ /* TMU3 TUNI */
	85	+ /{ 76, INTPRI00, 12, ? },/ /* TMU4 TUNI */
	86	+};
	87	+
	88	+static unsigned long ipr_offsets[] = {
	89	+ 0xffd00004UL, /* 0: IPRA */
	90	+ 0xffd00008UL, /* 1: IPRB */
	91	+ 0xffd0000cUL, /* 2: IPRC */
	92	+ 0xffd00010UL, /* 3: IPRD */
	93	+};
	94	+
	95	+/* given the IPR index return the address of the IPR register */
	96	+unsigned int map_ipridx_to_addr(int idx)
	97	+{
	98	+ if (idx >= ARRAY_SIZE(ipr_offsets))
	99	+ return 0;
	100	+ return ipr_offsets[idx];
	101	+}
	102	+
	103	+#define INTC_ICR 0xffd00000UL
	104	+#define INTC_ICR_IRLM (1<<7)
	105	+
	106	+/* enable individual interrupt mode for external interupts */
	107	+void ipr_irq_enable_irlm(void)
	108	+{
	109	+ ctrl_outw(ctrl_inw(INTC_ICR) \| INTC_ICR_IRLM, INTC_ICR);
	110	+}
	111	+
	112	+void __init init_IRQ_ipr()
	113	+{
	114	+ make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map));
	115	+#ifdef CONFIG_CPU_SUBTYPE_SH7751
	116	+ make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map));
	117	+#endif
	118	+}
...	...	@@ -12,7 +12,7 @@
12	12	#include <linux/kernel_stat.h>
13	13	#include <linux/seq_file.h>
14	14	#include <linux/io.h>
15		-#include <asm/irq.h>
	15	+#include <linux/irq.h>
16	16	#include <asm/processor.h>
17	17	#include <asm/uaccess.h>
18	18	#include <asm/thread_info.h>
...	...	@@ -112,7 +112,7 @@
112	112	#endif
113	113
114	114	#ifdef CONFIG_CPU_HAS_INTEVT
115		- irq = (ctrl_inl(INTEVT) >> 5) - 16;
	115	+ irq = evt2irq(ctrl_inl(INTEVT));
116	116	#else
117	117	irq = r4;
118	118	#endif
...	...	@@ -261,4 +261,25 @@
261	261	}
262	262	EXPORT_SYMBOL(do_softirq);
263	263	#endif
	264	+
	265	+void __init init_IRQ(void)
	266	+{
	267	+#ifdef CONFIG_CPU_HAS_PINT_IRQ
	268	+ init_IRQ_pint();
	269	+#endif
	270	+
	271	+#ifdef CONFIG_CPU_HAS_INTC2_IRQ
	272	+ init_IRQ_intc2();
	273	+#endif
	274	+
	275	+#ifdef CONFIG_CPU_HAS_IPR_IRQ
	276	+ init_IRQ_ipr();
	277	+#endif
	278	+
	279	+ /* Perform the machine specific initialisation */
	280	+ if (sh_mv.mv_init_irq)
	281	+ sh_mv.mv_init_irq();
	282	+
	283	+ irq_ctx_init(smp_processor_id());
	284	+}
...	...	@@ -104,6 +104,7 @@
104	104	config CPU_SUBTYPE_SH7750
105	105	bool "Support SH7750 processor"
106	106	select CPU_SH4
	107	+ select CPU_HAS_IPR_IRQ
107	108	help
108	109	Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
109	110
110	111
111	112
...	...	@@ -119,15 +120,18 @@
119	120	bool "Support SH7750R processor"
120	121	select CPU_SH4
121	122	select CPU_SUBTYPE_SH7750
	123	+ select CPU_HAS_IPR_IRQ
122	124
123	125	config CPU_SUBTYPE_SH7750S
124	126	bool "Support SH7750S processor"
125	127	select CPU_SH4
126	128	select CPU_SUBTYPE_SH7750
	129	+ select CPU_HAS_IPR_IRQ
127	130
128	131	config CPU_SUBTYPE_SH7751
129	132	bool "Support SH7751 processor"
130	133	select CPU_SH4
	134	+ select CPU_HAS_IPR_IRQ
131	135	help
132	136	Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
133	137	or if you have a HD6417751R CPU.
...	...	@@ -136,6 +140,7 @@
136	140	bool "Support SH7751R processor"
137	141	select CPU_SH4
138	142	select CPU_SUBTYPE_SH7751
	143	+ select CPU_HAS_IPR_IRQ
139	144
140	145	config CPU_SUBTYPE_SH7760
141	146	bool "Support SH7760 processor"
...	...	@@ -93,6 +93,12 @@
93	93	#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
94	94
95	95	/*
	96	+ * Convert back and forth between INTEVT and IRQ values.
	97	+ */
	98	+#define evt2irq(evt) (((evt) >> 5) - 16)
	99	+#define irq2evt(irq) (((irq) + 16) << 5)
	100	+
	101	+/*
96	102	* Simple Mask Register Support
97	103	*/
98	104	extern void make_maskreg_irq(unsigned int irq);
99	105
100	106
101	107
102	108
...	...	@@ -103,18 +109,36 @@
103	109	*/
104	110	void init_IRQ_pint(void);
105	111
	112	+/*
	113	+ * The shift value is now the number of bits to shift, not the number of
	114	+ * bits/4. This is to make it easier to read the value directly from the
	115	+ * datasheets. The IPR address, addr, will be set from ipr_idx via the
	116	+ * map_ipridx_to_addr function.
	117	+ */
106	118	struct ipr_data {
107	119	unsigned int irq;
108		- unsigned int addr; /* Address of Interrupt Priority Register */
109		- int shift; /* Shifts of the 16-bit data */
	120	+ int ipr_idx; /* Index for the IPR registered */
	121	+ int shift; /* Number of bits to shift the data */
110	122	int priority; /* The priority */
	123	+ unsigned int addr; /* Address of Interrupt Priority Register */
111	124	};
112	125
113	126	/*
	127	+ * Given an IPR IDX, map the value to an IPR register address.
	128	+ */
	129	+unsigned int map_ipridx_to_addr(int idx);
	130	+
	131	+/*
	132	+ * Enable individual interrupt mode for external IPR IRQs.
	133	+ */
	134	+void ipr_irq_enable_irlm(void);
	135	+
	136	+/*
114	137	* Function for "on chip support modules".
115	138	*/
116		-extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
117		-extern void make_imask_irq(unsigned int irq);
	139	+void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
	140	+void make_imask_irq(unsigned int irq);
	141	+void init_IRQ_ipr(void);
118	142
119	143	struct intc2_data {
120	144	unsigned short irq;
1	1	/*
2	2	* Platform defintions for Titan
3	3	*/
	4	+#ifndef _ASM_SH_TITAN_H
	5	+#define _ASM_SH_TITAN_H
4	6
5		-#ifndef _ASM_SH_TITAN_TITAN_H
6		-#define _ASM_SH_TITAN_TITAN_H
7		-
8	7	#define __IO_PREFIX titan
9	8	#include <asm/io_generic.h>
10	9
...	...	@@ -15,30 +14,5 @@
15	14	#define TITAN_IRQ_MPCIB 11 /* mPCI B */
16	15	#define TITAN_IRQ_USB 11 /* USB */
17	16
18		-/*
19		- * The external interrupt lines, these take up ints 0 - 15 inclusive
20		- * depending on the priority for the interrupt. In fact the priority
21		- * is the interrupt :-)
22		- */
23		-#define IRL0_IRQ 0
24		-#define IRL0_IPR_ADDR INTC_IPRD
25		-#define IRL0_IPR_POS 3
26		-#define IRL0_PRIORITY 8
27		-
28		-#define IRL1_IRQ 1
29		-#define IRL1_IPR_ADDR INTC_IPRD
30		-#define IRL1_IPR_POS 2
31		-#define IRL1_PRIORITY 8
32		-
33		-#define IRL2_IRQ 2
34		-#define IRL2_IPR_ADDR INTC_IPRD
35		-#define IRL2_IPR_POS 1
36		-#define IRL2_PRIORITY 8
37		-
38		-#define IRL3_IRQ 3
39		-#define IRL3_IPR_ADDR INTC_IPRD
40		-#define IRL3_IPR_POS 0
41		-#define IRL3_PRIORITY 8
42		-
43		-#endif
	17	+#endif /* __ASM_SH_TITAN_H */