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Commit ea5a3dcfda1c9140228f2842ea9b01e1713c559a

Authored by Robert P. J. Day
Committed by Linus Torvalds
1 parent ef48bd2461
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

COBALT: remove all references to Cobalt NVRAM 

Remove not only the references to Cobalt NVRAM, but the header file as
well.

Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Acked-by: Tim Hockin <thockin@hockin.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 2 changed files with 1 additions and 300 deletions Side-by-side Diff

drivers/char/nvram.c
Diff comments   View file @ ea5a3dc
... ... @@ -42,19 +42,12 @@
42 42  
43 43 #define PC 1
44 44 #define ATARI 2
45   -#define COBALT 3
46 45  
47 46 /* select machine configuration */
48 47 #if defined(CONFIG_ATARI)
49 48 # define MACH ATARI
50 49 #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) /* and others?? */
51   -#define MACH PC
52   -# if defined(CONFIG_COBALT)
53   -# include <linux/cobalt-nvram.h>
54   -# define MACH COBALT
55   -# else
56   -# define MACH PC
57   -# endif
  50 +# define MACH PC
58 51 #else
59 52 # error Cannot build nvram driver for this machine configuration.
60 53 #endif
... ... @@ -76,18 +69,6 @@
76 69  
77 70 #endif
78 71  
79   -#if MACH == COBALT
80   -
81   -#define CHECK_DRIVER_INIT() 1
82   -
83   -#define NVRAM_BYTES (128-NVRAM_FIRST_BYTE)
84   -
85   -#define mach_check_checksum cobalt_check_checksum
86   -#define mach_set_checksum cobalt_set_checksum
87   -#define mach_proc_infos cobalt_proc_infos
88   -
89   -#endif
90   -
91 72 #if MACH == ATARI
92 73  
93 74 /* Special parameters for RTC in Atari machines */
... ... @@ -603,177 +584,6 @@
603 584 #endif
604 585  
605 586 #endif /* MACH == PC */
606   -
607   -#if MACH == COBALT
608   -
609   -/* the cobalt CMOS has a wider range of its checksum */
610   -static int cobalt_check_checksum(void)
611   -{
612   - int i;
613   - unsigned short sum = 0;
614   - unsigned short expect;
615   -
616   - for (i = COBT_CMOS_CKS_START; i <= COBT_CMOS_CKS_END; ++i) {
617   - if ((i == COBT_CMOS_CHECKSUM) || (i == (COBT_CMOS_CHECKSUM+1)))
618   - continue;
619   -
620   - sum += __nvram_read_byte(i);
621   - }
622   - expect = __nvram_read_byte(COBT_CMOS_CHECKSUM) << 8 |
623   - __nvram_read_byte(COBT_CMOS_CHECKSUM+1);
624   - return ((sum & 0xffff) == expect);
625   -}
626   -
627   -static void cobalt_set_checksum(void)
628   -{
629   - int i;
630   - unsigned short sum = 0;
631   -
632   - for (i = COBT_CMOS_CKS_START; i <= COBT_CMOS_CKS_END; ++i) {
633   - if ((i == COBT_CMOS_CHECKSUM) || (i == (COBT_CMOS_CHECKSUM+1)))
634   - continue;
635   -
636   - sum += __nvram_read_byte(i);
637   - }
638   -
639   - __nvram_write_byte(sum >> 8, COBT_CMOS_CHECKSUM);
640   - __nvram_write_byte(sum & 0xff, COBT_CMOS_CHECKSUM+1);
641   -}
642   -
643   -#ifdef CONFIG_PROC_FS
644   -
645   -static int cobalt_proc_infos(unsigned char *nvram, char *buffer, int *len,
646   - off_t *begin, off_t offset, int size)
647   -{
648   - int i;
649   - unsigned int checksum;
650   - unsigned int flags;
651   - char sernum[14];
652   - char *key = "cNoEbTaWlOtR!";
653   - unsigned char bto_csum;
654   -
655   - spin_lock_irq(&rtc_lock);
656   - checksum = __nvram_check_checksum();
657   - spin_unlock_irq(&rtc_lock);
658   -
659   - PRINT_PROC("Checksum status: %svalid\n", checksum ? "" : "not ");
660   -
661   - flags = nvram[COBT_CMOS_FLAG_BYTE_0] << 8
662   - | nvram[COBT_CMOS_FLAG_BYTE_1];
663   -
664   - PRINT_PROC("Console: %s\n",
665   - flags & COBT_CMOS_CONSOLE_FLAG ? "on": "off");
666   -
667   - PRINT_PROC("Firmware Debug Messages: %s\n",
668   - flags & COBT_CMOS_DEBUG_FLAG ? "on": "off");
669   -
670   - PRINT_PROC("Auto Prompt: %s\n",
671   - flags & COBT_CMOS_AUTO_PROMPT_FLAG ? "on": "off");
672   -
673   - PRINT_PROC("Shutdown Status: %s\n",
674   - flags & COBT_CMOS_CLEAN_BOOT_FLAG ? "clean": "dirty");
675   -
676   - PRINT_PROC("Hardware Probe: %s\n",
677   - flags & COBT_CMOS_HW_NOPROBE_FLAG ? "partial": "full");
678   -
679   - PRINT_PROC("System Fault: %sdetected\n",
680   - flags & COBT_CMOS_SYSFAULT_FLAG ? "": "not ");
681   -
682   - PRINT_PROC("Panic on OOPS: %s\n",
683   - flags & COBT_CMOS_OOPSPANIC_FLAG ? "yes": "no");
684   -
685   - PRINT_PROC("Delayed Cache Initialization: %s\n",
686   - flags & COBT_CMOS_DELAY_CACHE_FLAG ? "yes": "no");
687   -
688   - PRINT_PROC("Show Logo at Boot: %s\n",
689   - flags & COBT_CMOS_NOLOGO_FLAG ? "no": "yes");
690   -
691   - PRINT_PROC("Boot Method: ");
692   - switch (nvram[COBT_CMOS_BOOT_METHOD]) {
693   - case COBT_CMOS_BOOT_METHOD_DISK:
694   - PRINT_PROC("disk\n");
695   - break;
696   -
697   - case COBT_CMOS_BOOT_METHOD_ROM:
698   - PRINT_PROC("rom\n");
699   - break;
700   -
701   - case COBT_CMOS_BOOT_METHOD_NET:
702   - PRINT_PROC("net\n");
703   - break;
704   -
705   - default:
706   - PRINT_PROC("unknown\n");
707   - break;
708   - }
709   -
710   - PRINT_PROC("Primary Boot Device: %d:%d\n",
711   - nvram[COBT_CMOS_BOOT_DEV0_MAJ],
712   - nvram[COBT_CMOS_BOOT_DEV0_MIN] );
713   - PRINT_PROC("Secondary Boot Device: %d:%d\n",
714   - nvram[COBT_CMOS_BOOT_DEV1_MAJ],
715   - nvram[COBT_CMOS_BOOT_DEV1_MIN] );
716   - PRINT_PROC("Tertiary Boot Device: %d:%d\n",
717   - nvram[COBT_CMOS_BOOT_DEV2_MAJ],
718   - nvram[COBT_CMOS_BOOT_DEV2_MIN] );
719   -
720   - PRINT_PROC("Uptime: %d\n",
721   - nvram[COBT_CMOS_UPTIME_0] << 24 |
722   - nvram[COBT_CMOS_UPTIME_1] << 16 |
723   - nvram[COBT_CMOS_UPTIME_2] << 8 |
724   - nvram[COBT_CMOS_UPTIME_3]);
725   -
726   - PRINT_PROC("Boot Count: %d\n",
727   - nvram[COBT_CMOS_BOOTCOUNT_0] << 24 |
728   - nvram[COBT_CMOS_BOOTCOUNT_1] << 16 |
729   - nvram[COBT_CMOS_BOOTCOUNT_2] << 8 |
730   - nvram[COBT_CMOS_BOOTCOUNT_3]);
731   -
732   - /* 13 bytes of serial num */
733   - for (i=0 ; i<13 ; i++) {
734   - sernum[i] = nvram[COBT_CMOS_SYS_SERNUM_0 + i];
735   - }
736   - sernum[13] = '\0';
737   -
738   - checksum = 0;
739   - for (i=0 ; i<13 ; i++) {
740   - checksum += sernum[i] ^ key[i];
741   - }
742   - checksum = ((checksum & 0x7f) ^ (0xd6)) & 0xff;
743   -
744   - PRINT_PROC("Serial Number: %s", sernum);
745   - if (checksum != nvram[COBT_CMOS_SYS_SERNUM_CSUM]) {
746   - PRINT_PROC(" (invalid checksum)");
747   - }
748   - PRINT_PROC("\n");
749   -
750   - PRINT_PROC("Rom Revison: %d.%d.%d\n", nvram[COBT_CMOS_ROM_REV_MAJ],
751   - nvram[COBT_CMOS_ROM_REV_MIN], nvram[COBT_CMOS_ROM_REV_REV]);
752   -
753   - PRINT_PROC("BTO Server: %d.%d.%d.%d", nvram[COBT_CMOS_BTO_IP_0],
754   - nvram[COBT_CMOS_BTO_IP_1], nvram[COBT_CMOS_BTO_IP_2],
755   - nvram[COBT_CMOS_BTO_IP_3]);
756   - bto_csum = nvram[COBT_CMOS_BTO_IP_0] + nvram[COBT_CMOS_BTO_IP_1]
757   - + nvram[COBT_CMOS_BTO_IP_2] + nvram[COBT_CMOS_BTO_IP_3];
758   - if (bto_csum != nvram[COBT_CMOS_BTO_IP_CSUM]) {
759   - PRINT_PROC(" (invalid checksum)");
760   - }
761   - PRINT_PROC("\n");
762   -
763   - if (flags & COBT_CMOS_VERSION_FLAG
764   - && nvram[COBT_CMOS_VERSION] >= COBT_CMOS_VER_BTOCODE) {
765   - PRINT_PROC("BTO Code: 0x%x\n",
766   - nvram[COBT_CMOS_BTO_CODE_0] << 24 |
767   - nvram[COBT_CMOS_BTO_CODE_1] << 16 |
768   - nvram[COBT_CMOS_BTO_CODE_2] << 8 |
769   - nvram[COBT_CMOS_BTO_CODE_3]);
770   - }
771   -
772   - return 1;
773   -}
774   -#endif /* CONFIG_PROC_FS */
775   -
776   -#endif /* MACH == COBALT */
777 587  
778 588 #if MACH == ATARI
779 589  
include/linux/cobalt-nvram.h
View file @ ea5a3dc
1   -/*
2   - * $Id: cobalt-nvram.h,v 1.20 2001/10/17 23:16:55 thockin Exp $
3   - * cobalt-nvram.h : defines for the various fields in the cobalt NVRAM
4   - *
5   - * Copyright 2001,2002 Sun Microsystems, Inc.
6   - */
7   -
8   -#ifndef COBALT_NVRAM_H
9   -#define COBALT_NVRAM_H
10   -
11   -#include <linux/nvram.h>
12   -
13   -#define COBT_CMOS_INFO_MAX 0x7f /* top address allowed */
14   -#define COBT_CMOS_BIOS_DRIVE_INFO 0x12 /* drive info would go here */
15   -
16   -#define COBT_CMOS_CKS_START NVRAM_OFFSET(0x0e)
17   -#define COBT_CMOS_CKS_END NVRAM_OFFSET(0x7f)
18   -
19   -/* flag bytes - 16 flags for now, leave room for more */
20   -#define COBT_CMOS_FLAG_BYTE_0 NVRAM_OFFSET(0x10)
21   -#define COBT_CMOS_FLAG_BYTE_1 NVRAM_OFFSET(0x11)
22   -
23   -/* flags in flag bytes - up to 16 */
24   -#define COBT_CMOS_FLAG_MIN 0x0001
25   -#define COBT_CMOS_CONSOLE_FLAG 0x0001 /* console on/off */
26   -#define COBT_CMOS_DEBUG_FLAG 0x0002 /* ROM debug messages */
27   -#define COBT_CMOS_AUTO_PROMPT_FLAG 0x0004 /* boot to ROM prompt? */
28   -#define COBT_CMOS_CLEAN_BOOT_FLAG 0x0008 /* set by a clean shutdown */
29   -#define COBT_CMOS_HW_NOPROBE_FLAG 0x0010 /* go easy on the probing */
30   -#define COBT_CMOS_SYSFAULT_FLAG 0x0020 /* system fault detected */
31   -#define COBT_CMOS_OOPSPANIC_FLAG 0x0040 /* panic on oops */
32   -#define COBT_CMOS_DELAY_CACHE_FLAG 0x0080 /* delay cache initialization */
33   -#define COBT_CMOS_NOLOGO_FLAG 0x0100 /* hide "C" logo @ boot */
34   -#define COBT_CMOS_VERSION_FLAG 0x0200 /* the version field is valid */
35   -#define COBT_CMOS_FLAG_MAX 0x0200
36   -
37   -/* leave byte 0x12 blank - Linux looks for drive info here */
38   -
39   -/* CMOS structure version, valid if COBT_CMOS_VERSION_FLAG is true */
40   -#define COBT_CMOS_VERSION NVRAM_OFFSET(0x13)
41   -#define COBT_CMOS_VER_BTOCODE 1 /* min. version needed for btocode */
42   -
43   -/* index of default boot method */
44   -#define COBT_CMOS_BOOT_METHOD NVRAM_OFFSET(0x20)
45   -#define COBT_CMOS_BOOT_METHOD_DISK 0
46   -#define COBT_CMOS_BOOT_METHOD_ROM 1
47   -#define COBT_CMOS_BOOT_METHOD_NET 2
48   -
49   -#define COBT_CMOS_BOOT_DEV_MIN NVRAM_OFFSET(0x21)
50   -/* major #, minor # of first through fourth boot device */
51   -#define COBT_CMOS_BOOT_DEV0_MAJ NVRAM_OFFSET(0x21)
52   -#define COBT_CMOS_BOOT_DEV0_MIN NVRAM_OFFSET(0x22)
53   -#define COBT_CMOS_BOOT_DEV1_MAJ NVRAM_OFFSET(0x23)
54   -#define COBT_CMOS_BOOT_DEV1_MIN NVRAM_OFFSET(0x24)
55   -#define COBT_CMOS_BOOT_DEV2_MAJ NVRAM_OFFSET(0x25)
56   -#define COBT_CMOS_BOOT_DEV2_MIN NVRAM_OFFSET(0x26)
57   -#define COBT_CMOS_BOOT_DEV3_MAJ NVRAM_OFFSET(0x27)
58   -#define COBT_CMOS_BOOT_DEV3_MIN NVRAM_OFFSET(0x28)
59   -#define COBT_CMOS_BOOT_DEV_MAX NVRAM_OFFSET(0x28)
60   -
61   -/* checksum of bytes 0xe-0x7f */
62   -#define COBT_CMOS_CHECKSUM NVRAM_OFFSET(0x2e)
63   -
64   -/* running uptime counter, units of 5 minutes (32 bits =~ 41000 years) */
65   -#define COBT_CMOS_UPTIME_0 NVRAM_OFFSET(0x30)
66   -#define COBT_CMOS_UPTIME_1 NVRAM_OFFSET(0x31)
67   -#define COBT_CMOS_UPTIME_2 NVRAM_OFFSET(0x32)
68   -#define COBT_CMOS_UPTIME_3 NVRAM_OFFSET(0x33)
69   -
70   -/* count of successful boots (32 bits) */
71   -#define COBT_CMOS_BOOTCOUNT_0 NVRAM_OFFSET(0x38)
72   -#define COBT_CMOS_BOOTCOUNT_1 NVRAM_OFFSET(0x39)
73   -#define COBT_CMOS_BOOTCOUNT_2 NVRAM_OFFSET(0x3a)
74   -#define COBT_CMOS_BOOTCOUNT_3 NVRAM_OFFSET(0x3b)
75   -
76   -/* 13 bytes: system serial number, same as on the back of the system */
77   -#define COBT_CMOS_SYS_SERNUM_LEN 13
78   -#define COBT_CMOS_SYS_SERNUM_0 NVRAM_OFFSET(0x40)
79   -#define COBT_CMOS_SYS_SERNUM_1 NVRAM_OFFSET(0x41)
80   -#define COBT_CMOS_SYS_SERNUM_2 NVRAM_OFFSET(0x42)
81   -#define COBT_CMOS_SYS_SERNUM_3 NVRAM_OFFSET(0x43)
82   -#define COBT_CMOS_SYS_SERNUM_4 NVRAM_OFFSET(0x44)
83   -#define COBT_CMOS_SYS_SERNUM_5 NVRAM_OFFSET(0x45)
84   -#define COBT_CMOS_SYS_SERNUM_6 NVRAM_OFFSET(0x46)
85   -#define COBT_CMOS_SYS_SERNUM_7 NVRAM_OFFSET(0x47)
86   -#define COBT_CMOS_SYS_SERNUM_8 NVRAM_OFFSET(0x48)
87   -#define COBT_CMOS_SYS_SERNUM_9 NVRAM_OFFSET(0x49)
88   -#define COBT_CMOS_SYS_SERNUM_10 NVRAM_OFFSET(0x4a)
89   -#define COBT_CMOS_SYS_SERNUM_11 NVRAM_OFFSET(0x4b)
90   -#define COBT_CMOS_SYS_SERNUM_12 NVRAM_OFFSET(0x4c)
91   -/* checksum for serial num - 1 byte */
92   -#define COBT_CMOS_SYS_SERNUM_CSUM NVRAM_OFFSET(0x4f)
93   -
94   -#define COBT_CMOS_ROM_REV_MAJ NVRAM_OFFSET(0x50)
95   -#define COBT_CMOS_ROM_REV_MIN NVRAM_OFFSET(0x51)
96   -#define COBT_CMOS_ROM_REV_REV NVRAM_OFFSET(0x52)
97   -
98   -#define COBT_CMOS_BTO_CODE_0 NVRAM_OFFSET(0x53)
99   -#define COBT_CMOS_BTO_CODE_1 NVRAM_OFFSET(0x54)
100   -#define COBT_CMOS_BTO_CODE_2 NVRAM_OFFSET(0x55)
101   -#define COBT_CMOS_BTO_CODE_3 NVRAM_OFFSET(0x56)
102   -
103   -#define COBT_CMOS_BTO_IP_CSUM NVRAM_OFFSET(0x57)
104   -#define COBT_CMOS_BTO_IP_0 NVRAM_OFFSET(0x58)
105   -#define COBT_CMOS_BTO_IP_1 NVRAM_OFFSET(0x59)
106   -#define COBT_CMOS_BTO_IP_2 NVRAM_OFFSET(0x5a)
107   -#define COBT_CMOS_BTO_IP_3 NVRAM_OFFSET(0x5b)
108   -
109   -#endif /* COBALT_NVRAM_H */