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Commit eaaf9c68e75edf0fa51c5770eb68c2a6cb5ff66b

Authored by Daniel Ritz
Committed by Linus Torvalds
1 parent d8c4b4195c
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[PATCH] pcmcia: disable read prefetch/write burst on old O2Micro bridges 

Older O2Micro bridges have problems with both read prefetch and write burst
depending on the combination of the chipset, bridge, cardbus card.  safest is
to disable read prefetch and write burst on those old bridges.

Signed-off-by: Daniel Ritz <daniel.ritz@gmx.ch>
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 1 changed file with 27 additions and 7 deletions Side-by-side Diff

drivers/pcmcia/o2micro.h
Diff comments   View file @ eaaf9c6
... ... @@ -120,11 +120,16 @@
120 120 #define O2_MODE_E_LED_OUT 0x08
121 121 #define O2_MODE_E_SKTA_ACTV 0x10
122 122  
  123 +#define O2_RESERVED1 0x94
  124 +#define O2_RESERVED2 0xD4
  125 +#define O2_RES_READ_PREFETCH 0x02
  126 +#define O2_RES_WRITE_BURST 0x08
  127 +
123 128 static int o2micro_override(struct yenta_socket *socket)
124 129 {
125 130 /*
126   - * 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
127   - * read prefetching which for example makes the RME Hammerfall DSP
  131 + * 'reserved' register at 0x94/D4. allows setting read prefetch and write
  132 + * bursting. read prefetching for example makes the RME Hammerfall DSP
128 133 * working. for some bridges it is at 0x94, for others at 0xD4. it's
129 134 * ok to write to both registers on all O2 bridges.
130 135 * from Eric Still, 02Micro.
131 136  
132 137  
133 138  
... ... @@ -132,20 +137,35 @@
132 137 u8 a, b;
133 138  
134 139 if (PCI_FUNC(socket->dev->devfn) == 0) {
135   - a = config_readb(socket, 0x94);
136   - b = config_readb(socket, 0xD4);
  140 + a = config_readb(socket, O2_RESERVED1);
  141 + b = config_readb(socket, O2_RESERVED2);
137 142  
138 143 printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a, b);
139 144  
140 145 switch (socket->dev->device) {
  146 + /*
  147 + * older bridges have problems with both read prefetch and write
  148 + * bursting depending on the combination of the chipset, bridge
  149 + * and the cardbus card. so disable them to be on the safe side.
  150 + */
  151 + case PCI_DEVICE_ID_O2_6729:
  152 + case PCI_DEVICE_ID_O2_6730:
  153 + case PCI_DEVICE_ID_O2_6812:
141 154 case PCI_DEVICE_ID_O2_6832:
142   - printk(KERN_INFO "Yenta O2: old bridge, not enabling read prefetch / write burst\n");
  155 + case PCI_DEVICE_ID_O2_6836:
  156 + printk(KERN_INFO "Yenta O2: old bridge, disabling read prefetch/write burst\n");
  157 + config_writeb(socket, O2_RESERVED1,
  158 + a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
  159 + config_writeb(socket, O2_RESERVED2,
  160 + b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
143 161 break;
144 162  
145 163 default:
146 164 printk(KERN_INFO "Yenta O2: enabling read prefetch/write burst\n");
147   - config_writeb(socket, 0x94, a | 0x0a);
148   - config_writeb(socket, 0xD4, b | 0x0a);
  165 + config_writeb(socket, O2_RESERVED1,
  166 + a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
  167 + config_writeb(socket, O2_RESERVED2,
  168 + b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
149 169 }
150 170 }
151 171