Commit ec6754a7b9e90a1eba7f3b2812003bb51d3dcf30

Authored by Jean-Christophe PLAGNIOL-VILLARD
1 parent 5314ec8e52

arm: at91: dt: at91sam9 add serial pinctrl support

Set the dbgu pinctrl config by default as we have only one possible config
For other uart set the rxd/txd by default.

For at91sam9x5ek create soc based dts as we need to include specific soc dtsi.

Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Showing 17 changed files with 703 additions and 72 deletions Side-by-side Diff

arch/arm/boot/dts/Makefile
1 1 ifeq ($(CONFIG_OF),y)
2 2  
3   -dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
4   - at91sam9263ek.dtb \
5   - at91sam9g20ek_2mmc.dtb \
6   - at91sam9g20ek.dtb \
7   - at91sam9g25ek.dtb \
8   - at91sam9m10g45ek.dtb \
9   - at91sam9n12ek.dtb \
10   - ethernut5.dtb \
11   - evk-pro3.dtb \
12   - kizbox.dtb \
13   - tny_a9260.dtb \
14   - tny_a9263.dtb \
15   - tny_a9g20.dtb \
16   - usb_a9260.dtb \
17   - usb_a9263.dtb \
18   - usb_a9g20.dtb
  3 +# Keep at91 dtb files sorted alphabetically for each SoC
  4 +# sam9260
  5 +dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
  6 +dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
  7 +dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
  8 +dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
  9 +dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
  10 +# sam9263
  11 +dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
  12 +dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
  13 +dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
  14 +# sam9g20
  15 +dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
  16 +dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
  17 +dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
  18 +dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
  19 +dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
  20 +# sam9g45
  21 +dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
  22 +# sam9n12
  23 +dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
  24 +# sam9x5
  25 +dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
  26 +dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
  27 +dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
  28 +dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
  29 +dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
  30 +
19 31 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
20 32 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
21 33 dove-cubox.dtb \
arch/arm/boot/dts/at91sam9260.dtsi
... ... @@ -112,7 +112,102 @@
112 112 >;
113 113  
114 114 /* shared pinctrl settings */
  115 + dbgu {
  116 + pinctrl_dbgu: dbgu-0 {
  117 + atmel,pins =
  118 + <1 14 0x1 0x0 /* PB14 periph A */
  119 + 1 15 0x1 0x1>; /* PB15 periph with pullup */
  120 + };
  121 + };
115 122  
  123 + uart0 {
  124 + pinctrl_uart0: uart0-0 {
  125 + atmel,pins =
  126 + <1 4 0x1 0x0 /* PB4 periph A */
  127 + 1 5 0x1 0x0>; /* PB5 periph A */
  128 + };
  129 +
  130 + pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  131 + atmel,pins =
  132 + <1 26 0x1 0x0 /* PB26 periph A */
  133 + 1 27 0x1 0x0>; /* PB27 periph A */
  134 + };
  135 +
  136 + pinctrl_uart0_dtr_dsr: uart0_dtr_dsr-0 {
  137 + atmel,pins =
  138 + <1 24 0x1 0x0 /* PB24 periph A */
  139 + 1 22 0x1 0x0>; /* PB22 periph A */
  140 + };
  141 +
  142 + pinctrl_uart0_dcd: uart0_dcd-0 {
  143 + atmel,pins =
  144 + <1 23 0x1 0x0>; /* PB23 periph A */
  145 + };
  146 +
  147 + pinctrl_uart0_ri: uart0_ri-0 {
  148 + atmel,pins =
  149 + <1 25 0x1 0x0>; /* PB25 periph A */
  150 + };
  151 + };
  152 +
  153 + uart1 {
  154 + pinctrl_uart1: uart1-0 {
  155 + atmel,pins =
  156 + <2 6 0x1 0x1 /* PB6 periph A with pullup */
  157 + 2 7 0x1 0x0>; /* PB7 periph A */
  158 + };
  159 +
  160 + pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  161 + atmel,pins =
  162 + <1 28 0x1 0x0 /* PB28 periph A */
  163 + 1 29 0x1 0x0>; /* PB29 periph A */
  164 + };
  165 + };
  166 +
  167 + uart2 {
  168 + pinctrl_uart2: uart2-0 {
  169 + atmel,pins =
  170 + <1 8 0x1 0x1 /* PB8 periph A with pullup */
  171 + 1 9 0x1 0x0>; /* PB9 periph A */
  172 + };
  173 +
  174 + pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  175 + atmel,pins =
  176 + <0 4 0x1 0x0 /* PA4 periph A */
  177 + 0 5 0x1 0x0>; /* PA5 periph A */
  178 + };
  179 + };
  180 +
  181 + uart3 {
  182 + pinctrl_uart3: uart3-0 {
  183 + atmel,pins =
  184 + <2 10 0x1 0x1 /* PB10 periph A with pullup */
  185 + 2 11 0x1 0x0>; /* PB11 periph A */
  186 + };
  187 +
  188 + pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  189 + atmel,pins =
  190 + <3 8 0x2 0x0 /* PB8 periph B */
  191 + 3 10 0x2 0x0>; /* PB10 periph B */
  192 + };
  193 + };
  194 +
  195 + uart4 {
  196 + pinctrl_uart4: uart4-0 {
  197 + atmel,pins =
  198 + <0 31 0x2 0x1 /* PA31 periph B with pullup */
  199 + 0 30 0x2 0x0>; /* PA30 periph B */
  200 + };
  201 + };
  202 +
  203 + uart5 {
  204 + pinctrl_uart5: uart5-0 {
  205 + atmel,pins =
  206 + <2 12 0x1 0x1 /* PB12 periph A with pullup */
  207 + 2 13 0x1 0x0>; /* PB13 periph A */
  208 + };
  209 + };
  210 +
116 211 pioA: gpio@fffff400 {
117 212 compatible = "atmel,at91rm9200-gpio";
118 213 reg = <0xfffff400 0x200>;
... ... @@ -148,6 +243,8 @@
148 243 compatible = "atmel,at91sam9260-usart";
149 244 reg = <0xfffff200 0x200>;
150 245 interrupts = <1 4 7>;
  246 + pinctrl-names = "default";
  247 + pinctrl-0 = <&pinctrl_dbgu>;
151 248 status = "disabled";
152 249 };
153 250  
... ... @@ -157,6 +254,8 @@
157 254 interrupts = <6 4 5>;
158 255 atmel,use-dma-rx;
159 256 atmel,use-dma-tx;
  257 + pinctrl-names = "default";
  258 + pinctrl-0 = <&pinctrl_uart0>;
160 259 status = "disabled";
161 260 };
162 261  
... ... @@ -166,6 +265,8 @@
166 265 interrupts = <7 4 5>;
167 266 atmel,use-dma-rx;
168 267 atmel,use-dma-tx;
  268 + pinctrl-names = "default";
  269 + pinctrl-0 = <&pinctrl_uart1>;
169 270 status = "disabled";
170 271 };
171 272  
... ... @@ -175,6 +276,8 @@
175 276 interrupts = <8 4 5>;
176 277 atmel,use-dma-rx;
177 278 atmel,use-dma-tx;
  279 + pinctrl-names = "default";
  280 + pinctrl-0 = <&pinctrl_uart2>;
178 281 status = "disabled";
179 282 };
180 283  
... ... @@ -184,6 +287,8 @@
184 287 interrupts = <23 4 5>;
185 288 atmel,use-dma-rx;
186 289 atmel,use-dma-tx;
  290 + pinctrl-names = "default";
  291 + pinctrl-0 = <&pinctrl_uart3>;
187 292 status = "disabled";
188 293 };
189 294  
... ... @@ -193,6 +298,8 @@
193 298 interrupts = <24 4 5>;
194 299 atmel,use-dma-rx;
195 300 atmel,use-dma-tx;
  301 + pinctrl-names = "default";
  302 + pinctrl-0 = <&pinctrl_uart4>;
196 303 status = "disabled";
197 304 };
198 305  
... ... @@ -202,6 +309,8 @@
202 309 interrupts = <25 4 5>;
203 310 atmel,use-dma-rx;
204 311 atmel,use-dma-tx;
  312 + pinctrl-names = "default";
  313 + pinctrl-0 = <&pinctrl_uart5>;
205 314 status = "disabled";
206 315 };
207 316  
arch/arm/boot/dts/at91sam9263.dtsi
... ... @@ -105,7 +105,56 @@
105 105 >;
106 106  
107 107 /* shared pinctrl settings */
  108 + dbgu {
  109 + pinctrl_dbgu: dbgu-0 {
  110 + atmel,pins =
  111 + <2 30 0x1 0x0 /* PC30 periph A */
  112 + 2 31 0x1 0x1>; /* PC31 periph with pullup */
  113 + };
  114 + };
108 115  
  116 + uart0 {
  117 + pinctrl_uart0: uart0-0 {
  118 + atmel,pins =
  119 + <0 26 0x1 0x1 /* PA26 periph A with pullup */
  120 + 0 27 0x1 0x0>; /* PA27 periph A */
  121 + };
  122 +
  123 + pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  124 + atmel,pins =
  125 + <0 28 0x1 0x0 /* PA28 periph A */
  126 + 0 29 0x1 0x0>; /* PA29 periph A */
  127 + };
  128 + };
  129 +
  130 + uart1 {
  131 + pinctrl_uart1: uart1-0 {
  132 + atmel,pins =
  133 + <3 0 0x1 0x1 /* PD0 periph A with pullup */
  134 + 3 1 0x1 0x0>; /* PD1 periph A */
  135 + };
  136 +
  137 + pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  138 + atmel,pins =
  139 + <3 7 0x2 0x0 /* PD7 periph B */
  140 + 3 8 0x2 0x0>; /* PD8 periph B */
  141 + };
  142 + };
  143 +
  144 + uart2 {
  145 + pinctrl_uart2: uart2-0 {
  146 + atmel,pins =
  147 + <3 2 0x1 0x1 /* PD2 periph A with pullup */
  148 + 3 3 0x1 0x0>; /* PD3 periph A */
  149 + };
  150 +
  151 + pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  152 + atmel,pins =
  153 + <3 5 0x2 0x0 /* PD5 periph B */
  154 + 4 6 0x2 0x0>; /* PD6 periph B */
  155 + };
  156 + };
  157 +
109 158 pioA: gpio@fffff200 {
110 159 compatible = "atmel,at91rm9200-gpio";
111 160 reg = <0xfffff200 0x200>;
... ... @@ -161,6 +210,8 @@
161 210 compatible = "atmel,at91sam9260-usart";
162 211 reg = <0xffffee00 0x200>;
163 212 interrupts = <1 4 7>;
  213 + pinctrl-names = "default";
  214 + pinctrl-0 = <&pinctrl_dbgu>;
164 215 status = "disabled";
165 216 };
166 217  
... ... @@ -170,6 +221,8 @@
170 221 interrupts = <7 4 5>;
171 222 atmel,use-dma-rx;
172 223 atmel,use-dma-tx;
  224 + pinctrl-names = "default";
  225 + pinctrl-0 = <&pinctrl_uart0>;
173 226 status = "disabled";
174 227 };
175 228  
... ... @@ -179,6 +232,8 @@
179 232 interrupts = <8 4 5>;
180 233 atmel,use-dma-rx;
181 234 atmel,use-dma-tx;
  235 + pinctrl-names = "default";
  236 + pinctrl-0 = <&pinctrl_uart1>;
182 237 status = "disabled";
183 238 };
184 239  
... ... @@ -188,6 +243,8 @@
188 243 interrupts = <9 4 5>;
189 244 atmel,use-dma-rx;
190 245 atmel,use-dma-tx;
  246 + pinctrl-names = "default";
  247 + pinctrl-0 = <&pinctrl_uart2>;
191 248 status = "disabled";
192 249 };
193 250  
arch/arm/boot/dts/at91sam9g15.dtsi
  1 +/*
  2 + * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
  3 + *
  4 + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5 + *
  6 + * Licensed under GPLv2.
  7 + */
  8 +
  9 +/include/ "at91sam9x5.dtsi"
  10 +
  11 +/ {
  12 + model = "Atmel AT91SAM9G15 SoC";
  13 + compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
  14 +
  15 + ahb {
  16 + apb {
  17 + pinctrl@fffff400 {
  18 + atmel,mux-mask = <
  19 + /* A B C */
  20 + 0xffffffff 0xffe0399f 0x00000000 /* pioA */
  21 + 0x00040000 0x00047e3f 0x00000000 /* pioB */
  22 + 0xfdffffff 0x00000000 0xb83fffff /* pioC */
  23 + 0x003fffff 0x003f8000 0x00000000 /* pioD */
  24 + >;
  25 + };
  26 + };
  27 + };
  28 +};
arch/arm/boot/dts/at91sam9g15ek.dts
  1 +/*
  2 + * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
  3 + *
  4 + * Copyright (C) 2012 Atmel,
  5 + * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  6 + *
  7 + * Licensed under GPLv2 or later.
  8 + */
  9 +/dts-v1/;
  10 +/include/ "at91sam9g15.dtsi"
  11 +/include/ "at91sam9x5ek.dtsi"
  12 +
  13 +/ {
  14 + model = "Atmel AT91SAM9G25-EK";
  15 + compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
  16 +};
arch/arm/boot/dts/at91sam9g25.dtsi
  1 +/*
  2 + * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
  3 + *
  4 + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5 + *
  6 + * Licensed under GPLv2.
  7 + */
  8 +
  9 +/include/ "at91sam9x5.dtsi"
  10 +
  11 +/ {
  12 + model = "Atmel AT91SAM9G25 SoC";
  13 + compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
  14 +
  15 + ahb {
  16 + apb {
  17 + pinctrl@fffff400 {
  18 + atmel,mux-mask = <
  19 + /* A B C */
  20 + 0xffffffff 0xffe0399f 0xc000001c /* pioA */
  21 + 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
  22 + 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
  23 + 0x003fffff 0x003f8000 0x00000000 /* pioD */
  24 + >;
  25 + };
  26 + };
  27 + };
  28 +};
arch/arm/boot/dts/at91sam9g25ek.dts
... ... @@ -7,56 +7,11 @@
7 7 * Licensed under GPLv2 or later.
8 8 */
9 9 /dts-v1/;
10   -/include/ "at91sam9x5.dtsi"
11   -/include/ "at91sam9x5cm.dtsi"
  10 +/include/ "at91sam9g25.dtsi"
  11 +/include/ "at91sam9x5ek.dtsi"
12 12  
13 13 / {
14 14 model = "Atmel AT91SAM9G25-EK";
15 15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16   -
17   - chosen {
18   - bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
19   - };
20   -
21   - ahb {
22   - apb {
23   - dbgu: serial@fffff200 {
24   - status = "okay";
25   - };
26   -
27   - usart0: serial@f801c000 {
28   - status = "okay";
29   - };
30   -
31   - macb0: ethernet@f802c000 {
32   - phy-mode = "rmii";
33   - status = "okay";
34   - };
35   -
36   - i2c0: i2c@f8010000 {
37   - status = "okay";
38   - };
39   -
40   - i2c1: i2c@f8014000 {
41   - status = "okay";
42   - };
43   -
44   - i2c2: i2c@f8018000 {
45   - status = "okay";
46   - };
47   - };
48   -
49   - usb0: ohci@00600000 {
50   - status = "okay";
51   - num-ports = <2>;
52   - atmel,vbus-gpio = <&pioD 19 1
53   - &pioD 20 1
54   - >;
55   - };
56   -
57   - usb1: ehci@00700000 {
58   - status = "okay";
59   - };
60   - };
61 16 };
arch/arm/boot/dts/at91sam9g35.dtsi
  1 +/*
  2 + * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
  3 + *
  4 + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5 + *
  6 + * Licensed under GPLv2.
  7 + */
  8 +
  9 +/include/ "at91sam9x5.dtsi"
  10 +
  11 +/ {
  12 + model = "Atmel AT91SAM9G35 SoC";
  13 + compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
  14 +
  15 + ahb {
  16 + apb {
  17 + pinctrl@fffff400 {
  18 + atmel,mux-mask = <
  19 + /* A B C */
  20 + 0xffffffff 0xffe0399f 0xc000000c /* pioA */
  21 + 0x000406ff 0x00047e3f 0x00000000 /* pioB */
  22 + 0xfdffffff 0x00000000 0xb83fffff /* pioC */
  23 + 0x003fffff 0x003f8000 0x00000000 /* pioD */
  24 + >;
  25 + };
  26 + };
  27 + };
  28 +};
arch/arm/boot/dts/at91sam9g35ek.dts
  1 +/*
  2 + * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
  3 + *
  4 + * Copyright (C) 2012 Atmel,
  5 + * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  6 + *
  7 + * Licensed under GPLv2 or later.
  8 + */
  9 +/dts-v1/;
  10 +/include/ "at91sam9g35.dtsi"
  11 +/include/ "at91sam9x5ek.dtsi"
  12 +
  13 +/ {
  14 + model = "Atmel AT91SAM9G35-EK";
  15 + compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
  16 +};
arch/arm/boot/dts/at91sam9g45.dtsi
... ... @@ -124,7 +124,70 @@
124 124 >;
125 125  
126 126 /* shared pinctrl settings */
  127 + dbgu {
  128 + pinctrl_dbgu: dbgu-0 {
  129 + atmel,pins =
  130 + <1 12 0x1 0x0 /* PB12 periph A */
  131 + 1 13 0x1 0x0>; /* PB13 periph A */
  132 + };
  133 + };
127 134  
  135 + uart0 {
  136 + pinctrl_uart0: uart0-0 {
  137 + atmel,pins =
  138 + <1 19 0x1 0x1 /* PB19 periph A with pullup */
  139 + 1 18 0x1 0x0>; /* PB18 periph A */
  140 + };
  141 +
  142 + pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  143 + atmel,pins =
  144 + <1 17 0x2 0x0 /* PB17 periph B */
  145 + 1 15 0x2 0x0>; /* PB15 periph B */
  146 + };
  147 + };
  148 +
  149 + uart1 {
  150 + pinctrl_uart1: uart1-0 {
  151 + atmel,pins =
  152 + <1 4 0x1 0x1 /* PB4 periph A with pullup */
  153 + 1 5 0x1 0x0>; /* PB5 periph A */
  154 + };
  155 +
  156 + pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  157 + atmel,pins =
  158 + <3 16 0x1 0x0 /* PD16 periph A */
  159 + 3 17 0x1 0x0>; /* PD17 periph A */
  160 + };
  161 + };
  162 +
  163 + uart2 {
  164 + pinctrl_uart2: uart2-0 {
  165 + atmel,pins =
  166 + <1 6 0x1 0x1 /* PB6 periph A with pullup */
  167 + 1 7 0x1 0x0>; /* PB7 periph A */
  168 + };
  169 +
  170 + pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  171 + atmel,pins =
  172 + <2 9 0x2 0x0 /* PC9 periph B */
  173 + 2 11 0x2 0x0>; /* PC11 periph B */
  174 + };
  175 + };
  176 +
  177 + uart3 {
  178 + pinctrl_uart3: uart3-0 {
  179 + atmel,pins =
  180 + <1 8 0x1 0x1 /* PB9 periph A with pullup */
  181 + 1 9 0x1 0x0>; /* PB8 periph A */
  182 + };
  183 +
  184 + pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  185 + atmel,pins =
  186 + <0 23 0x2 0x0 /* PA23 periph B */
  187 + 0 24 0x2 0x0>; /* PA24 periph B */
  188 + };
  189 + };
  190 +
128 191 pioA: gpio@fffff200 {
129 192 compatible = "atmel,at91rm9200-gpio";
130 193 reg = <0xfffff200 0x200>;
... ... @@ -180,6 +243,8 @@
180 243 compatible = "atmel,at91sam9260-usart";
181 244 reg = <0xffffee00 0x200>;
182 245 interrupts = <1 4 7>;
  246 + pinctrl-names = "default";
  247 + pinctrl-0 = <&pinctrl_dbgu>;
183 248 status = "disabled";
184 249 };
185 250  
... ... @@ -189,6 +254,8 @@
189 254 interrupts = <7 4 5>;
190 255 atmel,use-dma-rx;
191 256 atmel,use-dma-tx;
  257 + pinctrl-names = "default";
  258 + pinctrl-0 = <&pinctrl_uart0>;
192 259 status = "disabled";
193 260 };
194 261  
... ... @@ -198,6 +265,8 @@
198 265 interrupts = <8 4 5>;
199 266 atmel,use-dma-rx;
200 267 atmel,use-dma-tx;
  268 + pinctrl-names = "default";
  269 + pinctrl-0 = <&pinctrl_uart1>;
201 270 status = "disabled";
202 271 };
203 272  
... ... @@ -207,6 +276,8 @@
207 276 interrupts = <9 4 5>;
208 277 atmel,use-dma-rx;
209 278 atmel,use-dma-tx;
  279 + pinctrl-names = "default";
  280 + pinctrl-0 = <&pinctrl_uart2>;
210 281 status = "disabled";
211 282 };
212 283  
... ... @@ -216,6 +287,8 @@
216 287 interrupts = <10 4 5>;
217 288 atmel,use-dma-rx;
218 289 atmel,use-dma-tx;
  290 + pinctrl-names = "default";
  291 + pinctrl-0 = <&pinctrl_uart3>;
219 292 status = "disabled";
220 293 };
221 294  
arch/arm/boot/dts/at91sam9n12.dtsi
... ... @@ -117,7 +117,80 @@
117 117 >;
118 118  
119 119 /* shared pinctrl settings */
  120 + dbgu {
  121 + pinctrl_dbgu: dbgu-0 {
  122 + atmel,pins =
  123 + <0 9 0x1 0x0 /* PA9 periph A */
  124 + 0 10 0x1 0x1>; /* PA10 periph with pullup */
  125 + };
  126 + };
120 127  
  128 + uart0 {
  129 + pinctrl_uart0: uart0-0 {
  130 + atmel,pins =
  131 + <0 1 0x1 0x1 /* PA1 periph A with pullup */
  132 + 0 0 0x1 0x0>; /* PA0 periph A */
  133 + };
  134 +
  135 + pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  136 + atmel,pins =
  137 + <0 2 0x1 0x0 /* PA2 periph A */
  138 + 0 3 0x1 0x0>; /* PA3 periph A */
  139 + };
  140 + };
  141 +
  142 + uart1 {
  143 + pinctrl_uart1: uart1-0 {
  144 + atmel,pins =
  145 + <0 6 0x1 0x1 /* PA6 periph A with pullup */
  146 + 0 5 0x1 0x0>; /* PA5 periph A */
  147 + };
  148 + };
  149 +
  150 + uart2 {
  151 + pinctrl_uart2: uart2-0 {
  152 + atmel,pins =
  153 + <0 8 0x1 0x1 /* PA8 periph A with pullup */
  154 + 0 7 0x1 0x0>; /* PA7 periph A */
  155 + };
  156 +
  157 + pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  158 + atmel,pins =
  159 + <1 0 0x2 0x0 /* PB0 periph B */
  160 + 1 1 0x2 0x0>; /* PB1 periph B */
  161 + };
  162 + };
  163 +
  164 + uart3 {
  165 + pinctrl_uart3: uart3-0 {
  166 + atmel,pins =
  167 + <2 23 0x2 0x1 /* PC23 periph B with pullup */
  168 + 2 22 0x2 0x0>; /* PC22 periph B */
  169 + };
  170 +
  171 + pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  172 + atmel,pins =
  173 + <2 24 0x2 0x0 /* PC24 periph B */
  174 + 2 25 0x2 0x0>; /* PC25 periph B */
  175 + };
  176 + };
  177 +
  178 + usart0 {
  179 + pinctrl_usart0: usart0-0 {
  180 + atmel,pins =
  181 + <2 9 0x3 0x1 /* PC9 periph C with pullup */
  182 + 2 8 0x3 0x0>; /* PC8 periph C */
  183 + };
  184 + };
  185 +
  186 + usart1 {
  187 + pinctrl_usart1: usart1-0 {
  188 + atmel,pins =
  189 + <2 16 0x3 0x1 /* PC17 periph C with pullup */
  190 + 2 17 0x3 0x0>; /* PC16 periph C */
  191 + };
  192 + };
  193 +
121 194 pioA: gpio@fffff400 {
122 195 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
123 196 reg = <0xfffff400 0x200>;
... ... @@ -163,6 +236,8 @@
163 236 compatible = "atmel,at91sam9260-usart";
164 237 reg = <0xfffff200 0x200>;
165 238 interrupts = <1 4 7>;
  239 + pinctrl-names = "default";
  240 + pinctrl-0 = <&pinctrl_dbgu>;
166 241 status = "disabled";
167 242 };
168 243  
... ... @@ -172,6 +247,8 @@
172 247 interrupts = <5 4 5>;
173 248 atmel,use-dma-rx;
174 249 atmel,use-dma-tx;
  250 + pinctrl-names = "default";
  251 + pinctrl-0 = <&pinctrl_uart0>;
175 252 status = "disabled";
176 253 };
177 254  
... ... @@ -181,6 +258,8 @@
181 258 interrupts = <6 4 5>;
182 259 atmel,use-dma-rx;
183 260 atmel,use-dma-tx;
  261 + pinctrl-names = "default";
  262 + pinctrl-0 = <&pinctrl_uart1>;
184 263 status = "disabled";
185 264 };
186 265  
... ... @@ -190,6 +269,8 @@
190 269 interrupts = <7 4 5>;
191 270 atmel,use-dma-rx;
192 271 atmel,use-dma-tx;
  272 + pinctrl-names = "default";
  273 + pinctrl-0 = <&pinctrl_uart2>;
193 274 status = "disabled";
194 275 };
195 276  
... ... @@ -199,6 +280,8 @@
199 280 interrupts = <8 4 5>;
200 281 atmel,use-dma-rx;
201 282 atmel,use-dma-tx;
  283 + pinctrl-names = "default";
  284 + pinctrl-0 = <&pinctrl_uart3>;
202 285 status = "disabled";
203 286 };
204 287  
arch/arm/boot/dts/at91sam9x25.dtsi
  1 +/*
  2 + * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
  3 + *
  4 + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5 + *
  6 + * Licensed under GPLv2.
  7 + */
  8 +
  9 +/include/ "at91sam9x5.dtsi"
  10 +
  11 +/ {
  12 + model = "Atmel AT91SAM9X25 SoC";
  13 + compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
  14 +
  15 + ahb {
  16 + apb {
  17 + pinctrl@fffff400 {
  18 + atmel,mux-mask = <
  19 + /* A B C */
  20 + 0xffffffff 0xffe03fff 0xc000001c /* pioA */
  21 + 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
  22 + 0x80000000 0xfffd0000 0xb83fffff /* pioC */
  23 + 0x003fffff 0x003f8000 0x00000000 /* pioD */
  24 + >;
  25 + };
  26 + };
  27 + };
  28 +};
arch/arm/boot/dts/at91sam9x25ek.dts
  1 +/*
  2 + * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
  3 + *
  4 + * Copyright (C) 2012 Atmel,
  5 + * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  6 + *
  7 + * Licensed under GPLv2 or later.
  8 + */
  9 +/dts-v1/;
  10 +/include/ "at91sam9x25.dtsi"
  11 +/include/ "at91sam9x5ek.dtsi"
  12 +
  13 +/ {
  14 + model = "Atmel AT91SAM9G25-EK";
  15 + compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
  16 +};
arch/arm/boot/dts/at91sam9x35.dtsi
  1 +/*
  2 + * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
  3 + *
  4 + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5 + *
  6 + * Licensed under GPLv2.
  7 + */
  8 +
  9 +/include/ "at91sam9x5.dtsi"
  10 +
  11 +/ {
  12 + model = "Atmel AT91SAM9X35 SoC";
  13 + compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
  14 +
  15 + ahb {
  16 + apb {
  17 + pinctrl@fffff400 {
  18 + atmel,mux-mask = <
  19 + /* A B C */
  20 + 0xffffffff 0xffe03fff 0xc000000c /* pioA */
  21 + 0x000406ff 0x00047e3f 0x00000000 /* pioB */
  22 + 0xfdffffff 0x00000000 0xb83fffff /* pioC */
  23 + 0x003fffff 0x003f8000 0x00000000 /* pioD */
  24 + >;
  25 + };
  26 + };
  27 + };
  28 +};
arch/arm/boot/dts/at91sam9x35ek.dts
  1 +/*
  2 + * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
  3 + *
  4 + * Copyright (C) 2012 Atmel,
  5 + * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  6 + *
  7 + * Licensed under GPLv2 or later.
  8 + */
  9 +/dts-v1/;
  10 +/include/ "at91sam9x35.dtsi"
  11 +/include/ "at91sam9x5ek.dtsi"
  12 +
  13 +/ {
  14 + model = "Atmel AT91SAM9X35-EK";
  15 + compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
  16 +};
arch/arm/boot/dts/at91sam9x5.dtsi
... ... @@ -111,22 +111,93 @@
111 111 interrupts = <21 4 0>;
112 112 };
113 113  
114   - pinctrl@fffff200 {
  114 + pinctrl@fffff400 {
115 115 #address-cells = <1>;
116 116 #size-cells = <1>;
117 117 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
118 118 ranges = <0xfffff400 0xfffff400 0x800>;
119 119  
120   - atmel,mux-mask = <
121   - /* A B C */
122   - 0xffffffff 0xffe0399f 0xc000001c /* pioA */
123   - 0xffffffff 0xffc003ff 0xffc003ff /* pioB */
124   - 0xffffffff 0xffc003ff 0xffc003ff /* pioC */
125   - 0xffffffff 0xffc003ff 0xffc003ff /* pioD */
126   - >;
127   -
128 120 /* shared pinctrl settings */
  121 + dbgu {
  122 + pinctrl_dbgu: dbgu-0 {
  123 + atmel,pins =
  124 + <0 9 0x1 0x0 /* PA9 periph A */
  125 + 0 10 0x1 0x1>; /* PA10 periph A with pullup */
  126 + };
  127 + };
129 128  
  129 + uart0 {
  130 + pinctrl_uart0: uart0-0 {
  131 + atmel,pins =
  132 + <0 0 0x1 0x1 /* PA0 periph A with pullup */
  133 + 0 1 0x1 0x0>; /* PA1 periph A */
  134 + };
  135 +
  136 + pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  137 + atmel,pins =
  138 + <0 2 0x1 0x0 /* PA2 periph A */
  139 + 0 3 0x1 0x0>; /* PA3 periph A */
  140 + };
  141 + };
  142 +
  143 + uart1 {
  144 + pinctrl_uart1: uart1-0 {
  145 + atmel,pins =
  146 + <0 5 0x1 0x1 /* PA5 periph A with pullup */
  147 + 0 6 0x1 0x0>; /* PA6 periph A */
  148 + };
  149 +
  150 + pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  151 + atmel,pins =
  152 + <3 27 0x3 0x0 /* PC27 periph C */
  153 + 3 28 0x3 0x0>; /* PC28 periph C */
  154 + };
  155 + };
  156 +
  157 + uart2 {
  158 + pinctrl_uart2: uart2-0 {
  159 + atmel,pins =
  160 + <0 7 0x1 0x1 /* PA7 periph A with pullup */
  161 + 0 8 0x1 0x0>; /* PA8 periph A */
  162 + };
  163 +
  164 + pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  165 + atmel,pins =
  166 + <0 0 0x2 0x0 /* PB0 periph B */
  167 + 0 1 0x2 0x0>; /* PB1 periph B */
  168 + };
  169 + };
  170 +
  171 + uart3 {
  172 + pinctrl_uart3: uart3-0 {
  173 + atmel,pins =
  174 + <3 23 0x2 0x1 /* PC22 periph B with pullup */
  175 + 3 23 0x2 0x0>; /* PC23 periph B */
  176 + };
  177 +
  178 + pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  179 + atmel,pins =
  180 + <3 24 0x2 0x0 /* PC24 periph B */
  181 + 3 25 0x2 0x0>; /* PC25 periph B */
  182 + };
  183 + };
  184 +
  185 + usart0 {
  186 + pinctrl_usart0: usart0-0 {
  187 + atmel,pins =
  188 + <3 8 0x3 0x0 /* PC8 periph C */
  189 + 3 9 0x3 0x1>; /* PC9 periph C with pullup */
  190 + };
  191 + };
  192 +
  193 + usart1 {
  194 + pinctrl_usart1: usart1-0 {
  195 + atmel,pins =
  196 + <3 16 0x3 0x0 /* PC16 periph C */
  197 + 3 17 0x3 0x1>; /* PC17 periph C with pullup */
  198 + };
  199 + };
  200 +
130 201 pioA: gpio@fffff400 {
131 202 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
132 203 reg = <0xfffff400 0x200>;
... ... @@ -174,6 +245,8 @@
174 245 compatible = "atmel,at91sam9260-usart";
175 246 reg = <0xfffff200 0x200>;
176 247 interrupts = <1 4 7>;
  248 + pinctrl-names = "default";
  249 + pinctrl-0 = <&pinctrl_dbgu>;
177 250 status = "disabled";
178 251 };
179 252  
... ... @@ -183,6 +256,8 @@
183 256 interrupts = <5 4 5>;
184 257 atmel,use-dma-rx;
185 258 atmel,use-dma-tx;
  259 + pinctrl-names = "default";
  260 + pinctrl-0 = <&pinctrl_uart0>;
186 261 status = "disabled";
187 262 };
188 263  
... ... @@ -192,6 +267,8 @@
192 267 interrupts = <6 4 5>;
193 268 atmel,use-dma-rx;
194 269 atmel,use-dma-tx;
  270 + pinctrl-names = "default";
  271 + pinctrl-0 = <&pinctrl_uart1>;
195 272 status = "disabled";
196 273 };
197 274  
... ... @@ -201,6 +278,8 @@
201 278 interrupts = <7 4 5>;
202 279 atmel,use-dma-rx;
203 280 atmel,use-dma-tx;
  281 + pinctrl-names = "default";
  282 + pinctrl-0 = <&pinctrl_uart2>;
204 283 status = "disabled";
205 284 };
206 285  
arch/arm/boot/dts/at91sam9x5ek.dtsi
  1 +/*
  2 + * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
  3 + *
  4 + * Copyright (C) 2012 Atmel,
  5 + * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  6 + *
  7 + * Licensed under GPLv2 or later.
  8 + */
  9 +/include/ "at91sam9x5cm.dtsi"
  10 +
  11 +/ {
  12 + model = "Atmel AT91SAM9X5-EK";
  13 + compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
  14 +
  15 + chosen {
  16 + bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
  17 + };
  18 +
  19 + ahb {
  20 + apb {
  21 + dbgu: serial@fffff200 {
  22 + status = "okay";
  23 + };
  24 +
  25 + usart0: serial@f801c000 {
  26 + status = "okay";
  27 + };
  28 +
  29 + macb0: ethernet@f802c000 {
  30 + phy-mode = "rmii";
  31 + status = "okay";
  32 + };
  33 +
  34 + i2c0: i2c@f8010000 {
  35 + status = "okay";
  36 + };
  37 +
  38 + i2c1: i2c@f8014000 {
  39 + status = "okay";
  40 + };
  41 +
  42 + i2c2: i2c@f8018000 {
  43 + status = "okay";
  44 + };
  45 + };
  46 +
  47 + usb0: ohci@00600000 {
  48 + status = "okay";
  49 + num-ports = <2>;
  50 + atmel,vbus-gpio = <&pioD 19 1
  51 + &pioD 20 1
  52 + >;
  53 + };
  54 +
  55 + usb1: ehci@00700000 {
  56 + status = "okay";
  57 + };
  58 + };
  59 +};