Commit ed2b03ed3cec2a4719d04ef208319f9de6a4258a
Committed by
Ralf Baechle
1 parent
08d9d1c4d4
Exists in
master
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7 other branches
MIPS: MIPS64R2: Fix buggy __arch_swab64
The way the code is written it was assuming dshd has the function of a hypothetical dshw instruction ... Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Showing 1 changed file with 2 additions and 3 deletions Inline Diff
arch/mips/include/asm/byteorder.h
1 | /* | 1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | 2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 1996, 99, 2003 by Ralf Baechle | 6 | * Copyright (C) 1996, 99, 2003 by Ralf Baechle |
7 | */ | 7 | */ |
8 | #ifndef _ASM_BYTEORDER_H | 8 | #ifndef _ASM_BYTEORDER_H |
9 | #define _ASM_BYTEORDER_H | 9 | #define _ASM_BYTEORDER_H |
10 | 10 | ||
11 | #include <linux/compiler.h> | 11 | #include <linux/compiler.h> |
12 | #include <asm/types.h> | 12 | #include <asm/types.h> |
13 | 13 | ||
14 | #if defined(__MIPSEB__) | 14 | #if defined(__MIPSEB__) |
15 | # define __BIG_ENDIAN | 15 | # define __BIG_ENDIAN |
16 | #elif defined(__MIPSEL__) | 16 | #elif defined(__MIPSEL__) |
17 | # define __LITTLE_ENDIAN | 17 | # define __LITTLE_ENDIAN |
18 | #else | 18 | #else |
19 | # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" | 19 | # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" |
20 | #endif | 20 | #endif |
21 | 21 | ||
22 | #define __SWAB_64_THRU_32__ | 22 | #define __SWAB_64_THRU_32__ |
23 | 23 | ||
24 | #ifdef CONFIG_CPU_MIPSR2 | 24 | #ifdef CONFIG_CPU_MIPSR2 |
25 | 25 | ||
26 | static inline __attribute_const__ __u16 __arch_swab16(__u16 x) | 26 | static inline __attribute_const__ __u16 __arch_swab16(__u16 x) |
27 | { | 27 | { |
28 | __asm__( | 28 | __asm__( |
29 | " wsbh %0, %1 \n" | 29 | " wsbh %0, %1 \n" |
30 | : "=r" (x) | 30 | : "=r" (x) |
31 | : "r" (x)); | 31 | : "r" (x)); |
32 | 32 | ||
33 | return x; | 33 | return x; |
34 | } | 34 | } |
35 | #define __arch_swab16 __arch_swab16 | 35 | #define __arch_swab16 __arch_swab16 |
36 | 36 | ||
37 | static inline __attribute_const__ __u32 __arch_swab32(__u32 x) | 37 | static inline __attribute_const__ __u32 __arch_swab32(__u32 x) |
38 | { | 38 | { |
39 | __asm__( | 39 | __asm__( |
40 | " wsbh %0, %1 \n" | 40 | " wsbh %0, %1 \n" |
41 | " rotr %0, %0, 16 \n" | 41 | " rotr %0, %0, 16 \n" |
42 | : "=r" (x) | 42 | : "=r" (x) |
43 | : "r" (x)); | 43 | : "r" (x)); |
44 | 44 | ||
45 | return x; | 45 | return x; |
46 | } | 46 | } |
47 | #define __arch_swab32 __arch_swab32 | 47 | #define __arch_swab32 __arch_swab32 |
48 | 48 | ||
49 | #ifdef CONFIG_CPU_MIPS64_R2 | 49 | #ifdef CONFIG_CPU_MIPS64_R2 |
50 | static inline __attribute_const__ __u64 __arch_swab64(__u64 x) | 50 | static inline __attribute_const__ __u64 __arch_swab64(__u64 x) |
51 | { | 51 | { |
52 | __asm__( | 52 | __asm__( |
53 | " dsbh %0, %1 \n" | 53 | " dsbh %0, %1\n" |
54 | " dshd %0, %0 \n" | 54 | " dshd %0, %0" |
55 | " drotr %0, %0, 32 \n" | ||
56 | : "=r" (x) | 55 | : "=r" (x) |
57 | : "r" (x)); | 56 | : "r" (x)); |
58 | 57 | ||
59 | return x; | 58 | return x; |
60 | } | 59 | } |
61 | #define __arch_swab64 __arch_swab64 | 60 | #define __arch_swab64 __arch_swab64 |
62 | #endif /* CONFIG_CPU_MIPS64_R2 */ | 61 | #endif /* CONFIG_CPU_MIPS64_R2 */ |
63 | 62 | ||
64 | #endif /* CONFIG_CPU_MIPSR2 */ | 63 | #endif /* CONFIG_CPU_MIPSR2 */ |
65 | 64 | ||
66 | #include <linux/byteorder.h> | 65 | #include <linux/byteorder.h> |
67 | 66 | ||
68 | #endif /* _ASM_BYTEORDER_H */ | 67 | #endif /* _ASM_BYTEORDER_H */ |
69 | 68 |