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Commit edb6310aaa0dfc3da303a4ba6dff9dce3fbaa8d3

Authored by Daniel Laird
Committed by Ralf Baechle
1 parent 537fa37c86
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

MIPS: Add support for NXP PNX833x (STB222/5) into linux kernel 

The following patch add support for the NXP PNX833x SOC.  More
specifically it adds support for the STB222/5 variant. It fixes
the vectored interrupt issue.

Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 16 changed files with 2783 additions and 0 deletions Side-by-side Diff

... ... @@ -261,6 +261,19 @@
261 261 select SYS_HAS_CPU_VR41XX
262 262 select GENERIC_HARDIRQS_NO__DO_IRQ
263 263  
  264 +config NXP_STB220
  265 + bool "NXP STB220 board"
  266 + select SOC_PNX833X
  267 + help
  268 + Support for NXP Semiconductors STB220 Development Board.
  269 +
  270 +config NXP_STB225
  271 + bool "NXP 225 board"
  272 + select SOC_PNX833X
  273 + select SOC_PNX8335
  274 + help
  275 + Support for NXP Semiconductors STB225 Development Board.
  276 +
264 277 config PNX8550_JBS
265 278 bool "NXP PNX8550 based JBS board"
266 279 select PNX8550
... ... @@ -848,6 +861,24 @@
848 861 config MIPS_RM9122
849 862 bool
850 863 select SERIAL_RM9000
  864 +
  865 +config SOC_PNX833X
  866 + bool
  867 + select CEVT_R4K
  868 + select CSRC_R4K
  869 + select IRQ_CPU
  870 + select DMA_NONCOHERENT
  871 + select SYS_HAS_CPU_MIPS32_R2
  872 + select SYS_SUPPORTS_32BIT_KERNEL
  873 + select SYS_SUPPORTS_LITTLE_ENDIAN
  874 + select SYS_SUPPORTS_BIG_ENDIAN
  875 + select GENERIC_HARDIRQS_NO__DO_IRQ
  876 + select GENERIC_GPIO
  877 + select CPU_MIPSR2_IRQ_VI
  878 +
  879 +config SOC_PNX8335
  880 + bool
  881 + select SOC_PNX833X
851 882  
852 883 config PNX8550
853 884 bool
... ... @@ -381,6 +381,14 @@
381 381 #
382 382 load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
383 383  
  384 +# NXP STB225
  385 +core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/
  386 +cflags-$(CONFIG_SOC_PNX833X) += -Iarch/mips/include/asm/mach-pnx833x
  387 +libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/
  388 +load-$(CONFIG_NXP_STB220) += 0xffffffff80001000
  389 +libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/
  390 +load-$(CONFIG_NXP_STB225) += 0xffffffff80001000
  391 +
384 392 #
385 393 # Common NXP PNX8550
386 394 #
arch/mips/configs/pnx8335-stb225_defconfig
Diff comments   View file @ edb6310
Changes suppressed. Click to show
  1 +#
  2 +# Automatically generated make config: don't edit
  3 +# Linux kernel version: 2.6.26
  4 +# Sat Jul 26 09:02:59 2008
  5 +#
  6 +CONFIG_MIPS=y
  7 +
  8 +#
  9 +# Machine selection
  10 +#
  11 +# CONFIG_MACH_ALCHEMY is not set
  12 +# CONFIG_BASLER_EXCITE is not set
  13 +# CONFIG_BCM47XX is not set
  14 +# CONFIG_MIPS_COBALT is not set
  15 +# CONFIG_MACH_DECSTATION is not set
  16 +# CONFIG_MACH_JAZZ is not set
  17 +# CONFIG_LASAT is not set
  18 +# CONFIG_LEMOTE_FULONG is not set
  19 +# CONFIG_MIPS_MALTA is not set
  20 +# CONFIG_MIPS_SIM is not set
  21 +# CONFIG_MARKEINS is not set
  22 +# CONFIG_MACH_VR41XX is not set
  23 +# CONFIG_NXP_STB220 is not set
  24 +CONFIG_NXP_STB225=y
  25 +# CONFIG_PNX8550_JBS is not set
  26 +# CONFIG_PNX8550_STB810 is not set
  27 +# CONFIG_PMC_MSP is not set
  28 +# CONFIG_PMC_YOSEMITE is not set
  29 +# CONFIG_SGI_IP22 is not set
  30 +# CONFIG_SGI_IP27 is not set
  31 +# CONFIG_SGI_IP28 is not set
  32 +# CONFIG_SGI_IP32 is not set
  33 +# CONFIG_SIBYTE_CRHINE is not set
  34 +# CONFIG_SIBYTE_CARMEL is not set
  35 +# CONFIG_SIBYTE_CRHONE is not set
  36 +# CONFIG_SIBYTE_RHONE is not set
  37 +# CONFIG_SIBYTE_SWARM is not set
  38 +# CONFIG_SIBYTE_LITTLESUR is not set
  39 +# CONFIG_SIBYTE_SENTOSA is not set
  40 +# CONFIG_SIBYTE_BIGSUR is not set
  41 +# CONFIG_SNI_RM is not set
  42 +# CONFIG_MACH_TX39XX is not set
  43 +# CONFIG_MACH_TX49XX is not set
  44 +# CONFIG_WR_PPMC is not set
  45 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
  46 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
  47 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
  48 +CONFIG_ARCH_SUPPORTS_OPROFILE=y
  49 +CONFIG_GENERIC_FIND_NEXT_BIT=y
  50 +CONFIG_GENERIC_HWEIGHT=y
  51 +CONFIG_GENERIC_CALIBRATE_DELAY=y
  52 +CONFIG_GENERIC_CLOCKEVENTS=y
  53 +CONFIG_GENERIC_TIME=y
  54 +CONFIG_GENERIC_CMOS_UPDATE=y
  55 +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
  56 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
  57 +CONFIG_CEVT_R4K=y
  58 +CONFIG_CSRC_R4K=y
  59 +CONFIG_DMA_NONCOHERENT=y
  60 +CONFIG_DMA_NEED_PCI_MAP_STATE=y
  61 +# CONFIG_HOTPLUG_CPU is not set
  62 +# CONFIG_NO_IOPORT is not set
  63 +CONFIG_GENERIC_GPIO=y
  64 +# CONFIG_CPU_BIG_ENDIAN is not set
  65 +CONFIG_CPU_LITTLE_ENDIAN=y
  66 +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
  67 +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
  68 +CONFIG_IRQ_CPU=y
  69 +CONFIG_SOC_PNX833X=y
  70 +CONFIG_SOC_PNX8335=y
  71 +CONFIG_MIPS_L1_CACHE_SHIFT=5
  72 +
  73 +#
  74 +# CPU selection
  75 +#
  76 +# CONFIG_CPU_LOONGSON2 is not set
  77 +# CONFIG_CPU_MIPS32_R1 is not set
  78 +CONFIG_CPU_MIPS32_R2=y
  79 +# CONFIG_CPU_MIPS64_R1 is not set
  80 +# CONFIG_CPU_MIPS64_R2 is not set
  81 +# CONFIG_CPU_R3000 is not set
  82 +# CONFIG_CPU_TX39XX is not set
  83 +# CONFIG_CPU_VR41XX is not set
  84 +# CONFIG_CPU_R4300 is not set
  85 +# CONFIG_CPU_R4X00 is not set
  86 +# CONFIG_CPU_TX49XX is not set
  87 +# CONFIG_CPU_R5000 is not set
  88 +# CONFIG_CPU_R5432 is not set
  89 +# CONFIG_CPU_R6000 is not set
  90 +# CONFIG_CPU_NEVADA is not set
  91 +# CONFIG_CPU_R8000 is not set
  92 +# CONFIG_CPU_R10000 is not set
  93 +# CONFIG_CPU_RM7000 is not set
  94 +# CONFIG_CPU_RM9000 is not set
  95 +# CONFIG_CPU_SB1 is not set
  96 +CONFIG_SYS_HAS_CPU_MIPS32_R2=y
  97 +CONFIG_CPU_MIPS32=y
  98 +CONFIG_CPU_MIPSR2=y
  99 +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
  100 +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
  101 +
  102 +#
  103 +# Kernel type
  104 +#
  105 +CONFIG_32BIT=y
  106 +# CONFIG_64BIT is not set
  107 +CONFIG_PAGE_SIZE_4KB=y
  108 +# CONFIG_PAGE_SIZE_8KB is not set
  109 +# CONFIG_PAGE_SIZE_16KB is not set
  110 +# CONFIG_PAGE_SIZE_64KB is not set
  111 +CONFIG_CPU_HAS_PREFETCH=y
  112 +CONFIG_MIPS_MT_DISABLED=y
  113 +# CONFIG_MIPS_MT_SMP is not set
  114 +# CONFIG_MIPS_MT_SMTC is not set
  115 +CONFIG_CPU_HAS_LLSC=y
  116 +CONFIG_CPU_MIPSR2_IRQ_VI=y
  117 +CONFIG_CPU_HAS_SYNC=y
  118 +CONFIG_GENERIC_HARDIRQS=y
  119 +CONFIG_GENERIC_IRQ_PROBE=y
  120 +CONFIG_CPU_SUPPORTS_HIGHMEM=y
  121 +CONFIG_ARCH_FLATMEM_ENABLE=y
  122 +CONFIG_ARCH_POPULATES_NODE_MAP=y
  123 +CONFIG_SELECT_MEMORY_MODEL=y
  124 +CONFIG_FLATMEM_MANUAL=y
  125 +# CONFIG_DISCONTIGMEM_MANUAL is not set
  126 +# CONFIG_SPARSEMEM_MANUAL is not set
  127 +CONFIG_FLATMEM=y
  128 +CONFIG_FLAT_NODE_MEM_MAP=y
  129 +# CONFIG_SPARSEMEM_STATIC is not set
  130 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
  131 +CONFIG_PAGEFLAGS_EXTENDED=y
  132 +CONFIG_SPLIT_PTLOCK_CPUS=4
  133 +# CONFIG_RESOURCES_64BIT is not set
  134 +CONFIG_ZONE_DMA_FLAG=0
  135 +CONFIG_VIRT_TO_BUS=y
  136 +CONFIG_TICK_ONESHOT=y
  137 +CONFIG_NO_HZ=y
  138 +CONFIG_HIGH_RES_TIMERS=y
  139 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
  140 +# CONFIG_HZ_48 is not set
  141 +# CONFIG_HZ_100 is not set
  142 +CONFIG_HZ_128=y
  143 +# CONFIG_HZ_250 is not set
  144 +# CONFIG_HZ_256 is not set
  145 +# CONFIG_HZ_1000 is not set
  146 +# CONFIG_HZ_1024 is not set
  147 +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
  148 +CONFIG_HZ=128
  149 +# CONFIG_PREEMPT_NONE is not set
  150 +CONFIG_PREEMPT_VOLUNTARY=y
  151 +# CONFIG_PREEMPT is not set
  152 +# CONFIG_KEXEC is not set
  153 +# CONFIG_SECCOMP is not set
  154 +CONFIG_LOCKDEP_SUPPORT=y
  155 +CONFIG_STACKTRACE_SUPPORT=y
  156 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
  157 +
  158 +#
  159 +# General setup
  160 +#
  161 +CONFIG_EXPERIMENTAL=y
  162 +CONFIG_BROKEN_ON_SMP=y
  163 +CONFIG_INIT_ENV_ARG_LIMIT=32
  164 +CONFIG_LOCALVERSION=""
  165 +# CONFIG_LOCALVERSION_AUTO is not set
  166 +# CONFIG_SWAP is not set
  167 +CONFIG_SYSVIPC=y
  168 +CONFIG_SYSVIPC_SYSCTL=y
  169 +# CONFIG_POSIX_MQUEUE is not set
  170 +# CONFIG_BSD_PROCESS_ACCT is not set
  171 +# CONFIG_TASKSTATS is not set
  172 +# CONFIG_AUDIT is not set
  173 +# CONFIG_IKCONFIG is not set
  174 +CONFIG_LOG_BUF_SHIFT=14
  175 +# CONFIG_CGROUPS is not set
  176 +# CONFIG_GROUP_SCHED is not set
  177 +CONFIG_SYSFS_DEPRECATED=y
  178 +CONFIG_SYSFS_DEPRECATED_V2=y
  179 +# CONFIG_RELAY is not set
  180 +# CONFIG_NAMESPACES is not set
  181 +# CONFIG_BLK_DEV_INITRD is not set
  182 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
  183 +CONFIG_SYSCTL=y
  184 +CONFIG_EMBEDDED=y
  185 +CONFIG_SYSCTL_SYSCALL=y
  186 +CONFIG_SYSCTL_SYSCALL_CHECK=y
  187 +CONFIG_KALLSYMS=y
  188 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
  189 +CONFIG_HOTPLUG=y
  190 +CONFIG_PRINTK=y
  191 +CONFIG_BUG=y
  192 +CONFIG_ELF_CORE=y
  193 +CONFIG_PCSPKR_PLATFORM=y
  194 +CONFIG_COMPAT_BRK=y
  195 +CONFIG_BASE_FULL=y
  196 +CONFIG_FUTEX=y
  197 +CONFIG_ANON_INODES=y
  198 +CONFIG_EPOLL=y
  199 +CONFIG_SIGNALFD=y
  200 +CONFIG_TIMERFD=y
  201 +CONFIG_EVENTFD=y
  202 +CONFIG_SHMEM=y
  203 +CONFIG_VM_EVENT_COUNTERS=y
  204 +CONFIG_SLAB=y
  205 +# CONFIG_SLUB is not set
  206 +# CONFIG_SLOB is not set
  207 +# CONFIG_PROFILING is not set
  208 +# CONFIG_MARKERS is not set
  209 +CONFIG_HAVE_OPROFILE=y
  210 +# CONFIG_HAVE_KPROBES is not set
  211 +# CONFIG_HAVE_KRETPROBES is not set
  212 +# CONFIG_HAVE_DMA_ATTRS is not set
  213 +# CONFIG_USE_GENERIC_SMP_HELPERS is not set
  214 +CONFIG_PROC_PAGE_MONITOR=y
  215 +CONFIG_SLABINFO=y
  216 +CONFIG_RT_MUTEXES=y
  217 +# CONFIG_TINY_SHMEM is not set
  218 +CONFIG_BASE_SMALL=0
  219 +CONFIG_MODULES=y
  220 +# CONFIG_MODULE_FORCE_LOAD is not set
  221 +CONFIG_MODULE_UNLOAD=y
  222 +# CONFIG_MODULE_FORCE_UNLOAD is not set
  223 +# CONFIG_MODVERSIONS is not set
  224 +# CONFIG_MODULE_SRCVERSION_ALL is not set
  225 +CONFIG_KMOD=y
  226 +CONFIG_BLOCK=y
  227 +# CONFIG_LBD is not set
  228 +# CONFIG_BLK_DEV_IO_TRACE is not set
  229 +# CONFIG_LSF is not set
  230 +# CONFIG_BLK_DEV_BSG is not set
  231 +# CONFIG_BLK_DEV_INTEGRITY is not set
  232 +
  233 +#
  234 +# IO Schedulers
  235 +#
  236 +CONFIG_IOSCHED_NOOP=y
  237 +# CONFIG_IOSCHED_AS is not set
  238 +# CONFIG_IOSCHED_DEADLINE is not set
  239 +# CONFIG_IOSCHED_CFQ is not set
  240 +# CONFIG_DEFAULT_AS is not set
  241 +# CONFIG_DEFAULT_DEADLINE is not set
  242 +# CONFIG_DEFAULT_CFQ is not set
  243 +CONFIG_DEFAULT_NOOP=y
  244 +CONFIG_DEFAULT_IOSCHED="noop"
  245 +CONFIG_CLASSIC_RCU=y
  246 +
  247 +#
  248 +# Bus options (PCI, PCMCIA, EISA, ISA, TC)
  249 +#
  250 +# CONFIG_ARCH_SUPPORTS_MSI is not set
  251 +CONFIG_MMU=y
  252 +# CONFIG_PCCARD is not set
  253 +
  254 +#
  255 +# Executable file formats
  256 +#
  257 +CONFIG_BINFMT_ELF=y
  258 +# CONFIG_BINFMT_MISC is not set
  259 +CONFIG_TRAD_SIGNALS=y
  260 +
  261 +#
  262 +# Power management options
  263 +#
  264 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
  265 +CONFIG_PM=y
  266 +# CONFIG_PM_DEBUG is not set
  267 +CONFIG_PM_SLEEP=y
  268 +CONFIG_SUSPEND=y
  269 +CONFIG_SUSPEND_FREEZER=y
  270 +
  271 +#
  272 +# Networking
  273 +#
  274 +CONFIG_NET=y
  275 +
  276 +#
  277 +# Networking options
  278 +#
  279 +CONFIG_PACKET=y
  280 +# CONFIG_PACKET_MMAP is not set
  281 +CONFIG_UNIX=y
  282 +CONFIG_XFRM=y
  283 +# CONFIG_XFRM_USER is not set
  284 +# CONFIG_XFRM_SUB_POLICY is not set
  285 +# CONFIG_XFRM_MIGRATE is not set
  286 +# CONFIG_XFRM_STATISTICS is not set
  287 +# CONFIG_NET_KEY is not set
  288 +CONFIG_INET=y
  289 +CONFIG_IP_MULTICAST=y
  290 +# CONFIG_IP_ADVANCED_ROUTER is not set
  291 +CONFIG_IP_FIB_HASH=y
  292 +CONFIG_IP_PNP=y
  293 +CONFIG_IP_PNP_DHCP=y
  294 +# CONFIG_IP_PNP_BOOTP is not set
  295 +# CONFIG_IP_PNP_RARP is not set
  296 +# CONFIG_NET_IPIP is not set
  297 +# CONFIG_NET_IPGRE is not set
  298 +# CONFIG_IP_MROUTE is not set
  299 +# CONFIG_ARPD is not set
  300 +# CONFIG_SYN_COOKIES is not set
  301 +CONFIG_INET_AH=y
  302 +# CONFIG_INET_ESP is not set
  303 +# CONFIG_INET_IPCOMP is not set
  304 +# CONFIG_INET_XFRM_TUNNEL is not set
  305 +# CONFIG_INET_TUNNEL is not set
  306 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
  307 +CONFIG_INET_XFRM_MODE_TUNNEL=y
  308 +CONFIG_INET_XFRM_MODE_BEET=y
  309 +# CONFIG_INET_LRO is not set
  310 +CONFIG_INET_DIAG=y
  311 +CONFIG_INET_TCP_DIAG=y
  312 +# CONFIG_TCP_CONG_ADVANCED is not set
  313 +CONFIG_TCP_CONG_CUBIC=y
  314 +CONFIG_DEFAULT_TCP_CONG="cubic"
  315 +# CONFIG_TCP_MD5SIG is not set
  316 +# CONFIG_IPV6 is not set
  317 +# CONFIG_NETWORK_SECMARK is not set
  318 +# CONFIG_NETFILTER is not set
  319 +# CONFIG_IP_DCCP is not set
  320 +# CONFIG_IP_SCTP is not set
  321 +# CONFIG_TIPC is not set
  322 +# CONFIG_ATM is not set
  323 +# CONFIG_BRIDGE is not set
  324 +# CONFIG_VLAN_8021Q is not set
  325 +# CONFIG_DECNET is not set
  326 +# CONFIG_LLC2 is not set
  327 +# CONFIG_IPX is not set
  328 +# CONFIG_ATALK is not set
  329 +# CONFIG_X25 is not set
  330 +# CONFIG_LAPB is not set
  331 +# CONFIG_ECONET is not set
  332 +# CONFIG_WAN_ROUTER is not set
  333 +# CONFIG_NET_SCHED is not set
  334 +
  335 +#
  336 +# Network testing
  337 +#
  338 +# CONFIG_NET_PKTGEN is not set
  339 +# CONFIG_HAMRADIO is not set
  340 +# CONFIG_CAN is not set
  341 +# CONFIG_IRDA is not set
  342 +# CONFIG_BT is not set
  343 +# CONFIG_AF_RXRPC is not set
  344 +
  345 +#
  346 +# Wireless
  347 +#
  348 +# CONFIG_CFG80211 is not set
  349 +# CONFIG_WIRELESS_EXT is not set
  350 +# CONFIG_MAC80211 is not set
  351 +# CONFIG_IEEE80211 is not set
  352 +# CONFIG_RFKILL is not set
  353 +# CONFIG_NET_9P is not set
  354 +
  355 +#
  356 +# Device Drivers
  357 +#
  358 +
  359 +#
  360 +# Generic Driver Options
  361 +#
  362 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
  363 +CONFIG_STANDALONE=y
  364 +CONFIG_PREVENT_FIRMWARE_BUILD=y
  365 +CONFIG_FW_LOADER=y
  366 +CONFIG_FIRMWARE_IN_KERNEL=y
  367 +CONFIG_EXTRA_FIRMWARE=""
  368 +# CONFIG_SYS_HYPERVISOR is not set
  369 +# CONFIG_CONNECTOR is not set
  370 +CONFIG_MTD=y
  371 +# CONFIG_MTD_DEBUG is not set
  372 +# CONFIG_MTD_CONCAT is not set
  373 +CONFIG_MTD_PARTITIONS=y
  374 +# CONFIG_MTD_REDBOOT_PARTS is not set
  375 +CONFIG_MTD_CMDLINE_PARTS=y
  376 +# CONFIG_MTD_AR7_PARTS is not set
  377 +
  378 +#
  379 +# User Modules And Translation Layers
  380 +#
  381 +CONFIG_MTD_CHAR=y
  382 +CONFIG_MTD_BLKDEVS=y
  383 +CONFIG_MTD_BLOCK=y
  384 +# CONFIG_FTL is not set
  385 +# CONFIG_NFTL is not set
  386 +# CONFIG_INFTL is not set
  387 +# CONFIG_RFD_FTL is not set
  388 +# CONFIG_SSFDC is not set
  389 +# CONFIG_MTD_OOPS is not set
  390 +
  391 +#
  392 +# RAM/ROM/Flash chip drivers
  393 +#
  394 +CONFIG_MTD_CFI=y
  395 +# CONFIG_MTD_JEDECPROBE is not set
  396 +CONFIG_MTD_GEN_PROBE=y
  397 +CONFIG_MTD_CFI_ADV_OPTIONS=y
  398 +# CONFIG_MTD_CFI_NOSWAP is not set
  399 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
  400 +CONFIG_MTD_CFI_LE_BYTE_SWAP=y
  401 +CONFIG_MTD_CFI_GEOMETRY=y
  402 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
  403 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
  404 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
  405 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
  406 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
  407 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
  408 +CONFIG_MTD_CFI_I1=y
  409 +CONFIG_MTD_CFI_I2=y
  410 +# CONFIG_MTD_CFI_I4 is not set
  411 +# CONFIG_MTD_CFI_I8 is not set
  412 +# CONFIG_MTD_OTP is not set
  413 +# CONFIG_MTD_CFI_INTELEXT is not set
  414 +CONFIG_MTD_CFI_AMDSTD=y
  415 +# CONFIG_MTD_CFI_STAA is not set
  416 +CONFIG_MTD_CFI_UTIL=y
  417 +# CONFIG_MTD_RAM is not set
  418 +# CONFIG_MTD_ROM is not set
  419 +# CONFIG_MTD_ABSENT is not set
  420 +
  421 +#
  422 +# Mapping drivers for chip access
  423 +#
  424 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
  425 +CONFIG_MTD_PHYSMAP=y
  426 +CONFIG_MTD_PHYSMAP_START=0x18000000
  427 +CONFIG_MTD_PHYSMAP_LEN=0x04000000
  428 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
  429 +# CONFIG_MTD_PLATRAM is not set
  430 +
  431 +#
  432 +# Self-contained MTD device drivers
  433 +#
  434 +# CONFIG_MTD_SLRAM is not set
  435 +# CONFIG_MTD_PHRAM is not set
  436 +# CONFIG_MTD_MTDRAM is not set
  437 +# CONFIG_MTD_BLOCK2MTD is not set
  438 +
  439 +#
  440 +# Disk-On-Chip Device Drivers
  441 +#
  442 +# CONFIG_MTD_DOC2000 is not set
  443 +# CONFIG_MTD_DOC2001 is not set
  444 +# CONFIG_MTD_DOC2001PLUS is not set
  445 +# CONFIG_MTD_NAND is not set
  446 +# CONFIG_MTD_ONENAND is not set
  447 +
  448 +#
  449 +# UBI - Unsorted block images
  450 +#
  451 +# CONFIG_MTD_UBI is not set
  452 +# CONFIG_PARPORT is not set
  453 +CONFIG_BLK_DEV=y
  454 +# CONFIG_BLK_DEV_COW_COMMON is not set
  455 +CONFIG_BLK_DEV_LOOP=y
  456 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
  457 +# CONFIG_BLK_DEV_NBD is not set
  458 +# CONFIG_BLK_DEV_RAM is not set
  459 +# CONFIG_CDROM_PKTCDVD is not set
  460 +# CONFIG_ATA_OVER_ETH is not set
  461 +# CONFIG_BLK_DEV_HD is not set
  462 +# CONFIG_MISC_DEVICES is not set
  463 +CONFIG_HAVE_IDE=y
  464 +# CONFIG_IDE is not set
  465 +
  466 +#
  467 +# SCSI device support
  468 +#
  469 +# CONFIG_RAID_ATTRS is not set
  470 +CONFIG_SCSI=y
  471 +CONFIG_SCSI_DMA=y
  472 +# CONFIG_SCSI_TGT is not set
  473 +# CONFIG_SCSI_NETLINK is not set
  474 +CONFIG_SCSI_PROC_FS=y
  475 +
  476 +#
  477 +# SCSI support type (disk, tape, CD-ROM)
  478 +#
  479 +CONFIG_BLK_DEV_SD=y
  480 +# CONFIG_CHR_DEV_ST is not set
  481 +# CONFIG_CHR_DEV_OSST is not set
  482 +# CONFIG_BLK_DEV_SR is not set
  483 +# CONFIG_CHR_DEV_SG is not set
  484 +# CONFIG_CHR_DEV_SCH is not set
  485 +
  486 +#
  487 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
  488 +#
  489 +# CONFIG_SCSI_MULTI_LUN is not set
  490 +# CONFIG_SCSI_CONSTANTS is not set
  491 +# CONFIG_SCSI_LOGGING is not set
  492 +# CONFIG_SCSI_SCAN_ASYNC is not set
  493 +CONFIG_SCSI_WAIT_SCAN=m
  494 +
  495 +#
  496 +# SCSI Transports
  497 +#
  498 +# CONFIG_SCSI_SPI_ATTRS is not set
  499 +# CONFIG_SCSI_FC_ATTRS is not set
  500 +# CONFIG_SCSI_ISCSI_ATTRS is not set
  501 +# CONFIG_SCSI_SAS_LIBSAS is not set
  502 +# CONFIG_SCSI_SRP_ATTRS is not set
  503 +# CONFIG_SCSI_LOWLEVEL is not set
  504 +# CONFIG_SCSI_DH is not set
  505 +CONFIG_ATA=y
  506 +# CONFIG_ATA_NONSTANDARD is not set
  507 +CONFIG_SATA_PMP=y
  508 +CONFIG_ATA_SFF=y
  509 +# CONFIG_SATA_MV is not set
  510 +# CONFIG_PATA_PLATFORM is not set
  511 +# CONFIG_MD is not set
  512 +CONFIG_NETDEVICES=y
  513 +# CONFIG_DUMMY is not set
  514 +# CONFIG_BONDING is not set
  515 +# CONFIG_MACVLAN is not set
  516 +# CONFIG_EQUALIZER is not set
  517 +# CONFIG_TUN is not set
  518 +# CONFIG_VETH is not set
  519 +# CONFIG_PHYLIB is not set
  520 +CONFIG_NET_ETHERNET=y
  521 +CONFIG_MII=y
  522 +# CONFIG_AX88796 is not set
  523 +# CONFIG_DM9000 is not set
  524 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
  525 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
  526 +# CONFIG_IBM_NEW_EMAC_TAH is not set
  527 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
  528 +# CONFIG_B44 is not set
  529 +# CONFIG_NETDEV_1000 is not set
  530 +# CONFIG_NETDEV_10000 is not set
  531 +
  532 +#
  533 +# Wireless LAN
  534 +#
  535 +# CONFIG_WLAN_PRE80211 is not set
  536 +# CONFIG_WLAN_80211 is not set
  537 +# CONFIG_IWLWIFI_LEDS is not set
  538 +# CONFIG_WAN is not set
  539 +# CONFIG_PPP is not set
  540 +# CONFIG_SLIP is not set
  541 +# CONFIG_NETCONSOLE is not set
  542 +# CONFIG_NETPOLL is not set
  543 +# CONFIG_NET_POLL_CONTROLLER is not set
  544 +# CONFIG_ISDN is not set
  545 +# CONFIG_PHONE is not set
  546 +
  547 +#
  548 +# Input device support
  549 +#
  550 +CONFIG_INPUT=y
  551 +# CONFIG_INPUT_FF_MEMLESS is not set
  552 +# CONFIG_INPUT_POLLDEV is not set
  553 +
  554 +#
  555 +# Userland interfaces
  556 +#
  557 +# CONFIG_INPUT_MOUSEDEV is not set
  558 +# CONFIG_INPUT_JOYDEV is not set
  559 +CONFIG_INPUT_EVDEV=m
  560 +CONFIG_INPUT_EVBUG=m
  561 +
  562 +#
  563 +# Input Device Drivers
  564 +#
  565 +# CONFIG_INPUT_KEYBOARD is not set
  566 +# CONFIG_INPUT_MOUSE is not set
  567 +# CONFIG_INPUT_JOYSTICK is not set
  568 +# CONFIG_INPUT_TABLET is not set
  569 +# CONFIG_INPUT_TOUCHSCREEN is not set
  570 +# CONFIG_INPUT_MISC is not set
  571 +
  572 +#
  573 +# Hardware I/O ports
  574 +#
  575 +CONFIG_SERIO=y
  576 +# CONFIG_SERIO_I8042 is not set
  577 +CONFIG_SERIO_SERPORT=y
  578 +# CONFIG_SERIO_LIBPS2 is not set
  579 +# CONFIG_SERIO_RAW is not set
  580 +# CONFIG_GAMEPORT is not set
  581 +
  582 +#
  583 +# Character devices
  584 +#
  585 +CONFIG_VT=y
  586 +CONFIG_CONSOLE_TRANSLATIONS=y
  587 +# CONFIG_VT_CONSOLE is not set
  588 +CONFIG_HW_CONSOLE=y
  589 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
  590 +CONFIG_DEVKMEM=y
  591 +# CONFIG_SERIAL_NONSTANDARD is not set
  592 +
  593 +#
  594 +# Serial drivers
  595 +#
  596 +# CONFIG_SERIAL_8250 is not set
  597 +
  598 +#
  599 +# Non-8250 serial port support
  600 +#
  601 +CONFIG_SERIAL_PNX8XXX=y
  602 +CONFIG_SERIAL_PNX8XXX_CONSOLE=y
  603 +CONFIG_SERIAL_CORE=y
  604 +CONFIG_SERIAL_CORE_CONSOLE=y
  605 +CONFIG_UNIX98_PTYS=y
  606 +# CONFIG_LEGACY_PTYS is not set
  607 +# CONFIG_IPMI_HANDLER is not set
  608 +CONFIG_HW_RANDOM=y
  609 +# CONFIG_R3964 is not set
  610 +# CONFIG_RAW_DRIVER is not set
  611 +# CONFIG_TCG_TPM is not set
  612 +CONFIG_I2C=y
  613 +CONFIG_I2C_BOARDINFO=y
  614 +CONFIG_I2C_CHARDEV=y
  615 +
  616 +#
  617 +# I2C Hardware Bus support
  618 +#
  619 +
  620 +#
  621 +# I2C system bus drivers (mostly embedded / system-on-chip)
  622 +#
  623 +# CONFIG_I2C_GPIO is not set
  624 +# CONFIG_I2C_OCORES is not set
  625 +# CONFIG_I2C_SIMTEC is not set
  626 +
  627 +#
  628 +# External I2C/SMBus adapter drivers
  629 +#
  630 +# CONFIG_I2C_PARPORT_LIGHT is not set
  631 +# CONFIG_I2C_TAOS_EVM is not set
  632 +
  633 +#
  634 +# Other I2C/SMBus bus drivers
  635 +#
  636 +# CONFIG_I2C_PCA_PLATFORM is not set
  637 +# CONFIG_I2C_STUB is not set
  638 +
  639 +#
  640 +# Miscellaneous I2C Chip support
  641 +#
  642 +# CONFIG_DS1682 is not set
  643 +# CONFIG_AT24 is not set
  644 +# CONFIG_SENSORS_EEPROM is not set
  645 +# CONFIG_SENSORS_PCF8574 is not set
  646 +# CONFIG_PCF8575 is not set
  647 +# CONFIG_SENSORS_PCA9539 is not set
  648 +# CONFIG_SENSORS_PCF8591 is not set
  649 +# CONFIG_SENSORS_MAX6875 is not set
  650 +# CONFIG_SENSORS_TSL2550 is not set
  651 +# CONFIG_I2C_DEBUG_CORE is not set
  652 +# CONFIG_I2C_DEBUG_ALGO is not set
  653 +# CONFIG_I2C_DEBUG_BUS is not set
  654 +# CONFIG_I2C_DEBUG_CHIP is not set
  655 +# CONFIG_SPI is not set
  656 +# CONFIG_W1 is not set
  657 +# CONFIG_POWER_SUPPLY is not set
  658 +# CONFIG_HWMON is not set
  659 +# CONFIG_THERMAL is not set
  660 +# CONFIG_THERMAL_HWMON is not set
  661 +# CONFIG_WATCHDOG is not set
  662 +
  663 +#
  664 +# Sonics Silicon Backplane
  665 +#
  666 +CONFIG_SSB_POSSIBLE=y
  667 +# CONFIG_SSB is not set
  668 +
  669 +#
  670 +# Multifunction device drivers
  671 +#
  672 +# CONFIG_MFD_CORE is not set
  673 +# CONFIG_MFD_SM501 is not set
  674 +# CONFIG_HTC_PASIC3 is not set
  675 +
  676 +#
  677 +# Multimedia devices
  678 +#
  679 +
  680 +#
  681 +# Multimedia core support
  682 +#
  683 +# CONFIG_VIDEO_DEV is not set
  684 +CONFIG_DVB_CORE=y
  685 +CONFIG_VIDEO_MEDIA=y
  686 +
  687 +#
  688 +# Multimedia drivers
  689 +#
  690 +# CONFIG_MEDIA_ATTACH is not set
  691 +CONFIG_MEDIA_TUNER=y
  692 +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
  693 +CONFIG_MEDIA_TUNER_SIMPLE=y
  694 +CONFIG_MEDIA_TUNER_TDA8290=y
  695 +CONFIG_MEDIA_TUNER_TDA9887=y
  696 +CONFIG_MEDIA_TUNER_TEA5761=y
  697 +CONFIG_MEDIA_TUNER_TEA5767=y
  698 +CONFIG_MEDIA_TUNER_MT20XX=y
  699 +CONFIG_MEDIA_TUNER_XC2028=y
  700 +CONFIG_MEDIA_TUNER_XC5000=y
  701 +CONFIG_DVB_CAPTURE_DRIVERS=y
  702 +# CONFIG_TTPCI_EEPROM is not set
  703 +# CONFIG_DVB_B2C2_FLEXCOP is not set
  704 +
  705 +#
  706 +# Supported DVB Frontends
  707 +#
  708 +
  709 +#
  710 +# Customise DVB Frontends
  711 +#
  712 +# CONFIG_DVB_FE_CUSTOMISE is not set
  713 +
  714 +#
  715 +# DVB-S (satellite) frontends
  716 +#
  717 +# CONFIG_DVB_CX24110 is not set
  718 +# CONFIG_DVB_CX24123 is not set
  719 +# CONFIG_DVB_MT312 is not set
  720 +# CONFIG_DVB_S5H1420 is not set
  721 +# CONFIG_DVB_STV0299 is not set
  722 +# CONFIG_DVB_TDA8083 is not set
  723 +# CONFIG_DVB_TDA10086 is not set
  724 +# CONFIG_DVB_VES1X93 is not set
  725 +# CONFIG_DVB_TUNER_ITD1000 is not set
  726 +# CONFIG_DVB_TDA826X is not set
  727 +# CONFIG_DVB_TUA6100 is not set
  728 +
  729 +#
  730 +# DVB-T (terrestrial) frontends
  731 +#
  732 +# CONFIG_DVB_SP8870 is not set
  733 +# CONFIG_DVB_SP887X is not set
  734 +# CONFIG_DVB_CX22700 is not set
  735 +# CONFIG_DVB_CX22702 is not set
  736 +# CONFIG_DVB_DRX397XD is not set
  737 +# CONFIG_DVB_L64781 is not set
  738 +CONFIG_DVB_TDA1004X=y
  739 +# CONFIG_DVB_NXT6000 is not set
  740 +# CONFIG_DVB_MT352 is not set
  741 +# CONFIG_DVB_ZL10353 is not set
  742 +# CONFIG_DVB_DIB3000MB is not set
  743 +# CONFIG_DVB_DIB3000MC is not set
  744 +# CONFIG_DVB_DIB7000M is not set
  745 +# CONFIG_DVB_DIB7000P is not set
  746 +# CONFIG_DVB_TDA10048 is not set
  747 +
  748 +#
  749 +# DVB-C (cable) frontends
  750 +#
  751 +# CONFIG_DVB_VES1820 is not set
  752 +# CONFIG_DVB_TDA10021 is not set
  753 +# CONFIG_DVB_TDA10023 is not set
  754 +# CONFIG_DVB_STV0297 is not set
  755 +
  756 +#
  757 +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
  758 +#
  759 +# CONFIG_DVB_NXT200X is not set
  760 +# CONFIG_DVB_OR51211 is not set
  761 +# CONFIG_DVB_OR51132 is not set
  762 +# CONFIG_DVB_BCM3510 is not set
  763 +# CONFIG_DVB_LGDT330X is not set
  764 +# CONFIG_DVB_S5H1409 is not set
  765 +# CONFIG_DVB_AU8522 is not set
  766 +# CONFIG_DVB_S5H1411 is not set
  767 +
  768 +#
  769 +# Digital terrestrial only tuners/PLL
  770 +#
  771 +# CONFIG_DVB_PLL is not set
  772 +# CONFIG_DVB_TUNER_DIB0070 is not set
  773 +
  774 +#
  775 +# SEC control devices for DVB-S
  776 +#
  777 +# CONFIG_DVB_LNBP21 is not set
  778 +# CONFIG_DVB_ISL6405 is not set
  779 +# CONFIG_DVB_ISL6421 is not set
  780 +# CONFIG_DAB is not set
  781 +
  782 +#
  783 +# Graphics support
  784 +#
  785 +# CONFIG_VGASTATE is not set
  786 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
  787 +CONFIG_FB=y
  788 +# CONFIG_FIRMWARE_EDID is not set
  789 +# CONFIG_FB_DDC is not set
  790 +# CONFIG_FB_CFB_FILLRECT is not set
  791 +# CONFIG_FB_CFB_COPYAREA is not set
  792 +# CONFIG_FB_CFB_IMAGEBLIT is not set
  793 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
  794 +# CONFIG_FB_SYS_FILLRECT is not set
  795 +# CONFIG_FB_SYS_COPYAREA is not set
  796 +# CONFIG_FB_SYS_IMAGEBLIT is not set
  797 +# CONFIG_FB_FOREIGN_ENDIAN is not set
  798 +# CONFIG_FB_SYS_FOPS is not set
  799 +# CONFIG_FB_SVGALIB is not set
  800 +# CONFIG_FB_MACMODES is not set
  801 +# CONFIG_FB_BACKLIGHT is not set
  802 +# CONFIG_FB_MODE_HELPERS is not set
  803 +# CONFIG_FB_TILEBLITTING is not set
  804 +
  805 +#
  806 +# Frame buffer hardware drivers
  807 +#
  808 +# CONFIG_FB_S1D13XXX is not set
  809 +# CONFIG_FB_VIRTUAL is not set
  810 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
  811 +
  812 +#
  813 +# Display device support
  814 +#
  815 +# CONFIG_DISPLAY_SUPPORT is not set
  816 +
  817 +#
  818 +# Console display driver support
  819 +#
  820 +# CONFIG_VGA_CONSOLE is not set
  821 +CONFIG_DUMMY_CONSOLE=y
  822 +# CONFIG_FRAMEBUFFER_CONSOLE is not set
  823 +# CONFIG_LOGO is not set
  824 +CONFIG_SOUND=m
  825 +CONFIG_SND=m
  826 +CONFIG_SND_TIMER=m
  827 +CONFIG_SND_PCM=m
  828 +CONFIG_SND_SEQUENCER=m
  829 +# CONFIG_SND_SEQ_DUMMY is not set
  830 +CONFIG_SND_OSSEMUL=y
  831 +CONFIG_SND_MIXER_OSS=m
  832 +CONFIG_SND_PCM_OSS=m
  833 +CONFIG_SND_PCM_OSS_PLUGINS=y
  834 +CONFIG_SND_SEQUENCER_OSS=y
  835 +# CONFIG_SND_DYNAMIC_MINORS is not set
  836 +CONFIG_SND_SUPPORT_OLD_API=y
  837 +CONFIG_SND_VERBOSE_PROCFS=y
  838 +CONFIG_SND_VERBOSE_PRINTK=y
  839 +CONFIG_SND_DEBUG=y
  840 +# CONFIG_SND_DEBUG_VERBOSE is not set
  841 +# CONFIG_SND_PCM_XRUN_DEBUG is not set
  842 +CONFIG_SND_DRIVERS=y
  843 +# CONFIG_SND_DUMMY is not set
  844 +# CONFIG_SND_VIRMIDI is not set
  845 +# CONFIG_SND_MTPAV is not set
  846 +# CONFIG_SND_SERIAL_U16550 is not set
  847 +# CONFIG_SND_MPU401 is not set
  848 +CONFIG_SND_MIPS=y
  849 +# CONFIG_SND_SOC is not set
  850 +# CONFIG_SOUND_PRIME is not set
  851 +CONFIG_HID_SUPPORT=y
  852 +CONFIG_HID=y
  853 +# CONFIG_HID_DEBUG is not set
  854 +# CONFIG_HIDRAW is not set
  855 +CONFIG_USB_SUPPORT=y
  856 +# CONFIG_USB_ARCH_HAS_HCD is not set
  857 +# CONFIG_USB_ARCH_HAS_OHCI is not set
  858 +# CONFIG_USB_ARCH_HAS_EHCI is not set
  859 +# CONFIG_USB_OTG_WHITELIST is not set
  860 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
  861 +
  862 +#
  863 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
  864 +#
  865 +# CONFIG_USB_GADGET is not set
  866 +# CONFIG_MMC is not set
  867 +# CONFIG_MEMSTICK is not set
  868 +# CONFIG_NEW_LEDS is not set
  869 +# CONFIG_ACCESSIBILITY is not set
  870 +CONFIG_RTC_LIB=y
  871 +# CONFIG_RTC_CLASS is not set
  872 +# CONFIG_DMADEVICES is not set
  873 +# CONFIG_UIO is not set
  874 +
  875 +#
  876 +# File systems
  877 +#
  878 +CONFIG_EXT2_FS=m
  879 +# CONFIG_EXT2_FS_XATTR is not set
  880 +# CONFIG_EXT2_FS_XIP is not set
  881 +# CONFIG_EXT3_FS is not set
  882 +# CONFIG_EXT4DEV_FS is not set
  883 +# CONFIG_REISERFS_FS is not set
  884 +# CONFIG_JFS_FS is not set
  885 +# CONFIG_FS_POSIX_ACL is not set
  886 +# CONFIG_XFS_FS is not set
  887 +# CONFIG_OCFS2_FS is not set
  888 +# CONFIG_DNOTIFY is not set
  889 +CONFIG_INOTIFY=y
  890 +CONFIG_INOTIFY_USER=y
  891 +# CONFIG_QUOTA is not set
  892 +# CONFIG_AUTOFS_FS is not set
  893 +# CONFIG_AUTOFS4_FS is not set
  894 +# CONFIG_FUSE_FS is not set
  895 +
  896 +#
  897 +# CD-ROM/DVD Filesystems
  898 +#
  899 +# CONFIG_ISO9660_FS is not set
  900 +# CONFIG_UDF_FS is not set
  901 +
  902 +#
  903 +# DOS/FAT/NT Filesystems
  904 +#
  905 +CONFIG_FAT_FS=m
  906 +CONFIG_MSDOS_FS=m
  907 +CONFIG_VFAT_FS=m
  908 +CONFIG_FAT_DEFAULT_CODEPAGE=437
  909 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
  910 +# CONFIG_NTFS_FS is not set
  911 +
  912 +#
  913 +# Pseudo filesystems
  914 +#
  915 +CONFIG_PROC_FS=y
  916 +# CONFIG_PROC_KCORE is not set
  917 +CONFIG_PROC_SYSCTL=y
  918 +CONFIG_SYSFS=y
  919 +CONFIG_TMPFS=y
  920 +# CONFIG_TMPFS_POSIX_ACL is not set
  921 +# CONFIG_HUGETLB_PAGE is not set
  922 +# CONFIG_CONFIGFS_FS is not set
  923 +
  924 +#
  925 +# Miscellaneous filesystems
  926 +#
  927 +# CONFIG_ADFS_FS is not set
  928 +# CONFIG_AFFS_FS is not set
  929 +# CONFIG_HFS_FS is not set
  930 +# CONFIG_HFSPLUS_FS is not set
  931 +# CONFIG_BEFS_FS is not set
  932 +# CONFIG_BFS_FS is not set
  933 +# CONFIG_EFS_FS is not set
  934 +CONFIG_JFFS2_FS=y
  935 +CONFIG_JFFS2_FS_DEBUG=0
  936 +CONFIG_JFFS2_FS_WRITEBUFFER=y
  937 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
  938 +# CONFIG_JFFS2_SUMMARY is not set
  939 +# CONFIG_JFFS2_FS_XATTR is not set
  940 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
  941 +CONFIG_JFFS2_ZLIB=y
  942 +# CONFIG_JFFS2_LZO is not set
  943 +CONFIG_JFFS2_RTIME=y
  944 +# CONFIG_JFFS2_RUBIN is not set
  945 +CONFIG_CRAMFS=y
  946 +# CONFIG_VXFS_FS is not set
  947 +# CONFIG_MINIX_FS is not set
  948 +# CONFIG_HPFS_FS is not set
  949 +# CONFIG_QNX4FS_FS is not set
  950 +# CONFIG_ROMFS_FS is not set
  951 +# CONFIG_SYSV_FS is not set
  952 +# CONFIG_UFS_FS is not set
  953 +CONFIG_NETWORK_FILESYSTEMS=y
  954 +CONFIG_NFS_FS=y
  955 +CONFIG_NFS_V3=y
  956 +# CONFIG_NFS_V3_ACL is not set
  957 +# CONFIG_NFS_V4 is not set
  958 +CONFIG_ROOT_NFS=y
  959 +CONFIG_NFSD=m
  960 +CONFIG_NFSD_V3=y
  961 +# CONFIG_NFSD_V3_ACL is not set
  962 +# CONFIG_NFSD_V4 is not set
  963 +CONFIG_LOCKD=y
  964 +CONFIG_LOCKD_V4=y
  965 +CONFIG_EXPORTFS=m
  966 +CONFIG_NFS_COMMON=y
  967 +CONFIG_SUNRPC=y
  968 +# CONFIG_RPCSEC_GSS_KRB5 is not set
  969 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
  970 +# CONFIG_SMB_FS is not set
  971 +# CONFIG_CIFS is not set
  972 +# CONFIG_NCP_FS is not set
  973 +# CONFIG_CODA_FS is not set
  974 +# CONFIG_AFS_FS is not set
  975 +
  976 +#
  977 +# Partition Types
  978 +#
  979 +# CONFIG_PARTITION_ADVANCED is not set
  980 +CONFIG_MSDOS_PARTITION=y
  981 +CONFIG_NLS=y
  982 +CONFIG_NLS_DEFAULT="iso8859-1"
  983 +CONFIG_NLS_CODEPAGE_437=m
  984 +# CONFIG_NLS_CODEPAGE_737 is not set
  985 +# CONFIG_NLS_CODEPAGE_775 is not set
  986 +CONFIG_NLS_CODEPAGE_850=m
  987 +# CONFIG_NLS_CODEPAGE_852 is not set
  988 +# CONFIG_NLS_CODEPAGE_855 is not set
  989 +# CONFIG_NLS_CODEPAGE_857 is not set
  990 +# CONFIG_NLS_CODEPAGE_860 is not set
  991 +# CONFIG_NLS_CODEPAGE_861 is not set
  992 +# CONFIG_NLS_CODEPAGE_862 is not set
  993 +# CONFIG_NLS_CODEPAGE_863 is not set
  994 +# CONFIG_NLS_CODEPAGE_864 is not set
  995 +# CONFIG_NLS_CODEPAGE_865 is not set
  996 +# CONFIG_NLS_CODEPAGE_866 is not set
  997 +# CONFIG_NLS_CODEPAGE_869 is not set
  998 +# CONFIG_NLS_CODEPAGE_936 is not set
  999 +# CONFIG_NLS_CODEPAGE_950 is not set
  1000 +CONFIG_NLS_CODEPAGE_932=m
  1001 +# CONFIG_NLS_CODEPAGE_949 is not set
  1002 +# CONFIG_NLS_CODEPAGE_874 is not set
  1003 +# CONFIG_NLS_ISO8859_8 is not set
  1004 +# CONFIG_NLS_CODEPAGE_1250 is not set
  1005 +# CONFIG_NLS_CODEPAGE_1251 is not set
  1006 +CONFIG_NLS_ASCII=m
  1007 +CONFIG_NLS_ISO8859_1=m
  1008 +# CONFIG_NLS_ISO8859_2 is not set
  1009 +# CONFIG_NLS_ISO8859_3 is not set
  1010 +# CONFIG_NLS_ISO8859_4 is not set
  1011 +# CONFIG_NLS_ISO8859_5 is not set
  1012 +# CONFIG_NLS_ISO8859_6 is not set
  1013 +# CONFIG_NLS_ISO8859_7 is not set
  1014 +# CONFIG_NLS_ISO8859_9 is not set
  1015 +# CONFIG_NLS_ISO8859_13 is not set
  1016 +# CONFIG_NLS_ISO8859_14 is not set
  1017 +CONFIG_NLS_ISO8859_15=m
  1018 +# CONFIG_NLS_KOI8_R is not set
  1019 +# CONFIG_NLS_KOI8_U is not set
  1020 +CONFIG_NLS_UTF8=m
  1021 +# CONFIG_DLM is not set
  1022 +
  1023 +#
  1024 +# Kernel hacking
  1025 +#
  1026 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
  1027 +# CONFIG_PRINTK_TIME is not set
  1028 +CONFIG_ENABLE_WARN_DEPRECATED=y
  1029 +CONFIG_ENABLE_MUST_CHECK=y
  1030 +CONFIG_FRAME_WARN=1024
  1031 +# CONFIG_MAGIC_SYSRQ is not set
  1032 +# CONFIG_UNUSED_SYMBOLS is not set
  1033 +# CONFIG_DEBUG_FS is not set
  1034 +# CONFIG_HEADERS_CHECK is not set
  1035 +# CONFIG_DEBUG_KERNEL is not set
  1036 +# CONFIG_SAMPLES is not set
  1037 +# CONFIG_KERNEL_TESTS is not set
  1038 +CONFIG_CMDLINE=""
  1039 +
  1040 +#
  1041 +# Security options
  1042 +#
  1043 +# CONFIG_KEYS is not set
  1044 +# CONFIG_SECURITY is not set
  1045 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
  1046 +CONFIG_CRYPTO=y
  1047 +
  1048 +#
  1049 +# Crypto core or helper
  1050 +#
  1051 +CONFIG_CRYPTO_ALGAPI=y
  1052 +CONFIG_CRYPTO_HASH=y
  1053 +CONFIG_CRYPTO_MANAGER=y
  1054 +# CONFIG_CRYPTO_GF128MUL is not set
  1055 +# CONFIG_CRYPTO_NULL is not set
  1056 +# CONFIG_CRYPTO_CRYPTD is not set
  1057 +# CONFIG_CRYPTO_AUTHENC is not set
  1058 +# CONFIG_CRYPTO_TEST is not set
  1059 +
  1060 +#
  1061 +# Authenticated Encryption with Associated Data
  1062 +#
  1063 +# CONFIG_CRYPTO_CCM is not set
  1064 +# CONFIG_CRYPTO_GCM is not set
  1065 +# CONFIG_CRYPTO_SEQIV is not set
  1066 +
  1067 +#
  1068 +# Block modes
  1069 +#
  1070 +# CONFIG_CRYPTO_CBC is not set
  1071 +# CONFIG_CRYPTO_CTR is not set
  1072 +# CONFIG_CRYPTO_CTS is not set
  1073 +# CONFIG_CRYPTO_ECB is not set
  1074 +# CONFIG_CRYPTO_LRW is not set
  1075 +# CONFIG_CRYPTO_PCBC is not set
  1076 +# CONFIG_CRYPTO_XTS is not set
  1077 +
  1078 +#
  1079 +# Hash modes
  1080 +#
  1081 +CONFIG_CRYPTO_HMAC=y
  1082 +# CONFIG_CRYPTO_XCBC is not set
  1083 +
  1084 +#
  1085 +# Digest
  1086 +#
  1087 +# CONFIG_CRYPTO_CRC32C is not set
  1088 +# CONFIG_CRYPTO_MD4 is not set
  1089 +CONFIG_CRYPTO_MD5=y
  1090 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
  1091 +# CONFIG_CRYPTO_RMD128 is not set
  1092 +# CONFIG_CRYPTO_RMD160 is not set
  1093 +# CONFIG_CRYPTO_RMD256 is not set
  1094 +# CONFIG_CRYPTO_RMD320 is not set
  1095 +CONFIG_CRYPTO_SHA1=y
  1096 +# CONFIG_CRYPTO_SHA256 is not set
  1097 +# CONFIG_CRYPTO_SHA512 is not set
  1098 +# CONFIG_CRYPTO_TGR192 is not set
  1099 +# CONFIG_CRYPTO_WP512 is not set
  1100 +
  1101 +#
  1102 +# Ciphers
  1103 +#
  1104 +# CONFIG_CRYPTO_AES is not set
  1105 +# CONFIG_CRYPTO_ANUBIS is not set
  1106 +# CONFIG_CRYPTO_ARC4 is not set
  1107 +# CONFIG_CRYPTO_BLOWFISH is not set
  1108 +# CONFIG_CRYPTO_CAMELLIA is not set
  1109 +# CONFIG_CRYPTO_CAST5 is not set
  1110 +# CONFIG_CRYPTO_CAST6 is not set
  1111 +# CONFIG_CRYPTO_DES is not set
  1112 +# CONFIG_CRYPTO_FCRYPT is not set
  1113 +# CONFIG_CRYPTO_KHAZAD is not set
  1114 +# CONFIG_CRYPTO_SALSA20 is not set
  1115 +# CONFIG_CRYPTO_SEED is not set
  1116 +# CONFIG_CRYPTO_SERPENT is not set
  1117 +# CONFIG_CRYPTO_TEA is not set
  1118 +# CONFIG_CRYPTO_TWOFISH is not set
  1119 +
  1120 +#
  1121 +# Compression
  1122 +#
  1123 +# CONFIG_CRYPTO_DEFLATE is not set
  1124 +# CONFIG_CRYPTO_LZO is not set
  1125 +
  1126 +#
  1127 +# Random Number Generation
  1128 +#
  1129 +# CONFIG_CRYPTO_PRNG is not set
  1130 +CONFIG_CRYPTO_HW=y
  1131 +
  1132 +#
  1133 +# Library routines
  1134 +#
  1135 +CONFIG_BITREVERSE=y
  1136 +# CONFIG_GENERIC_FIND_FIRST_BIT is not set
  1137 +# CONFIG_CRC_CCITT is not set
  1138 +# CONFIG_CRC16 is not set
  1139 +# CONFIG_CRC_T10DIF is not set
  1140 +# CONFIG_CRC_ITU_T is not set
  1141 +CONFIG_CRC32=y
  1142 +# CONFIG_CRC7 is not set
  1143 +# CONFIG_LIBCRC32C is not set
  1144 +CONFIG_ZLIB_INFLATE=y
  1145 +CONFIG_ZLIB_DEFLATE=y
  1146 +CONFIG_PLIST=y
  1147 +CONFIG_HAS_IOMEM=y
  1148 +CONFIG_HAS_IOPORT=y
  1149 +CONFIG_HAS_DMA=y
arch/mips/include/asm/mach-pnx833x/gpio.h
Diff comments   View file @ edb6310
  1 +/*
  2 + * gpio.h: GPIO Support for PNX833X.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * This program is free software; you can redistribute it and/or modify
  9 + * it under the terms of the GNU General Public License as published by
  10 + * the Free Software Foundation; either version 2 of the License, or
  11 + * (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 + */
  22 +#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
  23 +#define __ASM_MIPS_MACH_PNX833X_GPIO_H
  24 +
  25 +/* BIG FAT WARNING: races danger!
  26 + No protections exist here. Current users are only early init code,
  27 + when locking is not needed because no cuncurency yet exists there,
  28 + and GPIO IRQ dispatcher, which does locking.
  29 + However, if many uses will ever happen, proper locking will be needed
  30 + - including locking between different uses
  31 +*/
  32 +
  33 +#include "pnx833x.h"
  34 +
  35 +#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
  36 +#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
  37 +
  38 +/* Initialize GPIO to a known state */
  39 +static inline void pnx833x_gpio_init(void)
  40 +{
  41 + PNX833X_PIO_DIR = 0;
  42 + PNX833X_PIO_DIR2 = 0;
  43 + PNX833X_PIO_SEL = 0;
  44 + PNX833X_PIO_SEL2 = 0;
  45 + PNX833X_PIO_INT_EDGE = 0;
  46 + PNX833X_PIO_INT_HI = 0;
  47 + PNX833X_PIO_INT_LO = 0;
  48 +
  49 + /* clear any GPIO interrupt requests */
  50 + PNX833X_PIO_INT_CLEAR = 0xffff;
  51 + PNX833X_PIO_INT_CLEAR = 0;
  52 + PNX833X_PIO_INT_ENABLE = 0;
  53 +}
  54 +
  55 +/* Select GPIO direction for a pin */
  56 +static inline void pnx833x_gpio_select_input(unsigned int pin)
  57 +{
  58 + if (pin < 32)
  59 + CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
  60 + else
  61 + CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  62 +}
  63 +static inline void pnx833x_gpio_select_output(unsigned int pin)
  64 +{
  65 + if (pin < 32)
  66 + SET_REG_BIT(PNX833X_PIO_DIR, pin);
  67 + else
  68 + SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  69 +}
  70 +
  71 +/* Select GPIO or alternate function for a pin */
  72 +static inline void pnx833x_gpio_select_function_io(unsigned int pin)
  73 +{
  74 + if (pin < 32)
  75 + CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
  76 + else
  77 + CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  78 +}
  79 +static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
  80 +{
  81 + if (pin < 32)
  82 + SET_REG_BIT(PNX833X_PIO_SEL, pin);
  83 + else
  84 + SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  85 +}
  86 +
  87 +/* Read GPIO pin */
  88 +static inline int pnx833x_gpio_read(unsigned int pin)
  89 +{
  90 + if (pin < 32)
  91 + return (PNX833X_PIO_IN >> pin) & 1;
  92 + else
  93 + return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
  94 +}
  95 +
  96 +/* Write GPIO pin */
  97 +static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
  98 +{
  99 + if (pin < 32) {
  100 + if (val)
  101 + SET_REG_BIT(PNX833X_PIO_OUT, pin);
  102 + else
  103 + CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
  104 + } else {
  105 + if (val)
  106 + SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
  107 + else
  108 + CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
  109 + }
  110 +}
  111 +
  112 +/* Configure GPIO interrupt */
  113 +#define GPIO_INT_NONE 0
  114 +#define GPIO_INT_LEVEL_LOW 1
  115 +#define GPIO_INT_LEVEL_HIGH 2
  116 +#define GPIO_INT_EDGE_RISING 3
  117 +#define GPIO_INT_EDGE_FALLING 4
  118 +#define GPIO_INT_EDGE_BOTH 5
  119 +static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
  120 +{
  121 + switch (when) {
  122 + case GPIO_INT_LEVEL_LOW:
  123 + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  124 + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
  125 + SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
  126 + break;
  127 + case GPIO_INT_LEVEL_HIGH:
  128 + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  129 + SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
  130 + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
  131 + break;
  132 + case GPIO_INT_EDGE_RISING:
  133 + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  134 + SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
  135 + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
  136 + break;
  137 + case GPIO_INT_EDGE_FALLING:
  138 + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  139 + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
  140 + SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
  141 + break;
  142 + case GPIO_INT_EDGE_BOTH:
  143 + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  144 + SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
  145 + SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
  146 + break;
  147 + default:
  148 + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  149 + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
  150 + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
  151 + break;
  152 + }
  153 +}
  154 +
  155 +/* Enable/disable GPIO interrupt */
  156 +static inline void pnx833x_gpio_enable_irq(unsigned int pin)
  157 +{
  158 + SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
  159 +}
  160 +static inline void pnx833x_gpio_disable_irq(unsigned int pin)
  161 +{
  162 + CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
  163 +}
  164 +
  165 +/* Clear GPIO interrupt request */
  166 +static inline void pnx833x_gpio_clear_irq(unsigned int pin)
  167 +{
  168 + SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
  169 + CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
  170 +}
  171 +
  172 +#endif
arch/mips/include/asm/mach-pnx833x/irq-mapping.h
Diff comments   View file @ edb6310
  1 +
  2 +/*
  3 + * irq.h: IRQ mappings for PNX833X.
  4 + *
  5 + * Copyright 2008 NXP Semiconductors
  6 + * Chris Steel <chris.steel@nxp.com>
  7 + * Daniel Laird <daniel.j.laird@nxp.com>
  8 + *
  9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License as published by
  11 + * the Free Software Foundation; either version 2 of the License, or
  12 + * (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 + */
  23 +
  24 +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
  25 +#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
  26 +/*
  27 + * The "IRQ numbers" are completely virtual.
  28 + *
  29 + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
  30 + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
  31 + * numbers 49..64 for (virtual) GPIO interrupts.
  32 + *
  33 + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
  34 + * connected to PIC, which uses core hardware interrupt 2, and also
  35 + * a timer interrupt through hardware interrupt 5.
  36 + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
  37 + * numbers 65..80 for (virtual) GPIO interrupts.
  38 + *
  39 + */
  40 +#include <irq.h>
  41 +
  42 +#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
  43 +
  44 +/* Interrupts supported by PIC */
  45 +#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1)
  46 +#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2)
  47 +#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3)
  48 +#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4)
  49 +#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5)
  50 +#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6)
  51 +#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7)
  52 +#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8)
  53 +#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9)
  54 +#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10)
  55 +#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11)
  56 +#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12)
  57 +#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13)
  58 +#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13)
  59 +#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14)
  60 +#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15)
  61 +#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16)
  62 +#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17)
  63 +#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18)
  64 +#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19)
  65 +#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20)
  66 +#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21)
  67 +#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22)
  68 +#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23)
  69 +#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24)
  70 +#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25)
  71 +#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26)
  72 +#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27)
  73 +#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28)
  74 +#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29)
  75 +#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30)
  76 +#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31)
  77 +#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32)
  78 +#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33)
  79 +#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34)
  80 +#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35)
  81 +#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36)
  82 +
  83 +#if defined(CONFIG_SOC_PNX8335)
  84 +#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37)
  85 +#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38)
  86 +#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39)
  87 +#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40)
  88 +#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41)
  89 +#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42)
  90 +#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43)
  91 +#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44)
  92 +#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45)
  93 +#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46)
  94 +#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47)
  95 +#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48)
  96 +#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49)
  97 +#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50)
  98 +#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51)
  99 +#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52)
  100 +#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53)
  101 +#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54)
  102 +#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55)
  103 +#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56)
  104 +#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57)
  105 +#endif
  106 +
  107 +/* GPIO interrupts */
  108 +#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0)
  109 +#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1)
  110 +#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2)
  111 +#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3)
  112 +#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4)
  113 +#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5)
  114 +#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6)
  115 +#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7)
  116 +#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8)
  117 +#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9)
  118 +#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10)
  119 +#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11)
  120 +#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12)
  121 +#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13)
  122 +#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14)
  123 +#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
  124 +
  125 +#endif
arch/mips/include/asm/mach-pnx833x/irq.h
Diff comments   View file @ edb6310
  1 +/*
  2 + * irq.h: IRQ mappings for PNX833X.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * This program is free software; you can redistribute it and/or modify
  9 + * it under the terms of the GNU General Public License as published by
  10 + * the Free Software Foundation; either version 2 of the License, or
  11 + * (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 + */
  22 +
  23 +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
  24 +#define __ASM_MIPS_MACH_PNX833X_IRQ_H
  25 +/*
  26 + * The "IRQ numbers" are completely virtual.
  27 + *
  28 + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
  29 + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
  30 + * numbers 49..64 for (virtual) GPIO interrupts.
  31 + *
  32 + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
  33 + * connected to PIC, which uses core hardware interrupt 2, and also
  34 + * a timer interrupt through hardware interrupt 5.
  35 + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
  36 + * numbers 65..80 for (virtual) GPIO interrupts.
  37 + *
  38 + */
  39 +#if defined(CONFIG_SOC_PNX8335)
  40 + #define PNX833X_PIC_NUM_IRQ 58
  41 +#else
  42 + #define PNX833X_PIC_NUM_IRQ 37
  43 +#endif
  44 +
  45 +#define MIPS_CPU_NUM_IRQ 8
  46 +#define PNX833X_GPIO_NUM_IRQ 16
  47 +
  48 +#define MIPS_CPU_IRQ_BASE 0
  49 +#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
  50 +#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
  51 +#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
  52 +
  53 +#endif
arch/mips/include/asm/mach-pnx833x/pnx833x.h
Diff comments   View file @ edb6310
  1 +/*
  2 + * pnx833x.h: Register mappings for PNX833X.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * This program is free software; you can redistribute it and/or modify
  9 + * it under the terms of the GNU General Public License as published by
  10 + * the Free Software Foundation; either version 2 of the License, or
  11 + * (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 + */
  22 +#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
  23 +#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
  24 +
  25 +/* All regs are accessed in KSEG1 */
  26 +#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul)
  27 +
  28 +#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs)))
  29 +
  30 +/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
  31 +
  32 +/* Read access to multibit fields */
  33 +#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
  34 +#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
  35 +
  36 +/* Use PNX833X_FIELD to extract a field from val */
  37 +#define PNX_FIELD(cpu, val, reg, field) \
  38 + (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
  39 + PNX##cpu##_##reg##_##field##_SHIFT)
  40 +#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
  41 +#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
  42 +#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
  43 +
  44 +/* Use PNX833X_REGFIELD to extract a field from a register */
  45 +#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
  46 +#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
  47 +#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
  48 +
  49 +
  50 +#define PNX_WRITEFIELD(cpu, val, reg, field) \
  51 + (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
  52 + ((val) << PNX##cpu##_##reg##_##field##_SHIFT))
  53 +#define PNX833X_WRITEFIELD(val, reg, field) \
  54 + PNX_WRITEFIELD(833X, val, reg, field)
  55 +#define PNX8330_WRITEFIELD(val, reg, field) \
  56 + PNX_WRITEFIELD(8330, val, reg, field)
  57 +#define PNX8335_WRITEFIELD(val, reg, field) \
  58 + PNX_WRITEFIELD(8335, val, reg, field)
  59 +
  60 +
  61 +/* Macros to detect CPU type */
  62 +
  63 +#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC)
  64 +#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000
  65 +#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12
  66 +#define PNX8330_CONFIG_MODULE_MAJREV 4
  67 +#define PNX8335_CONFIG_MODULE_MAJREV 5
  68 +#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
  69 + PNX8330_CONFIG_MODULE_MAJREV)
  70 +#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
  71 + PNX8335_CONFIG_MODULE_MAJREV)
  72 +
  73 +
  74 +
  75 +#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004)
  76 +#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014)
  77 +
  78 +#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs))
  79 +#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0)
  80 +#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4)
  81 +#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */
  82 +#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3
  83 +#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq))
  84 +
  85 +#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
  86 +#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */
  87 +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */
  88 +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
  89 +
  90 +#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020)
  91 +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f
  92 +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0
  93 +
  94 +#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004)
  95 +#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */
  96 +
  97 +#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040)
  98 +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000
  99 +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19
  100 +
  101 +#define PNX833X_PIO_IN PNX833X_REG(0xF000)
  102 +#define PNX833X_PIO_OUT PNX833X_REG(0xF004)
  103 +#define PNX833X_PIO_DIR PNX833X_REG(0xF008)
  104 +#define PNX833X_PIO_SEL PNX833X_REG(0xF014)
  105 +#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020)
  106 +#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024)
  107 +#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028)
  108 +#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0)
  109 +#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4)
  110 +#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8)
  111 +#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C)
  112 +#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060)
  113 +#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064)
  114 +#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068)
  115 +
  116 +#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000)
  117 +#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF)
  118 +#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000)
  119 +#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF)
  120 +
  121 +#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000)
  122 +#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF)
  123 +
  124 +#define PNX833X_CONFIG_USB PNX833X_REG(0x7008)
  125 +
  126 +#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000)
  127 +#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF)
  128 +#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000)
  129 +#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF)
  130 +
  131 +#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000)
  132 +#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF)
  133 +#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC)
  134 +
  135 +#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
  136 +#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16
  137 +#define PNX833X_IDE_MODULE_ID_VALUE 0xA009
  138 +
  139 +
  140 +#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004)
  141 +#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008)
  142 +#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C)
  143 +#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010)
  144 +#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014)
  145 +#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018)
  146 +#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C)
  147 +#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020)
  148 +
  149 +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14)
  150 +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
  151 +
  152 +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
  153 +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7
  154 +
  155 +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9)
  156 +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9
  157 +
  158 +#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000)
  159 +
  160 +#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3)
  161 +#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3
  162 +
  163 +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
  164 +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2
  165 +
  166 +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
  167 +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1
  168 +
  169 +#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0)
  170 +#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0
  171 +
  172 +#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
  173 + (PNX833X_MIU_CONFIG_SPI = \
  174 + ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \
  175 + ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \
  176 + ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \
  177 + ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
  178 +
  179 +#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000)
  180 +#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF)
  181 +#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC)
  182 +
  183 +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
  184 +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16
  185 +#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902
  186 +
  187 + /* I/O location(gets remapped)*/
  188 +#define PNX8335_NAND_BASE 0x18000000
  189 +/* I/O location with CLE high */
  190 +#define PNX8335_NAND_CLE_MASK 0x00100000
  191 +/* I/O location with ALE high */
  192 +#define PNX8335_NAND_ALE_MASK 0x00010000
  193 +
  194 +#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000)
  195 +#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF)
  196 +#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC)
  197 +
  198 +#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
  199 +#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16
  200 +#define PNX8335_SATA_MODULE_ID_VALUE 0xA099
  201 +
  202 +#endif
arch/mips/include/asm/mach-pnx833x/war.h
Diff comments   View file @ edb6310
  1 +/*
  2 + * This file is subject to the terms and conditions of the GNU General Public
  3 + * License. See the file "COPYING" in the main directory of this archive
  4 + * for more details.
  5 + *
  6 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
  7 + */
  8 +#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
  9 +#define __ASM_MIPS_MACH_PNX833X_WAR_H
  10 +
  11 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
  12 +#define R4600_V1_HIT_CACHEOP_WAR 0
  13 +#define R4600_V2_HIT_CACHEOP_WAR 0
  14 +#define R5432_CP0_INTERRUPT_WAR 0
  15 +#define BCM1250_M3_WAR 0
  16 +#define SIBYTE_1956_WAR 0
  17 +#define MIPS4K_ICACHE_REFILL_WAR 0
  18 +#define MIPS_CACHE_SYNC_WAR 0
  19 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
  20 +#define RM9000_CDEX_SMP_WAR 0
  21 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
  22 +#define R10000_LLSC_WAR 0
  23 +#define MIPS34K_MISSED_ITLB_WAR 0
  24 +
  25 +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
arch/mips/nxp/pnx833x/common/Makefile
Diff comments   View file @ edb6310
  1 +obj-y := interrupts.o platform.o prom.o setup.o reset.o
  2 +
  3 +EXTRA_CFLAGS += -Werror
arch/mips/nxp/pnx833x/common/interrupts.c
Diff comments   View file @ edb6310
  1 +/*
  2 + * interrupts.c: Interrupt mappings for PNX833X.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * This program is free software; you can redistribute it and/or modify
  9 + * it under the terms of the GNU General Public License as published by
  10 + * the Free Software Foundation; either version 2 of the License, or
  11 + * (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 + */
  22 +#include <linux/kernel.h>
  23 +#include <linux/irq.h>
  24 +#include <linux/hardirq.h>
  25 +#include <linux/interrupt.h>
  26 +#include <asm/mipsregs.h>
  27 +#include <asm/irq_cpu.h>
  28 +#include <irq.h>
  29 +#include <irq-mapping.h>
  30 +#include <gpio.h>
  31 +
  32 +static int mips_cpu_timer_irq;
  33 +
  34 +static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
  35 +{
  36 + 0, /* unused */
  37 + 4, /* PNX833X_PIC_I2C0_INT 1 */
  38 + 4, /* PNX833X_PIC_I2C1_INT 2 */
  39 + 1, /* PNX833X_PIC_UART0_INT 3 */
  40 + 1, /* PNX833X_PIC_UART1_INT 4 */
  41 + 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */
  42 + 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */
  43 + 7, /* PNX833X_PIC_GPIO_INT 7 */
  44 + 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */
  45 + 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */
  46 + 4, /* PNX833X_PIC_CONFIG_INT 10 */
  47 + 4, /* PNX833X_PIC_AOI_INT 11 */
  48 + 9, /* PNX833X_PIC_SYNC_INT 12 */
  49 + 9, /* PNX8335_PIC_SATA_INT 13 */
  50 + 4, /* PNX833X_PIC_OSD_INT 14 */
  51 + 9, /* PNX833X_PIC_DISP1_INT 15 */
  52 + 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */
  53 + 9, /* PNX833X_PIC_DISPLAY2_INT 17 */
  54 + 4, /* PNX833X_PIC_VC_INT 18 */
  55 + 4, /* PNX833X_PIC_SC_INT 19 */
  56 + 9, /* PNX833X_PIC_IDE_INT 20 */
  57 + 9, /* PNX833X_PIC_IDE_DMA_INT 21 */
  58 + 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */
  59 + 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */
  60 + 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */
  61 + 4, /* PNX833X_PIC_TS_OUT_INT 25 */
  62 + 4, /* PNX833X_PIC_IR_INT 26 */
  63 + 3, /* PNX833X_PIC_VMSP1_INT 27 */
  64 + 3, /* PNX833X_PIC_VMSP2_INT 28 */
  65 + 4, /* PNX833X_PIC_PIBC_INT 29 */
  66 + 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */
  67 + 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */
  68 + 5, /* PNX833X_PIC_USB_INT 32 */
  69 + 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */
  70 + 4, /* PNX833X_PIC_CLOCK_INT 34 */
  71 + 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */
  72 + 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */
  73 +#if defined(CONFIG_SOC_PNX8335)
  74 + 4, /* PNX8335_PIC_MIU_INT 37 */
  75 + 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */
  76 + 9, /* PNX8335_PIC_SYNC_HD_INT 39 */
  77 + 9, /* PNX8335_PIC_DISP_HD_INT 40 */
  78 + 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */
  79 + 4, /* PNX8335_PIC_OSD_HD1_INT 42 */
  80 + 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */
  81 + 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */
  82 + 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */
  83 + 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */
  84 + 4, /* PNX8335_PIC_DENC_TTX_INT 47 */
  85 + 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */
  86 + 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */
  87 + 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */
  88 + 4, /* PNX8335_PIC_PIBCS_INT 51 */
  89 + 12, /* PNX8335_PIC_ETHERNET_INT 52 */
  90 + 3, /* PNX8335_PIC_VMSP1_0_INT 53 */
  91 + 3, /* PNX8335_PIC_VMSP1_1_INT 54 */
  92 + 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */
  93 + 4, /* PNX8335_PIC_TDGR_DE_INT 56 */
  94 + 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */
  95 +#endif
  96 +};
  97 +
  98 +static void pnx833x_timer_dispatch(void)
  99 +{
  100 + do_IRQ(mips_cpu_timer_irq);
  101 +}
  102 +
  103 +static void pic_dispatch(void)
  104 +{
  105 + unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
  106 +
  107 + if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
  108 + unsigned long priority = PNX833X_PIC_INT_PRIORITY;
  109 + PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
  110 +
  111 + if (irq == PNX833X_PIC_GPIO_INT) {
  112 + unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
  113 + int pin;
  114 + while ((pin = ffs(mask & 0xffff))) {
  115 + pin -= 1;
  116 + do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
  117 + mask &= ~(1 << pin);
  118 + }
  119 + } else {
  120 + do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
  121 + }
  122 +
  123 + PNX833X_PIC_INT_PRIORITY = priority;
  124 + } else {
  125 + printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
  126 + }
  127 +}
  128 +
  129 +asmlinkage void plat_irq_dispatch(void)
  130 +{
  131 + unsigned int pending = read_c0_status() & read_c0_cause();
  132 +
  133 + if (pending & STATUSF_IP4)
  134 + pic_dispatch();
  135 + else if (pending & STATUSF_IP7)
  136 + do_IRQ(PNX833X_TIMER_IRQ);
  137 + else
  138 + spurious_interrupt();
  139 +}
  140 +
  141 +static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
  142 +{
  143 + /* Currently we do this by setting IRQ priority to 1.
  144 + If priority support is being implemented, 1 should be repalced
  145 + by a better value. */
  146 + PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
  147 +}
  148 +
  149 +static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
  150 +{
  151 + /* Disable IRQ by writing setting it's priority to 0 */
  152 + PNX833X_PIC_INT_REG(irq) = 0;
  153 +}
  154 +
  155 +static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */
  156 +#define IRQFLAG_STARTED 1
  157 +#define IRQFLAG_DISABLED 2
  158 +
  159 +static DEFINE_SPINLOCK(pnx833x_irq_lock);
  160 +
  161 +static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
  162 +{
  163 + unsigned long flags;
  164 + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
  165 +
  166 + spin_lock_irqsave(&pnx833x_irq_lock, flags);
  167 +
  168 + irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */
  169 + pnx833x_hard_enable_pic_irq(pic_irq);
  170 +
  171 + spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
  172 + return 0;
  173 +}
  174 +
  175 +static void pnx833x_shutdown_pic_irq(unsigned int irq)
  176 +{
  177 + unsigned long flags;
  178 + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
  179 +
  180 + spin_lock_irqsave(&pnx833x_irq_lock, flags);
  181 +
  182 + irqflags[pic_irq] = 0; /* not started */
  183 + pnx833x_hard_disable_pic_irq(pic_irq);
  184 +
  185 + spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
  186 +}
  187 +
  188 +static void pnx833x_enable_pic_irq(unsigned int irq)
  189 +{
  190 + unsigned long flags;
  191 + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
  192 +
  193 + spin_lock_irqsave(&pnx833x_irq_lock, flags);
  194 +
  195 + irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
  196 + if (irqflags[pic_irq] == IRQFLAG_STARTED)
  197 + pnx833x_hard_enable_pic_irq(pic_irq);
  198 +
  199 + spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
  200 +}
  201 +
  202 +static void pnx833x_disable_pic_irq(unsigned int irq)
  203 +{
  204 + unsigned long flags;
  205 + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
  206 +
  207 + spin_lock_irqsave(&pnx833x_irq_lock, flags);
  208 +
  209 + irqflags[pic_irq] |= IRQFLAG_DISABLED;
  210 + pnx833x_hard_disable_pic_irq(pic_irq);
  211 +
  212 + spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
  213 +}
  214 +
  215 +static void pnx833x_ack_pic_irq(unsigned int irq)
  216 +{
  217 +}
  218 +
  219 +static void pnx833x_end_pic_irq(unsigned int irq)
  220 +{
  221 +}
  222 +
  223 +static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
  224 +
  225 +static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
  226 +{
  227 + int pin = irq - PNX833X_GPIO_IRQ_BASE;
  228 + unsigned long flags;
  229 + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
  230 + pnx833x_gpio_enable_irq(pin);
  231 + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
  232 + return 0;
  233 +}
  234 +
  235 +static void pnx833x_enable_gpio_irq(unsigned int irq)
  236 +{
  237 + int pin = irq - PNX833X_GPIO_IRQ_BASE;
  238 + unsigned long flags;
  239 + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
  240 + pnx833x_gpio_enable_irq(pin);
  241 + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
  242 +}
  243 +
  244 +static void pnx833x_disable_gpio_irq(unsigned int irq)
  245 +{
  246 + int pin = irq - PNX833X_GPIO_IRQ_BASE;
  247 + unsigned long flags;
  248 + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
  249 + pnx833x_gpio_disable_irq(pin);
  250 + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
  251 +}
  252 +
  253 +static void pnx833x_ack_gpio_irq(unsigned int irq)
  254 +{
  255 +}
  256 +
  257 +static void pnx833x_end_gpio_irq(unsigned int irq)
  258 +{
  259 + int pin = irq - PNX833X_GPIO_IRQ_BASE;
  260 + unsigned long flags;
  261 + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
  262 + pnx833x_gpio_clear_irq(pin);
  263 + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
  264 +}
  265 +
  266 +static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
  267 +{
  268 + int pin = irq - PNX833X_GPIO_IRQ_BASE;
  269 + int gpio_mode;
  270 +
  271 + switch (flow_type) {
  272 + case IRQ_TYPE_EDGE_RISING:
  273 + gpio_mode = GPIO_INT_EDGE_RISING;
  274 + break;
  275 + case IRQ_TYPE_EDGE_FALLING:
  276 + gpio_mode = GPIO_INT_EDGE_FALLING;
  277 + break;
  278 + case IRQ_TYPE_EDGE_BOTH:
  279 + gpio_mode = GPIO_INT_EDGE_BOTH;
  280 + break;
  281 + case IRQ_TYPE_LEVEL_HIGH:
  282 + gpio_mode = GPIO_INT_LEVEL_HIGH;
  283 + break;
  284 + case IRQ_TYPE_LEVEL_LOW:
  285 + gpio_mode = GPIO_INT_LEVEL_LOW;
  286 + break;
  287 + default:
  288 + gpio_mode = GPIO_INT_NONE;
  289 + break;
  290 + }
  291 +
  292 + pnx833x_gpio_setup_irq(gpio_mode, pin);
  293 +
  294 + return 0;
  295 +}
  296 +
  297 +static struct irq_chip pnx833x_pic_irq_type = {
  298 + .typename = "PNX-PIC",
  299 + .startup = pnx833x_startup_pic_irq,
  300 + .shutdown = pnx833x_shutdown_pic_irq,
  301 + .enable = pnx833x_enable_pic_irq,
  302 + .disable = pnx833x_disable_pic_irq,
  303 + .ack = pnx833x_ack_pic_irq,
  304 + .end = pnx833x_end_pic_irq
  305 +};
  306 +
  307 +static struct irq_chip pnx833x_gpio_irq_type = {
  308 + .typename = "PNX-GPIO",
  309 + .startup = pnx833x_startup_gpio_irq,
  310 + .shutdown = pnx833x_disable_gpio_irq,
  311 + .enable = pnx833x_enable_gpio_irq,
  312 + .disable = pnx833x_disable_gpio_irq,
  313 + .ack = pnx833x_ack_gpio_irq,
  314 + .end = pnx833x_end_gpio_irq,
  315 + .set_type = pnx833x_set_type_gpio_irq
  316 +};
  317 +
  318 +void __init arch_init_irq(void)
  319 +{
  320 + unsigned int irq;
  321 +
  322 + /* setup standard internal cpu irqs */
  323 + mips_cpu_irq_init();
  324 +
  325 + /* Set IRQ information in irq_desc */
  326 + for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
  327 + pnx833x_hard_disable_pic_irq(irq);
  328 + set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
  329 + }
  330 +
  331 + for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
  332 + set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
  333 +
  334 + /* Set PIC priority limiter register to 0 */
  335 + PNX833X_PIC_INT_PRIORITY = 0;
  336 +
  337 + /* Setup GPIO IRQ dispatching */
  338 + pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
  339 +
  340 + /* Enable PIC IRQs (HWIRQ2) */
  341 + if (cpu_has_vint)
  342 + set_vi_handler(4, pic_dispatch);
  343 +
  344 + write_c0_status(read_c0_status() | IE_IRQ2);
  345 +}
  346 +
  347 +unsigned int __cpuinit get_c0_compare_int(void)
  348 +{
  349 + if (cpu_has_vint)
  350 + set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
  351 +
  352 + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
  353 + return mips_cpu_timer_irq;
  354 +}
  355 +
  356 +void __init plat_time_init(void)
  357 +{
  358 + /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
  359 +
  360 + extern unsigned long mips_hpt_frequency;
  361 + unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
  362 +
  363 + if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
  364 + /* Functional clock is disabled so use crystal frequency */
  365 + mips_hpt_frequency = 25;
  366 + } else {
  367 +#if defined(CONFIG_SOC_PNX8335)
  368 + /* Functional clock is enabled, so get clock multiplier */
  369 + mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
  370 +#else
  371 + static const unsigned long int freq[4] = {240, 160, 120, 80};
  372 + mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
  373 +#endif
  374 + }
  375 +
  376 + printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
  377 +
  378 + mips_hpt_frequency *= 500000;
  379 +}
arch/mips/nxp/pnx833x/common/platform.c
Diff comments   View file @ edb6310
  1 +/*
  2 + * platform.c: platform support for PNX833X.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * Based on software written by:
  9 + * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License as published by
  13 + * the Free Software Foundation; either version 2 of the License, or
  14 + * (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 + */
  25 +#include <linux/device.h>
  26 +#include <linux/dma-mapping.h>
  27 +#include <linux/platform_device.h>
  28 +#include <linux/kernel.h>
  29 +#include <linux/init.h>
  30 +#include <linux/resource.h>
  31 +#include <linux/serial.h>
  32 +#include <linux/serial_pnx8xxx.h>
  33 +#include <linux/mtd/nand.h>
  34 +#include <linux/mtd/partitions.h>
  35 +
  36 +#ifdef CONFIG_I2C_PNX0105
  37 +/* Until i2c driver available in kernel.*/
  38 +#include <linux/i2c-pnx0105.h>
  39 +#endif
  40 +
  41 +#include <irq.h>
  42 +#include <irq-mapping.h>
  43 +#include <pnx833x.h>
  44 +
  45 +static u64 uart_dmamask = DMA_32BIT_MASK;
  46 +
  47 +static struct resource pnx833x_uart_resources[] = {
  48 + [0] = {
  49 + .start = PNX833X_UART0_PORTS_START,
  50 + .end = PNX833X_UART0_PORTS_END,
  51 + .flags = IORESOURCE_MEM,
  52 + },
  53 + [1] = {
  54 + .start = PNX833X_PIC_UART0_INT,
  55 + .end = PNX833X_PIC_UART0_INT,
  56 + .flags = IORESOURCE_IRQ,
  57 + },
  58 + [2] = {
  59 + .start = PNX833X_UART1_PORTS_START,
  60 + .end = PNX833X_UART1_PORTS_END,
  61 + .flags = IORESOURCE_MEM,
  62 + },
  63 + [3] = {
  64 + .start = PNX833X_PIC_UART1_INT,
  65 + .end = PNX833X_PIC_UART1_INT,
  66 + .flags = IORESOURCE_IRQ,
  67 + },
  68 +};
  69 +
  70 +struct pnx8xxx_port pnx8xxx_ports[] = {
  71 + [0] = {
  72 + .port = {
  73 + .type = PORT_PNX8XXX,
  74 + .iotype = UPIO_MEM,
  75 + .membase = (void __iomem *)PNX833X_UART0_PORTS_START,
  76 + .mapbase = PNX833X_UART0_PORTS_START,
  77 + .irq = PNX833X_PIC_UART0_INT,
  78 + .uartclk = 3692300,
  79 + .fifosize = 16,
  80 + .flags = UPF_BOOT_AUTOCONF,
  81 + .line = 0,
  82 + },
  83 + },
  84 + [1] = {
  85 + .port = {
  86 + .type = PORT_PNX8XXX,
  87 + .iotype = UPIO_MEM,
  88 + .membase = (void __iomem *)PNX833X_UART1_PORTS_START,
  89 + .mapbase = PNX833X_UART1_PORTS_START,
  90 + .irq = PNX833X_PIC_UART1_INT,
  91 + .uartclk = 3692300,
  92 + .fifosize = 16,
  93 + .flags = UPF_BOOT_AUTOCONF,
  94 + .line = 1,
  95 + },
  96 + },
  97 +};
  98 +
  99 +static struct platform_device pnx833x_uart_device = {
  100 + .name = "pnx8xxx-uart",
  101 + .id = -1,
  102 + .dev = {
  103 + .dma_mask = &uart_dmamask,
  104 + .coherent_dma_mask = DMA_32BIT_MASK,
  105 + .platform_data = pnx8xxx_ports,
  106 + },
  107 + .num_resources = ARRAY_SIZE(pnx833x_uart_resources),
  108 + .resource = pnx833x_uart_resources,
  109 +};
  110 +
  111 +static u64 ehci_dmamask = DMA_32BIT_MASK;
  112 +
  113 +static struct resource pnx833x_usb_ehci_resources[] = {
  114 + [0] = {
  115 + .start = PNX833X_USB_PORTS_START,
  116 + .end = PNX833X_USB_PORTS_END,
  117 + .flags = IORESOURCE_MEM,
  118 + },
  119 + [1] = {
  120 + .start = PNX833X_PIC_USB_INT,
  121 + .end = PNX833X_PIC_USB_INT,
  122 + .flags = IORESOURCE_IRQ,
  123 + },
  124 +};
  125 +
  126 +static struct platform_device pnx833x_usb_ehci_device = {
  127 + .name = "pnx833x-ehci",
  128 + .id = -1,
  129 + .dev = {
  130 + .dma_mask = &ehci_dmamask,
  131 + .coherent_dma_mask = DMA_32BIT_MASK,
  132 + },
  133 + .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources),
  134 + .resource = pnx833x_usb_ehci_resources,
  135 +};
  136 +
  137 +#ifdef CONFIG_I2C_PNX0105
  138 +static struct resource pnx833x_i2c0_resources[] = {
  139 + {
  140 + .start = PNX833X_I2C0_PORTS_START,
  141 + .end = PNX833X_I2C0_PORTS_END,
  142 + .flags = IORESOURCE_MEM,
  143 + },
  144 + {
  145 + .start = PNX833X_PIC_I2C0_INT,
  146 + .end = PNX833X_PIC_I2C0_INT,
  147 + .flags = IORESOURCE_IRQ,
  148 + },
  149 +};
  150 +
  151 +static struct resource pnx833x_i2c1_resources[] = {
  152 + {
  153 + .start = PNX833X_I2C1_PORTS_START,
  154 + .end = PNX833X_I2C1_PORTS_END,
  155 + .flags = IORESOURCE_MEM,
  156 + },
  157 + {
  158 + .start = PNX833X_PIC_I2C1_INT,
  159 + .end = PNX833X_PIC_I2C1_INT,
  160 + .flags = IORESOURCE_IRQ,
  161 + },
  162 +};
  163 +
  164 +static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = {
  165 + {
  166 + .base = PNX833X_I2C0_PORTS_START,
  167 + .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */
  168 + .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */
  169 + .bus_addr = 0, /* no slave support */
  170 + },
  171 + {
  172 + .base = PNX833X_I2C1_PORTS_START,
  173 + .irq = -1, /* on high freq, polling is faster */
  174 + /*.irq = PNX833X_PIC_I2C1_INT,*/
  175 + .clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */
  176 + .bus_addr = 0, /* no slave support */
  177 + },
  178 +};
  179 +
  180 +static struct platform_device pnx833x_i2c0_device = {
  181 + .name = "i2c-pnx0105",
  182 + .id = 0,
  183 + .dev = {
  184 + .platform_data = &pnx833x_i2c_dev[0],
  185 + },
  186 + .num_resources = ARRAY_SIZE(pnx833x_i2c0_resources),
  187 + .resource = pnx833x_i2c0_resources,
  188 +};
  189 +
  190 +static struct platform_device pnx833x_i2c1_device = {
  191 + .name = "i2c-pnx0105",
  192 + .id = 1,
  193 + .dev = {
  194 + .platform_data = &pnx833x_i2c_dev[1],
  195 + },
  196 + .num_resources = ARRAY_SIZE(pnx833x_i2c1_resources),
  197 + .resource = pnx833x_i2c1_resources,
  198 +};
  199 +#endif
  200 +
  201 +static u64 ethernet_dmamask = DMA_32BIT_MASK;
  202 +
  203 +static struct resource pnx833x_ethernet_resources[] = {
  204 + [0] = {
  205 + .start = PNX8335_IP3902_PORTS_START,
  206 + .end = PNX8335_IP3902_PORTS_END,
  207 + .flags = IORESOURCE_MEM,
  208 + },
  209 + [1] = {
  210 + .start = PNX8335_PIC_ETHERNET_INT,
  211 + .end = PNX8335_PIC_ETHERNET_INT,
  212 + .flags = IORESOURCE_IRQ,
  213 + },
  214 +};
  215 +
  216 +static struct platform_device pnx833x_ethernet_device = {
  217 + .name = "ip3902-eth",
  218 + .id = -1,
  219 + .dev = {
  220 + .dma_mask = &ethernet_dmamask,
  221 + .coherent_dma_mask = DMA_32BIT_MASK,
  222 + },
  223 + .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
  224 + .resource = pnx833x_ethernet_resources,
  225 +};
  226 +
  227 +static struct resource pnx833x_sata_resources[] = {
  228 + [0] = {
  229 + .start = PNX8335_SATA_PORTS_START,
  230 + .end = PNX8335_SATA_PORTS_END,
  231 + .flags = IORESOURCE_MEM,
  232 + },
  233 + [1] = {
  234 + .start = PNX8335_PIC_SATA_INT,
  235 + .end = PNX8335_PIC_SATA_INT,
  236 + .flags = IORESOURCE_IRQ,
  237 + },
  238 +};
  239 +
  240 +static struct platform_device pnx833x_sata_device = {
  241 + .name = "pnx833x-sata",
  242 + .id = -1,
  243 + .num_resources = ARRAY_SIZE(pnx833x_sata_resources),
  244 + .resource = pnx833x_sata_resources,
  245 +};
  246 +
  247 +static const char *part_probes[] = {
  248 + "cmdlinepart",
  249 + NULL
  250 +};
  251 +
  252 +static void
  253 +pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  254 +{
  255 + struct nand_chip *this = mtd->priv;
  256 + unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
  257 +
  258 + if (cmd == NAND_CMD_NONE)
  259 + return;
  260 +
  261 + if (ctrl & NAND_CLE)
  262 + writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK));
  263 + else
  264 + writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK));
  265 +}
  266 +
  267 +static struct platform_nand_data pnx833x_flash_nand_data = {
  268 + .chip = {
  269 + .chip_delay = 25,
  270 + .part_probe_types = part_probes,
  271 + },
  272 + .ctrl = {
  273 + .cmd_ctrl = pnx833x_flash_nand_cmd_ctrl
  274 + }
  275 +};
  276 +
  277 +/*
  278 + * Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!),
  279 + * 12 bytes more seems to be the standard that allows for NAND access.
  280 + */
  281 +static struct resource pnx833x_flash_nand_resource = {
  282 + .start = PNX8335_NAND_BASE,
  283 + .end = PNX8335_NAND_BASE + 12,
  284 + .flags = IORESOURCE_MEM,
  285 +};
  286 +
  287 +static struct platform_device pnx833x_flash_nand = {
  288 + .name = "gen_nand",
  289 + .id = -1,
  290 + .num_resources = 1,
  291 + .resource = &pnx833x_flash_nand_resource,
  292 + .dev = {
  293 + .platform_data = &pnx833x_flash_nand_data,
  294 + },
  295 +};
  296 +
  297 +static struct platform_device *pnx833x_platform_devices[] __initdata = {
  298 + &pnx833x_uart_device,
  299 + &pnx833x_usb_ehci_device,
  300 +#ifdef CONFIG_I2C_PNX0105
  301 + &pnx833x_i2c0_device,
  302 + &pnx833x_i2c1_device,
  303 +#endif
  304 + &pnx833x_ethernet_device,
  305 + &pnx833x_sata_device,
  306 + &pnx833x_flash_nand,
  307 +};
  308 +
  309 +static int __init pnx833x_platform_init(void)
  310 +{
  311 + int res;
  312 +
  313 + res = platform_add_devices(pnx833x_platform_devices,
  314 + ARRAY_SIZE(pnx833x_platform_devices));
  315 +
  316 + return res;
  317 +}
  318 +
  319 +arch_initcall(pnx833x_platform_init);
arch/mips/nxp/pnx833x/common/prom.c
Diff comments   View file @ edb6310
  1 +/*
  2 + * prom.c:
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * Based on software written by:
  9 + * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License as published by
  13 + * the Free Software Foundation; either version 2 of the License, or
  14 + * (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 + */
  25 +#include <linux/init.h>
  26 +#include <asm/bootinfo.h>
  27 +#include <linux/string.h>
  28 +
  29 +void __init prom_init_cmdline(void)
  30 +{
  31 + int argc = fw_arg0;
  32 + char **argv = (char **)fw_arg1;
  33 + char *c = &(arcs_cmdline[0]);
  34 + int i;
  35 +
  36 + for (i = 1; i < argc; i++) {
  37 + strcpy(c, argv[i]);
  38 + c += strlen(argv[i]);
  39 + if (i < argc-1)
  40 + *c++ = ' ';
  41 + }
  42 + *c = 0;
  43 +}
  44 +
  45 +char __init *prom_getenv(char *envname)
  46 +{
  47 + extern char **prom_envp;
  48 + char **env = prom_envp;
  49 + int i;
  50 +
  51 + i = strlen(envname);
  52 +
  53 + while (*env) {
  54 + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
  55 + return *env + i + 1;
  56 + env++;
  57 + }
  58 +
  59 + return 0;
  60 +}
  61 +
  62 +void __init prom_free_prom_memory(void)
  63 +{
  64 +}
  65 +
  66 +char * __init prom_getcmdline(void)
  67 +{
  68 + return arcs_cmdline;
  69 +}
arch/mips/nxp/pnx833x/common/reset.c
Diff comments   View file @ edb6310
  1 +/*
  2 + * reset.c: reset support for PNX833X.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * Based on software written by:
  9 + * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License as published by
  13 + * the Free Software Foundation; either version 2 of the License, or
  14 + * (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 + */
  25 +#include <linux/slab.h>
  26 +#include <linux/reboot.h>
  27 +#include <pnx833x.h>
  28 +
  29 +void pnx833x_machine_restart(char *command)
  30 +{
  31 + PNX833X_RESET_CONTROL_2 = 0;
  32 + PNX833X_RESET_CONTROL = 0;
  33 +}
  34 +
  35 +void pnx833x_machine_halt(void)
  36 +{
  37 + while (1)
  38 + __asm__ __volatile__ ("wait");
  39 +
  40 +}
  41 +
  42 +void pnx833x_machine_power_off(void)
  43 +{
  44 + pnx833x_machine_halt();
  45 +}
arch/mips/nxp/pnx833x/common/setup.c
Diff comments   View file @ edb6310
  1 +/*
  2 + * setup.c: Setup PNX833X Soc.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * Based on software written by:
  9 + * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License as published by
  13 + * the Free Software Foundation; either version 2 of the License, or
  14 + * (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 + */
  25 +#include <linux/init.h>
  26 +#include <linux/interrupt.h>
  27 +#include <linux/ioport.h>
  28 +#include <linux/io.h>
  29 +#include <linux/pci.h>
  30 +#include <asm/reboot.h>
  31 +#include <pnx833x.h>
  32 +#include <gpio.h>
  33 +
  34 +extern void pnx833x_board_setup(void);
  35 +extern void pnx833x_machine_restart(char *);
  36 +extern void pnx833x_machine_halt(void);
  37 +extern void pnx833x_machine_power_off(void);
  38 +
  39 +int __init plat_mem_setup(void)
  40 +{
  41 + /* fake pci bus to avoid bounce buffers */
  42 + PCI_DMA_BUS_IS_PHYS = 1;
  43 +
  44 + /* set mips clock to 320MHz */
  45 +#if defined(CONFIG_SOC_PNX8335)
  46 + PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ);
  47 +#endif
  48 + pnx833x_gpio_init(); /* so it will be ready in board_setup() */
  49 +
  50 + pnx833x_board_setup();
  51 +
  52 + _machine_restart = pnx833x_machine_restart;
  53 + _machine_halt = pnx833x_machine_halt;
  54 + pm_power_off = pnx833x_machine_power_off;
  55 +
  56 + /* IO/MEM resources. */
  57 + set_io_port_base(KSEG1);
  58 + ioport_resource.start = 0;
  59 + ioport_resource.end = ~0;
  60 + iomem_resource.start = 0;
  61 + iomem_resource.end = ~0;
  62 +
  63 + return 0;
  64 +}
arch/mips/nxp/pnx833x/stb22x/Makefile
Diff comments   View file @ edb6310
  1 +lib-y := board.o
  2 +
  3 +EXTRA_CFLAGS += -Werror
arch/mips/nxp/pnx833x/stb22x/board.c
Diff comments   View file @ edb6310
  1 +/*
  2 + * board.c: STB225 board support.
  3 + *
  4 + * Copyright 2008 NXP Semiconductors
  5 + * Chris Steel <chris.steel@nxp.com>
  6 + * Daniel Laird <daniel.j.laird@nxp.com>
  7 + *
  8 + * Based on software written by:
  9 + * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License as published by
  13 + * the Free Software Foundation; either version 2 of the License, or
  14 + * (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 + */
  25 +#include <linux/init.h>
  26 +#include <asm/bootinfo.h>
  27 +#include <linux/mm.h>
  28 +#include <pnx833x.h>
  29 +#include <gpio.h>
  30 +
  31 +/* endianess twiddlers */
  32 +#define PNX8335_DEBUG0 0x4400
  33 +#define PNX8335_DEBUG1 0x4404
  34 +#define PNX8335_DEBUG2 0x4408
  35 +#define PNX8335_DEBUG3 0x440c
  36 +#define PNX8335_DEBUG4 0x4410
  37 +#define PNX8335_DEBUG5 0x4414
  38 +#define PNX8335_DEBUG6 0x4418
  39 +#define PNX8335_DEBUG7 0x441c
  40 +
  41 +int prom_argc;
  42 +char **prom_argv = 0, **prom_envp = 0;
  43 +
  44 +extern void prom_init_cmdline(void);
  45 +extern char *prom_getenv(char *envname);
  46 +
  47 +const char *get_system_type(void)
  48 +{
  49 + return "NXP STB22x";
  50 +}
  51 +
  52 +static inline unsigned long env_or_default(char *env, unsigned long dfl)
  53 +{
  54 + char *str = prom_getenv(env);
  55 + return str ? simple_strtol(str, 0, 0) : dfl;
  56 +}
  57 +
  58 +void __init prom_init(void)
  59 +{
  60 + unsigned long memsize;
  61 +
  62 + prom_argc = fw_arg0;
  63 + prom_argv = (char **)fw_arg1;
  64 + prom_envp = (char **)fw_arg2;
  65 +
  66 + prom_init_cmdline();
  67 +
  68 + memsize = env_or_default("memsize", 0x02000000);
  69 + add_memory_region(0, memsize, BOOT_MEM_RAM);
  70 +}
  71 +
  72 +void __init pnx833x_board_setup(void)
  73 +{
  74 + pnx833x_gpio_select_function_alt(4);
  75 + pnx833x_gpio_select_output(4);
  76 + pnx833x_gpio_select_function_alt(5);
  77 + pnx833x_gpio_select_input(5);
  78 + pnx833x_gpio_select_function_alt(6);
  79 + pnx833x_gpio_select_input(6);
  80 + pnx833x_gpio_select_function_alt(7);
  81 + pnx833x_gpio_select_output(7);
  82 +
  83 + pnx833x_gpio_select_function_alt(25);
  84 + pnx833x_gpio_select_function_alt(26);
  85 +
  86 + pnx833x_gpio_select_function_alt(27);
  87 + pnx833x_gpio_select_function_alt(28);
  88 + pnx833x_gpio_select_function_alt(29);
  89 + pnx833x_gpio_select_function_alt(30);
  90 + pnx833x_gpio_select_function_alt(31);
  91 + pnx833x_gpio_select_function_alt(32);
  92 + pnx833x_gpio_select_function_alt(33);
  93 +
  94 +#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  95 + /* Setup MIU for NAND access on CS0...
  96 + *
  97 + * (it seems that we must also configure CS1 for reliable operation,
  98 + * otherwise the first read ID command will fail if it's read as 4 bytes
  99 + * but pass if it's read as 1 word.)
  100 + */
  101 +
  102 + /* Setup MIU CS0 & CS1 timing */
  103 + PNX833X_MIU_SEL0 = 0;
  104 + PNX833X_MIU_SEL1 = 0;
  105 + PNX833X_MIU_SEL0_TIMING = 0x50003081;
  106 + PNX833X_MIU_SEL1_TIMING = 0x50003081;
  107 +
  108 + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
  109 + pnx833x_gpio_select_function_alt(0);
  110 +
  111 + /* Setup GPIO 04 to input NAND read/busy signal */
  112 + pnx833x_gpio_select_function_io(4);
  113 + pnx833x_gpio_select_input(4);
  114 +
  115 + /* Setup GPIO 05 to disable NAND write protect */
  116 + pnx833x_gpio_select_function_io(5);
  117 + pnx833x_gpio_select_output(5);
  118 + pnx833x_gpio_write(1, 5);
  119 +
  120 +#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE)
  121 +
  122 + /* Set up MIU for 16-bit NOR access on CS0 and CS1... */
  123 +
  124 + /* Setup MIU CS0 & CS1 timing */
  125 + PNX833X_MIU_SEL0 = 1;
  126 + PNX833X_MIU_SEL1 = 1;
  127 + PNX833X_MIU_SEL0_TIMING = 0x6A08D082;
  128 + PNX833X_MIU_SEL1_TIMING = 0x6A08D082;
  129 +
  130 + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
  131 + pnx833x_gpio_select_function_alt(0);
  132 +#endif
  133 +}