cnic: Add support for 57712 device

Add new interrupt ack functions and other hardware interface logic to support the new device. Update version to 2.2.6. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>

cnic: Add support for 57712 device
Add new interrupt ack functions and other hardware interface logic to support the new device. Update version to 2.2.6. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Michael Chan · David S. Miller
1 parent a3ceeeb8f1
Showing 3 changed files with 103 additions and 17 deletions Side-by-side Diff
drivers/net/cnic.c
drivers/net/cnic.h
drivers/net/cnic_if.h
@@ -1077,7 +1077,7 @@
  
 	cp->ctx_blks = blks;
 	cp->ctx_blk_size = ctx_blk_size;
-	if (BNX2X_CHIP_IS_E1H(cp->chip_id))
+	if (!BNX2X_CHIP_IS_57710(cp->chip_id))
 		cp->ctx_align = 0;
 	else
 		cp->ctx_align = ctx_blk_size;
@@ -2406,6 +2406,22 @@
 	CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
 }
  
+static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
+			    u16 index, u8 op, u8 update)
+{
+	struct igu_regular cmd_data;
+	u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
+
+	cmd_data.sb_id_and_flags =
+		(index << IGU_REGULAR_SB_INDEX_SHIFT) |
+		(segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
+		(update << IGU_REGULAR_BUPDATE_SHIFT) |
+		(op << IGU_REGULAR_ENABLE_INT_SHIFT);
+
+
+	CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
+}
+
 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
 {
 	struct cnic_local *cp = dev->cnic_priv;
@@ -2414,6 +2430,14 @@
 			   IGU_INT_DISABLE, 0);
 }
  
+static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
+{
+	struct cnic_local *cp = dev->cnic_priv;
+
+	cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
+			IGU_INT_DISABLE, 0);
+}
+
 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
 {
 	u32 last_status = *info->status_idx_ptr;
@@ -2445,8 +2469,12 @@
 	status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  
 	CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
-	cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
-			   status_idx, IGU_INT_ENABLE, 1);
+	if (BNX2X_CHIP_IS_E2(cp->chip_id))
+		cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
+				status_idx, IGU_INT_ENABLE, 1);
+	else
+		cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
+				   status_idx, IGU_INT_ENABLE, 1);
 }
  
 static int cnic_service_bnx2x(void *data, void *status_blk)
@@ -4208,7 +4236,7 @@
 static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
 {
 	struct cnic_local *cp = dev->cnic_priv;
-	u32 base, addr, val;
+	u32 base, base2, addr, val;
 	int port = CNIC_PORT(cp);
  
 	dev->max_iscsi_conn = 0;
@@ -4216,6 +4244,8 @@
 	if (base == 0)
 		return;
  
+	base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
+					      MISC_REG_GENERIC_CR_0));
 	addr = BNX2X_SHMEM_ADDR(base,
 		dev_info.port_hw_config[port].iscsi_mac_upper);
  
  
@@ -4248,11 +4278,15 @@
 			val16 ^= 0x1e1e;
 		dev->max_iscsi_conn = val16;
 	}
-	if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
+	if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
 		int func = CNIC_FUNC(cp);
 		u32 mf_cfg_addr;
  
-		mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
+		if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
+			mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
+					      mf_cfg_addr));
+		else
+			mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  
 		addr = mf_cfg_addr +
 			offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
  
@@ -4277,9 +4311,22 @@
 	struct cnic_eth_dev *ethdev = cp->ethdev;
 	int func = CNIC_FUNC(cp), ret, i;
 	u32 pfid;
-	struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  
-	cp->pfid = func;
+	if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+		u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
+
+		if (!(val & 1))
+			val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
+		else
+			val = (val >> 1) & 1;
+
+		if (val)
+			cp->pfid = func >> 1;
+		else
+			cp->pfid = func & 0x6;
+	} else {
+		cp->pfid = func;
+	}
 	pfid = cp->pfid;
  
 	ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  
@@ -4294,11 +4341,22 @@
 			  CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
 	cp->kcq1.sw_prod_idx = 0;
  
-	cp->kcq1.hw_prod_idx_ptr =
-		&sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
-	cp->kcq1.status_idx_ptr =
-		&sb->sb.running_index[SM_RX_ID];
+	if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+		struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  
+		cp->kcq1.hw_prod_idx_ptr =
+			&sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
+		cp->kcq1.status_idx_ptr =
+			&sb->sb.running_index[SM_RX_ID];
+	} else {
+		struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
+
+		cp->kcq1.hw_prod_idx_ptr =
+			&sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
+		cp->kcq1.status_idx_ptr =
+			&sb->sb.running_index[SM_RX_ID];
+	}
+
 	cnic_get_bnx2x_iscsi_info(dev);
  
 	/* Only 1 EQ */
@@ -4380,7 +4438,9 @@
 		cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  
 		off = BAR_USTRORM_INTMEM +
-			 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli);
+			(BNX2X_CHIP_IS_E2(cp->chip_id) ?
+			 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
+			 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  
 		for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
 			CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
@@ -4506,7 +4566,6 @@
 		return -EALREADY;
  
 	dev->regview = ethdev->io_base;
-	cp->chip_id = ethdev->chip_id;
 	pci_dev_get(dev->pcidev);
 	cp->func = PCI_FUNC(dev->pcidev->devfn);
 	cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
@@ -4683,6 +4742,7 @@
 	cp = cdev->cnic_priv;
 	cp->ethdev = ethdev;
 	cdev->pcidev = pdev;
+	cp->chip_id = ethdev->chip_id;
  
 	cp->cnic_ops = &cnic_bnx2_ops;
 	cp->start_hw = cnic_start_bnx2_hw;
@@ -4737,6 +4797,7 @@
 	cp = cdev->cnic_priv;
 	cp->ethdev = ethdev;
 	cdev->pcidev = pdev;
+	cp->chip_id = ethdev->chip_id;
  
 	cp->cnic_ops = &cnic_bnx2x_ops;
 	cp->start_hw = cnic_start_bnx2x_hw;
@@ -4748,7 +4809,10 @@
 	cp->stop_cm = cnic_cm_stop_bnx2x_hw;
 	cp->enable_int = cnic_enable_bnx2x_int;
 	cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
-	cp->ack_int = cnic_ack_bnx2x_msix;
+	if (BNX2X_CHIP_IS_E2(cp->chip_id))
+		cp->ack_int = cnic_ack_bnx2x_e2_msix;
+	else
+		cp->ack_int = cnic_ack_bnx2x_msix;
 	cp->close_conn = cnic_close_bnx2x_conn;
 	cp->next_idx = cnic_bnx2x_next_idx;
 	cp->hw_idx = cnic_bnx2x_hw_idx;
@@ -372,15 +372,35 @@
 #define BNX2X_ISCSI_PBL_NOT_CACHED	0xff
 #define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED	0xff
  
+#define BNX2X_CHIP_NUM_57710		0x164e
 #define BNX2X_CHIP_NUM_57711		0x164f
 #define BNX2X_CHIP_NUM_57711E		0x1650
+#define BNX2X_CHIP_NUM_57712		0x1662
+#define BNX2X_CHIP_NUM_57712E		0x1663
+#define BNX2X_CHIP_NUM_57713		0x1651
+#define BNX2X_CHIP_NUM_57713E		0x1652
+
 #define BNX2X_CHIP_NUM(x)		(x >> 16)
+#define BNX2X_CHIP_IS_57710(x)		\
+	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57710)
 #define BNX2X_CHIP_IS_57711(x)		\
 	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711)
 #define BNX2X_CHIP_IS_57711E(x)		\
 	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711E)
 #define BNX2X_CHIP_IS_E1H(x)		\
 	(BNX2X_CHIP_IS_57711(x) || BNX2X_CHIP_IS_57711E(x))
+#define BNX2X_CHIP_IS_57712(x)		\
+	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712)
+#define BNX2X_CHIP_IS_57712E(x)		\
+	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712E)
+#define BNX2X_CHIP_IS_57713(x)		\
+	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713)
+#define BNX2X_CHIP_IS_57713E(x)		\
+	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713E)
+#define BNX2X_CHIP_IS_E2(x)		\
+	(BNX2X_CHIP_IS_57712(x) || BNX2X_CHIP_IS_57712E(x) || \
+	 BNX2X_CHIP_IS_57713(x) || BNX2X_CHIP_IS_57713E(x))
+
 #define IS_E1H_OFFSET       		BNX2X_CHIP_IS_E1H(cp->chip_id)
  
 #define BNX2X_RX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
@@ -409,6 +429,8 @@
  
 #define CNIC_PORT(cp)			((cp)->pfid & 1)
 #define CNIC_FUNC(cp)			((cp)->func)
+#define CNIC_PATH(cp)			(!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
+					 (CNIC_FUNC(cp) & 1))
 #define CNIC_E1HVN(cp)			((cp)->pfid >> 1)
  
 #define BNX2X_HW_CID(cp, x)		((CNIC_PORT(cp) << 23) | \
@@ -12,8 +12,8 @@
 #ifndef CNIC_IF_H
 #define CNIC_IF_H
  
-#define CNIC_MODULE_VERSION	"2.2.5"
-#define CNIC_MODULE_RELDATE	"September 29, 2010"
+#define CNIC_MODULE_VERSION	"2.2.6"
+#define CNIC_MODULE_RELDATE	"Oct 12, 2010"
  
 #define CNIC_ULP_RDMA		0
 #define CNIC_ULP_ISCSI		1
...	...	@@ -1077,7 +1077,7 @@
1077	1077
1078	1078	cp->ctx_blks = blks;
1079	1079	cp->ctx_blk_size = ctx_blk_size;
1080		- if (BNX2X_CHIP_IS_E1H(cp->chip_id))
	1080	+ if (!BNX2X_CHIP_IS_57710(cp->chip_id))
1081	1081	cp->ctx_align = 0;
1082	1082	else
1083	1083	cp->ctx_align = ctx_blk_size;
...	...	@@ -2406,6 +2406,22 @@
2406	2406	CNIC_WR(dev, hc_addr, ((u32 )&igu_ack));
2407	2407	}
2408	2408
	2409	+static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
	2410	+ u16 index, u8 op, u8 update)
	2411	+{
	2412	+ struct igu_regular cmd_data;
	2413	+ u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
	2414	+
	2415	+ cmd_data.sb_id_and_flags =
	2416	+ (index << IGU_REGULAR_SB_INDEX_SHIFT) \|
	2417	+ (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) \|
	2418	+ (update << IGU_REGULAR_BUPDATE_SHIFT) \|
	2419	+ (op << IGU_REGULAR_ENABLE_INT_SHIFT);
	2420	+
	2421	+
	2422	+ CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
	2423	+}
	2424	+
2409	2425	static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2410	2426	{
2411	2427	struct cnic_local *cp = dev->cnic_priv;
...	...	@@ -2414,6 +2430,14 @@
2414	2430	IGU_INT_DISABLE, 0);
2415	2431	}
2416	2432
	2433	+static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
	2434	+{
	2435	+ struct cnic_local *cp = dev->cnic_priv;
	2436	+
	2437	+ cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
	2438	+ IGU_INT_DISABLE, 0);
	2439	+}
	2440	+
2417	2441	static u32 cnic_service_bnx2x_kcq(struct cnic_dev dev, struct kcq_info info)
2418	2442	{
2419	2443	u32 last_status = *info->status_idx_ptr;
...	...	@@ -2445,8 +2469,12 @@
2445	2469	status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
2446	2470
2447	2471	CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
2448		- cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
2449		- status_idx, IGU_INT_ENABLE, 1);
	2472	+ if (BNX2X_CHIP_IS_E2(cp->chip_id))
	2473	+ cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
	2474	+ status_idx, IGU_INT_ENABLE, 1);
	2475	+ else
	2476	+ cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
	2477	+ status_idx, IGU_INT_ENABLE, 1);
2450	2478	}
2451	2479
2452	2480	static int cnic_service_bnx2x(void data, void status_blk)
...	...	@@ -4208,7 +4236,7 @@
4208	4236	static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4209	4237	{
4210	4238	struct cnic_local *cp = dev->cnic_priv;
4211		- u32 base, addr, val;
	4239	+ u32 base, base2, addr, val;
4212	4240	int port = CNIC_PORT(cp);
4213	4241
4214	4242	dev->max_iscsi_conn = 0;
...	...	@@ -4216,6 +4244,8 @@
4216	4244	if (base == 0)
4217	4245	return;
4218	4246
	4247	+ base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
	4248	+ MISC_REG_GENERIC_CR_0));
4219	4249	addr = BNX2X_SHMEM_ADDR(base,
4220	4250	dev_info.port_hw_config[port].iscsi_mac_upper);
4221	4251
4222	4252
...	...	@@ -4248,11 +4278,15 @@
4248	4278	val16 ^= 0x1e1e;
4249	4279	dev->max_iscsi_conn = val16;
4250	4280	}
4251		- if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
	4281	+ if (BNX2X_CHIP_IS_E1H(cp->chip_id) \|\| BNX2X_CHIP_IS_E2(cp->chip_id)) {
4252	4282	int func = CNIC_FUNC(cp);
4253	4283	u32 mf_cfg_addr;
4254	4284
4255		- mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
	4285	+ if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
	4286	+ mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
	4287	+ mf_cfg_addr));
	4288	+ else
	4289	+ mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
4256	4290
4257	4291	addr = mf_cfg_addr +
4258	4292	offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
4259	4293
...	...	@@ -4277,9 +4311,22 @@
4277	4311	struct cnic_eth_dev *ethdev = cp->ethdev;
4278	4312	int func = CNIC_FUNC(cp), ret, i;
4279	4313	u32 pfid;
4280		- struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
4281	4314
4282		- cp->pfid = func;
	4315	+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
	4316	+ u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
	4317	+
	4318	+ if (!(val & 1))
	4319	+ val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
	4320	+ else
	4321	+ val = (val >> 1) & 1;
	4322	+
	4323	+ if (val)
	4324	+ cp->pfid = func >> 1;
	4325	+ else
	4326	+ cp->pfid = func & 0x6;
	4327	+ } else {
	4328	+ cp->pfid = func;
	4329	+ }
4283	4330	pfid = cp->pfid;
4284	4331
4285	4332	ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4286	4333
...	...	@@ -4294,11 +4341,22 @@
4294	4341	CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
4295	4342	cp->kcq1.sw_prod_idx = 0;
4296	4343
4297		- cp->kcq1.hw_prod_idx_ptr =
4298		- &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4299		- cp->kcq1.status_idx_ptr =
4300		- &sb->sb.running_index[SM_RX_ID];
	4344	+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
	4345	+ struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4301	4346
	4347	+ cp->kcq1.hw_prod_idx_ptr =
	4348	+ &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
	4349	+ cp->kcq1.status_idx_ptr =
	4350	+ &sb->sb.running_index[SM_RX_ID];
	4351	+ } else {
	4352	+ struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
	4353	+
	4354	+ cp->kcq1.hw_prod_idx_ptr =
	4355	+ &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
	4356	+ cp->kcq1.status_idx_ptr =
	4357	+ &sb->sb.running_index[SM_RX_ID];
	4358	+ }
	4359	+
4302	4360	cnic_get_bnx2x_iscsi_info(dev);
4303	4361
4304	4362	/* Only 1 EQ */
...	...	@@ -4380,7 +4438,9 @@
4380	4438	cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4381	4439
4382	4440	off = BAR_USTRORM_INTMEM +
4383		- USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli);
	4441	+ (BNX2X_CHIP_IS_E2(cp->chip_id) ?
	4442	+ USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
	4443	+ USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
4384	4444
4385	4445	for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4386	4446	CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
...	...	@@ -4506,7 +4566,6 @@
4506	4566	return -EALREADY;
4507	4567
4508	4568	dev->regview = ethdev->io_base;
4509		- cp->chip_id = ethdev->chip_id;
4510	4569	pci_dev_get(dev->pcidev);
4511	4570	cp->func = PCI_FUNC(dev->pcidev->devfn);
4512	4571	cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
...	...	@@ -4683,6 +4742,7 @@
4683	4742	cp = cdev->cnic_priv;
4684	4743	cp->ethdev = ethdev;
4685	4744	cdev->pcidev = pdev;
	4745	+ cp->chip_id = ethdev->chip_id;
4686	4746
4687	4747	cp->cnic_ops = &cnic_bnx2_ops;
4688	4748	cp->start_hw = cnic_start_bnx2_hw;
...	...	@@ -4737,6 +4797,7 @@
4737	4797	cp = cdev->cnic_priv;
4738	4798	cp->ethdev = ethdev;
4739	4799	cdev->pcidev = pdev;
	4800	+ cp->chip_id = ethdev->chip_id;
4740	4801
4741	4802	cp->cnic_ops = &cnic_bnx2x_ops;
4742	4803	cp->start_hw = cnic_start_bnx2x_hw;
...	...	@@ -4748,7 +4809,10 @@
4748	4809	cp->stop_cm = cnic_cm_stop_bnx2x_hw;
4749	4810	cp->enable_int = cnic_enable_bnx2x_int;
4750	4811	cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
4751		- cp->ack_int = cnic_ack_bnx2x_msix;
	4812	+ if (BNX2X_CHIP_IS_E2(cp->chip_id))
	4813	+ cp->ack_int = cnic_ack_bnx2x_e2_msix;
	4814	+ else
	4815	+ cp->ack_int = cnic_ack_bnx2x_msix;
4752	4816	cp->close_conn = cnic_close_bnx2x_conn;
4753	4817	cp->next_idx = cnic_bnx2x_next_idx;
4754	4818	cp->hw_idx = cnic_bnx2x_hw_idx;
...	...	@@ -372,15 +372,35 @@
372	372	#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
373	373	#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
374	374
	375	+#define BNX2X_CHIP_NUM_57710 0x164e
375	376	#define BNX2X_CHIP_NUM_57711 0x164f
376	377	#define BNX2X_CHIP_NUM_57711E 0x1650
	378	+#define BNX2X_CHIP_NUM_57712 0x1662
	379	+#define BNX2X_CHIP_NUM_57712E 0x1663
	380	+#define BNX2X_CHIP_NUM_57713 0x1651
	381	+#define BNX2X_CHIP_NUM_57713E 0x1652
	382	+
377	383	#define BNX2X_CHIP_NUM(x) (x >> 16)
	384	+#define BNX2X_CHIP_IS_57710(x) \
	385	+ (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57710)
378	386	#define BNX2X_CHIP_IS_57711(x) \
379	387	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711)
380	388	#define BNX2X_CHIP_IS_57711E(x) \
381	389	(BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711E)
382	390	#define BNX2X_CHIP_IS_E1H(x) \
383	391	(BNX2X_CHIP_IS_57711(x) \|\| BNX2X_CHIP_IS_57711E(x))
	392	+#define BNX2X_CHIP_IS_57712(x) \
	393	+ (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712)
	394	+#define BNX2X_CHIP_IS_57712E(x) \
	395	+ (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712E)
	396	+#define BNX2X_CHIP_IS_57713(x) \
	397	+ (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713)
	398	+#define BNX2X_CHIP_IS_57713E(x) \
	399	+ (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713E)
	400	+#define BNX2X_CHIP_IS_E2(x) \
	401	+ (BNX2X_CHIP_IS_57712(x) \|\| BNX2X_CHIP_IS_57712E(x) \|\| \
	402	+ BNX2X_CHIP_IS_57713(x) \|\| BNX2X_CHIP_IS_57713E(x))
	403	+
384	404	#define IS_E1H_OFFSET BNX2X_CHIP_IS_E1H(cp->chip_id)
385	405
386	406	#define BNX2X_RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
...	...	@@ -409,6 +429,8 @@
409	429
410	430	#define CNIC_PORT(cp) ((cp)->pfid & 1)
411	431	#define CNIC_FUNC(cp) ((cp)->func)
	432	+#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
	433	+ (CNIC_FUNC(cp) & 1))
412	434	#define CNIC_E1HVN(cp) ((cp)->pfid >> 1)
413	435
414	436	#define BNX2X_HW_CID(cp, x) ((CNIC_PORT(cp) << 23) \| \
...	...	@@ -12,8 +12,8 @@
12	12	#ifndef CNIC_IF_H
13	13	#define CNIC_IF_H
14	14
15		-#define CNIC_MODULE_VERSION "2.2.5"
16		-#define CNIC_MODULE_RELDATE "September 29, 2010"
	15	+#define CNIC_MODULE_VERSION "2.2.6"
	16	+#define CNIC_MODULE_RELDATE "Oct 12, 2010"
17	17
18	18	#define CNIC_ULP_RDMA 0
19	19	#define CNIC_ULP_ISCSI 1