MIPS: Alchemy: irq: use runtime CPU type detection

Use runtime CPU detection instead of relying on preprocessor symbols. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Alchemy: irq: use runtime CPU type detection
Use runtime CPU detection instead of relying on preprocessor symbols. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss · Ralf Baechle
1 parent 5d400f5c59
Showing 1 changed file with 54 additions and 43 deletions Side-by-side Diff
arch/mips/alchemy/common/irq.c
@@ -51,8 +51,9 @@
 	int im_irq;
 	int im_type;
 	int im_request;		/* set 1 to get higher priority */
-} au1xxx_ic0_map[] __initdata = {
-#if defined(CONFIG_SOC_AU1000)
+};
+
+struct au1xxx_irqmap au1000_irqmap[] __initdata = {
 	{ AU1000_UART0_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1000_UART1_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1000_UART2_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
  
@@ -84,9 +85,10 @@
 	{ AU1000_MAC0_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1000_MAC1_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1000_AC97C_INT,	  IRQ_TYPE_EDGE_RISING, 0 },
+	{ -1, },
+};
  
-#elif defined(CONFIG_SOC_AU1500)
-
+struct au1xxx_irqmap au1500_irqmap[] __initdata = {
 	{ AU1500_UART0_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1500_PCI_INTA,	  IRQ_TYPE_LEVEL_LOW,   0 },
 	{ AU1500_PCI_INTB,	  IRQ_TYPE_LEVEL_LOW,   0 },
  
@@ -116,9 +118,10 @@
 	{ AU1500_MAC0_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1500_MAC1_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1500_AC97C_INT,	  IRQ_TYPE_EDGE_RISING, 0 },
+	{ -1, },
+};
  
-#elif defined(CONFIG_SOC_AU1100)
-
+struct au1xxx_irqmap au1100_irqmap[] __initdata = {
 	{ AU1100_UART0_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1100_UART1_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1100_SD_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
  
@@ -150,9 +153,10 @@
 	{ AU1100_MAC0_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1100_LCD_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1100_AC97C_INT,	  IRQ_TYPE_EDGE_RISING, 0 },
+	{ -1, },
+};
  
-#elif defined(CONFIG_SOC_AU1550)
-
+struct au1xxx_irqmap au1550_irqmap[] __initdata = {
 	{ AU1550_UART0_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1550_PCI_INTA,	  IRQ_TYPE_LEVEL_LOW,   0 },
 	{ AU1550_PCI_INTB,	  IRQ_TYPE_LEVEL_LOW,   0 },
  
@@ -181,9 +185,10 @@
 	{ AU1550_USB_HOST_INT,	  IRQ_TYPE_LEVEL_LOW,   0 },
 	{ AU1550_MAC0_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1550_MAC1_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
+	{ -1, },
+};
  
-#elif defined(CONFIG_SOC_AU1200)
-
+struct au1xxx_irqmap au1200_irqmap[] __initdata = {
 	{ AU1200_UART0_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1200_SWT_INT,	  IRQ_TYPE_EDGE_RISING, 0 },
 	{ AU1200_SD_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
@@ -207,10 +212,7 @@
 	{ AU1200_USB_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1200_LCD_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
 	{ AU1200_MAE_BOTH_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
-
-#else
-#error "Error: Unknown Alchemy SOC"
-#endif
+	{ -1, },
 };
  
  
  
@@ -547,36 +549,9 @@
 	do_IRQ(off);
 }
  
-/* setup edge/level and assign request 0/1 */
-static void __init setup_irqmap(struct au1xxx_irqmap *map, int count)
+static void __init au1000_init_irq(struct au1xxx_irqmap *map)
 {
 	unsigned int bit, irq_nr;
-
-	while (count--) {
-		irq_nr = map[count].im_irq;
-
-		if (((irq_nr < AU1000_INTC0_INT_BASE) ||
-		     (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
-		    ((irq_nr < AU1000_INTC1_INT_BASE) ||
-		     (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
-			continue;
-
-		if (irq_nr >= AU1000_INTC1_INT_BASE) {
-			bit = irq_nr - AU1000_INTC1_INT_BASE;
-			if (map[count].im_request)
-				au_writel(1 << bit, IC1_ASSIGNSET);
-		} else {
-			bit = irq_nr - AU1000_INTC0_INT_BASE;
-			if (map[count].im_request)
-				au_writel(1 << bit, IC0_ASSIGNSET);
-		}
-
-		au1x_ic_settype(irq_nr, map[count].im_type);
-	}
-}
-
-void __init arch_init_irq(void)
-{
 	int i;
  
 	/*
  
  
@@ -620,8 +595,44 @@
 	/*
 	 * Initialize IC0, which is fixed per processor.
 	 */
-	setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
+	while (map->im_irq != -1) {
+		irq_nr = map->im_irq;
  
+		if (irq_nr >= AU1000_INTC1_INT_BASE) {
+			bit = irq_nr - AU1000_INTC1_INT_BASE;
+			if (map->im_request)
+				au_writel(1 << bit, IC1_ASSIGNSET);
+		} else {
+			bit = irq_nr - AU1000_INTC0_INT_BASE;
+			if (map->im_request)
+				au_writel(1 << bit, IC0_ASSIGNSET);
+		}
+
+		au1x_ic_settype(irq_nr, map->im_type);
+		++map;
+	}
+
 	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
+}
+
+void __init arch_init_irq(void)
+{
+	switch (alchemy_get_cputype()) {
+	case ALCHEMY_CPU_AU1000:
+		au1000_init_irq(au1000_irqmap);
+		break;
+	case ALCHEMY_CPU_AU1500:
+		au1000_init_irq(au1500_irqmap);
+		break;
+	case ALCHEMY_CPU_AU1100:
+		au1000_init_irq(au1100_irqmap);
+		break;
+	case ALCHEMY_CPU_AU1550:
+		au1000_init_irq(au1550_irqmap);
+		break;
+	case ALCHEMY_CPU_AU1200:
+		au1000_init_irq(au1200_irqmap);
+		break;
+	}
 }
...	...	@@ -51,8 +51,9 @@
51	51	int im_irq;
52	52	int im_type;
53	53	int im_request; /* set 1 to get higher priority */
54		-} au1xxx_ic0_map[] __initdata = {
55		-#if defined(CONFIG_SOC_AU1000)
	54	+};
	55	+
	56	+struct au1xxx_irqmap au1000_irqmap[] __initdata = {
56	57	{ AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
57	58	{ AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
58	59	{ AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
59	60
...	...	@@ -84,9 +85,10 @@
84	85	{ AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
85	86	{ AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
86	87	{ AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
	88	+ { -1, },
	89	+};
87	90
88		-#elif defined(CONFIG_SOC_AU1500)
89		-
	91	+struct au1xxx_irqmap au1500_irqmap[] __initdata = {
90	92	{ AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
91	93	{ AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
92	94	{ AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
93	95
...	...	@@ -116,9 +118,10 @@
116	118	{ AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117	119	{ AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118	120	{ AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
	121	+ { -1, },
	122	+};
119	123
120		-#elif defined(CONFIG_SOC_AU1100)
121		-
	124	+struct au1xxx_irqmap au1100_irqmap[] __initdata = {
122	125	{ AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
123	126	{ AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
124	127	{ AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
125	128
...	...	@@ -150,9 +153,10 @@
150	153	{ AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151	154	{ AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
152	155	{ AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
	156	+ { -1, },
	157	+};
153	158
154		-#elif defined(CONFIG_SOC_AU1550)
155		-
	159	+struct au1xxx_irqmap au1550_irqmap[] __initdata = {
156	160	{ AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157	161	{ AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
158	162	{ AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
159	163
...	...	@@ -181,9 +185,10 @@
181	185	{ AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
182	186	{ AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183	187	{ AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
	188	+ { -1, },
	189	+};
184	190
185		-#elif defined(CONFIG_SOC_AU1200)
186		-
	191	+struct au1xxx_irqmap au1200_irqmap[] __initdata = {
187	192	{ AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188	193	{ AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
189	194	{ AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
...	...	@@ -207,10 +212,7 @@
207	212	{ AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
208	213	{ AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
209	214	{ AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
210		-
211		-#else
212		-#error "Error: Unknown Alchemy SOC"
213		-#endif
	215	+ { -1, },
214	216	};
215	217
216	218
217	219
...	...	@@ -547,36 +549,9 @@
547	549	do_IRQ(off);
548	550	}
549	551
550		-/* setup edge/level and assign request 0/1 */
551		-static void __init setup_irqmap(struct au1xxx_irqmap *map, int count)
	552	+static void __init au1000_init_irq(struct au1xxx_irqmap *map)
552	553	{
553	554	unsigned int bit, irq_nr;
554		-
555		- while (count--) {
556		- irq_nr = map[count].im_irq;
557		-
558		- if (((irq_nr < AU1000_INTC0_INT_BASE) \|\|
559		- (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
560		- ((irq_nr < AU1000_INTC1_INT_BASE) \|\|
561		- (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
562		- continue;
563		-
564		- if (irq_nr >= AU1000_INTC1_INT_BASE) {
565		- bit = irq_nr - AU1000_INTC1_INT_BASE;
566		- if (map[count].im_request)
567		- au_writel(1 << bit, IC1_ASSIGNSET);
568		- } else {
569		- bit = irq_nr - AU1000_INTC0_INT_BASE;
570		- if (map[count].im_request)
571		- au_writel(1 << bit, IC0_ASSIGNSET);
572		- }
573		-
574		- au1x_ic_settype(irq_nr, map[count].im_type);
575		- }
576		-}
577		-
578		-void __init arch_init_irq(void)
579		-{
580	555	int i;
581	556
582	557	/*
583	558
584	559
...	...	@@ -620,8 +595,44 @@
620	595	/*
621	596	* Initialize IC0, which is fixed per processor.
622	597	*/
623		- setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
	598	+ while (map->im_irq != -1) {
	599	+ irq_nr = map->im_irq;
624	600
	601	+ if (irq_nr >= AU1000_INTC1_INT_BASE) {
	602	+ bit = irq_nr - AU1000_INTC1_INT_BASE;
	603	+ if (map->im_request)
	604	+ au_writel(1 << bit, IC1_ASSIGNSET);
	605	+ } else {
	606	+ bit = irq_nr - AU1000_INTC0_INT_BASE;
	607	+ if (map->im_request)
	608	+ au_writel(1 << bit, IC0_ASSIGNSET);
	609	+ }
	610	+
	611	+ au1x_ic_settype(irq_nr, map->im_type);
	612	+ ++map;
	613	+ }
	614	+
625	615	set_c0_status(IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \| IE_IRQ3);
	616	+}
	617	+
	618	+void __init arch_init_irq(void)
	619	+{
	620	+ switch (alchemy_get_cputype()) {
	621	+ case ALCHEMY_CPU_AU1000:
	622	+ au1000_init_irq(au1000_irqmap);
	623	+ break;
	624	+ case ALCHEMY_CPU_AU1500:
	625	+ au1000_init_irq(au1500_irqmap);
	626	+ break;
	627	+ case ALCHEMY_CPU_AU1100:
	628	+ au1000_init_irq(au1100_irqmap);
	629	+ break;
	630	+ case ALCHEMY_CPU_AU1550:
	631	+ au1000_init_irq(au1550_irqmap);
	632	+ break;
	633	+ case ALCHEMY_CPU_AU1200:
	634	+ au1000_init_irq(au1200_irqmap);
	635	+ break;
	636	+ }
626	637	}