Commit f0dad6e701cb66301287074c39183c7312139530
Exists in
smarc-imx_3.14.28_1.0.0_ga
and in
1 other branch
Merge branch 'dma_complete' into next
Showing 30 changed files Side-by-side Diff
- crypto/async_tx/async_tx.c
- drivers/dma/amba-pl08x.c
- drivers/dma/at_hdmac.c
- drivers/dma/coh901318.c
- drivers/dma/cppi41.c
- drivers/dma/dma-jz4740.c
- drivers/dma/dmaengine.c
- drivers/dma/dmatest.c
- drivers/dma/dw/core.c
- drivers/dma/edma.c
- drivers/dma/imx-dma.c
- drivers/dma/imx-sdma.c
- drivers/dma/intel_mid_dma.c
- drivers/dma/ioat/dma.c
- drivers/dma/ioat/dma_v3.c
- drivers/dma/iop-adma.c
- drivers/dma/k3dma.c
- drivers/dma/mmp_tdma.c
- drivers/dma/mv_xor.c
- drivers/dma/mxs-dma.c
- drivers/dma/omap-dma.c
- drivers/dma/ppc4xx/adma.c
- drivers/dma/sa11x0-dma.c
- drivers/dma/sh/shdma-base.c
- drivers/dma/ste_dma40.c
- drivers/dma/tegra20-apb-dma.c
- drivers/dma/txx9dmac.c
- drivers/tty/serial/sh-sci.c
- include/linux/dmaengine.h
- net/ipv4/tcp.c
crypto/async_tx/async_tx.c
... | ... | @@ -128,7 +128,7 @@ |
128 | 128 | } |
129 | 129 | device->device_issue_pending(chan); |
130 | 130 | } else { |
131 | - if (dma_wait_for_async_tx(depend_tx) != DMA_SUCCESS) | |
131 | + if (dma_wait_for_async_tx(depend_tx) != DMA_COMPLETE) | |
132 | 132 | panic("%s: DMA error waiting for depend_tx\n", |
133 | 133 | __func__); |
134 | 134 | tx->tx_submit(tx); |
... | ... | @@ -280,7 +280,7 @@ |
280 | 280 | * we are referring to the correct operation |
281 | 281 | */ |
282 | 282 | BUG_ON(async_tx_test_ack(*tx)); |
283 | - if (dma_wait_for_async_tx(*tx) != DMA_SUCCESS) | |
283 | + if (dma_wait_for_async_tx(*tx) != DMA_COMPLETE) | |
284 | 284 | panic("%s: DMA error waiting for transaction\n", |
285 | 285 | __func__); |
286 | 286 | async_tx_ack(*tx); |
drivers/dma/amba-pl08x.c
... | ... | @@ -1252,7 +1252,7 @@ |
1252 | 1252 | size_t bytes = 0; |
1253 | 1253 | |
1254 | 1254 | ret = dma_cookie_status(chan, cookie, txstate); |
1255 | - if (ret == DMA_SUCCESS) | |
1255 | + if (ret == DMA_COMPLETE) | |
1256 | 1256 | return ret; |
1257 | 1257 | |
1258 | 1258 | /* |
... | ... | @@ -1267,7 +1267,7 @@ |
1267 | 1267 | |
1268 | 1268 | spin_lock_irqsave(&plchan->vc.lock, flags); |
1269 | 1269 | ret = dma_cookie_status(chan, cookie, txstate); |
1270 | - if (ret != DMA_SUCCESS) { | |
1270 | + if (ret != DMA_COMPLETE) { | |
1271 | 1271 | vd = vchan_find_desc(&plchan->vc, cookie); |
1272 | 1272 | if (vd) { |
1273 | 1273 | /* On the issued list, so hasn't been processed yet */ |
drivers/dma/at_hdmac.c
drivers/dma/coh901318.c
drivers/dma/cppi41.c
drivers/dma/dma-jz4740.c
drivers/dma/dmaengine.c
... | ... | @@ -1062,7 +1062,7 @@ |
1062 | 1062 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); |
1063 | 1063 | |
1064 | 1064 | if (!tx) |
1065 | - return DMA_SUCCESS; | |
1065 | + return DMA_COMPLETE; | |
1066 | 1066 | |
1067 | 1067 | while (tx->cookie == -EBUSY) { |
1068 | 1068 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { |
drivers/dma/dmatest.c
... | ... | @@ -740,7 +740,7 @@ |
740 | 740 | len, 0); |
741 | 741 | failed_tests++; |
742 | 742 | continue; |
743 | - } else if (status != DMA_SUCCESS) { | |
743 | + } else if (status != DMA_COMPLETE) { | |
744 | 744 | enum dmatest_error_type type = (status == DMA_ERROR) ? |
745 | 745 | DMATEST_ET_DMA_ERROR : DMATEST_ET_DMA_IN_PROGRESS; |
746 | 746 | thread_result_add(info, result, type, |
drivers/dma/dw/core.c
... | ... | @@ -1098,13 +1098,13 @@ |
1098 | 1098 | enum dma_status ret; |
1099 | 1099 | |
1100 | 1100 | ret = dma_cookie_status(chan, cookie, txstate); |
1101 | - if (ret == DMA_SUCCESS) | |
1101 | + if (ret == DMA_COMPLETE) | |
1102 | 1102 | return ret; |
1103 | 1103 | |
1104 | 1104 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
1105 | 1105 | |
1106 | 1106 | ret = dma_cookie_status(chan, cookie, txstate); |
1107 | - if (ret != DMA_SUCCESS) | |
1107 | + if (ret != DMA_COMPLETE) | |
1108 | 1108 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
1109 | 1109 | |
1110 | 1110 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
drivers/dma/edma.c
drivers/dma/imx-dma.c
... | ... | @@ -771,7 +771,7 @@ |
771 | 771 | desc->desc.tx_submit = imxdma_tx_submit; |
772 | 772 | /* txd.flags will be overwritten in prep funcs */ |
773 | 773 | desc->desc.flags = DMA_CTRL_ACK; |
774 | - desc->status = DMA_SUCCESS; | |
774 | + desc->status = DMA_COMPLETE; | |
775 | 775 | |
776 | 776 | list_add_tail(&desc->node, &imxdmac->ld_free); |
777 | 777 | imxdmac->descs_allocated++; |
drivers/dma/imx-sdma.c
drivers/dma/intel_mid_dma.c
... | ... | @@ -309,7 +309,7 @@ |
309 | 309 | callback_txd(param_txd); |
310 | 310 | } |
311 | 311 | if (midc->raw_tfr) { |
312 | - desc->status = DMA_SUCCESS; | |
312 | + desc->status = DMA_COMPLETE; | |
313 | 313 | if (desc->lli != NULL) { |
314 | 314 | pci_pool_free(desc->lli_pool, desc->lli, |
315 | 315 | desc->lli_phys); |
... | ... | @@ -481,7 +481,7 @@ |
481 | 481 | enum dma_status ret; |
482 | 482 | |
483 | 483 | ret = dma_cookie_status(chan, cookie, txstate); |
484 | - if (ret != DMA_SUCCESS) { | |
484 | + if (ret != DMA_COMPLETE) { | |
485 | 485 | spin_lock_bh(&midc->lock); |
486 | 486 | midc_scan_descriptors(to_middma_device(chan->device), midc); |
487 | 487 | spin_unlock_bh(&midc->lock); |
drivers/dma/ioat/dma.c
... | ... | @@ -733,7 +733,7 @@ |
733 | 733 | enum dma_status ret; |
734 | 734 | |
735 | 735 | ret = dma_cookie_status(c, cookie, txstate); |
736 | - if (ret == DMA_SUCCESS) | |
736 | + if (ret == DMA_COMPLETE) | |
737 | 737 | return ret; |
738 | 738 | |
739 | 739 | device->cleanup_fn((unsigned long) c); |
... | ... | @@ -859,7 +859,7 @@ |
859 | 859 | |
860 | 860 | if (tmo == 0 || |
861 | 861 | dma->device_tx_status(dma_chan, cookie, NULL) |
862 | - != DMA_SUCCESS) { | |
862 | + != DMA_COMPLETE) { | |
863 | 863 | dev_err(dev, "Self-test copy timed out, disabling\n"); |
864 | 864 | err = -ENODEV; |
865 | 865 | goto unmap_dma; |
drivers/dma/ioat/dma_v3.c
... | ... | @@ -807,7 +807,7 @@ |
807 | 807 | enum dma_status ret; |
808 | 808 | |
809 | 809 | ret = dma_cookie_status(c, cookie, txstate); |
810 | - if (ret == DMA_SUCCESS) | |
810 | + if (ret == DMA_COMPLETE) | |
811 | 811 | return ret; |
812 | 812 | |
813 | 813 | ioat3_cleanup(ioat); |
... | ... | @@ -1468,7 +1468,7 @@ |
1468 | 1468 | |
1469 | 1469 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
1470 | 1470 | |
1471 | - if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { | |
1471 | + if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { | |
1472 | 1472 | dev_err(dev, "Self-test xor timed out\n"); |
1473 | 1473 | err = -ENODEV; |
1474 | 1474 | goto dma_unmap; |
... | ... | @@ -1530,7 +1530,7 @@ |
1530 | 1530 | |
1531 | 1531 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
1532 | 1532 | |
1533 | - if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { | |
1533 | + if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { | |
1534 | 1534 | dev_err(dev, "Self-test validate timed out\n"); |
1535 | 1535 | err = -ENODEV; |
1536 | 1536 | goto dma_unmap; |
... | ... | @@ -1577,7 +1577,7 @@ |
1577 | 1577 | |
1578 | 1578 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
1579 | 1579 | |
1580 | - if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { | |
1580 | + if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { | |
1581 | 1581 | dev_err(dev, "Self-test 2nd validate timed out\n"); |
1582 | 1582 | err = -ENODEV; |
1583 | 1583 | goto dma_unmap; |
drivers/dma/iop-adma.c
... | ... | @@ -864,7 +864,7 @@ |
864 | 864 | int ret; |
865 | 865 | |
866 | 866 | ret = dma_cookie_status(chan, cookie, txstate); |
867 | - if (ret == DMA_SUCCESS) | |
867 | + if (ret == DMA_COMPLETE) | |
868 | 868 | return ret; |
869 | 869 | |
870 | 870 | iop_adma_slot_cleanup(iop_chan); |
... | ... | @@ -983,7 +983,7 @@ |
983 | 983 | msleep(1); |
984 | 984 | |
985 | 985 | if (iop_adma_status(dma_chan, cookie, NULL) != |
986 | - DMA_SUCCESS) { | |
986 | + DMA_COMPLETE) { | |
987 | 987 | dev_err(dma_chan->device->dev, |
988 | 988 | "Self-test copy timed out, disabling\n"); |
989 | 989 | err = -ENODEV; |
... | ... | @@ -1083,7 +1083,7 @@ |
1083 | 1083 | msleep(8); |
1084 | 1084 | |
1085 | 1085 | if (iop_adma_status(dma_chan, cookie, NULL) != |
1086 | - DMA_SUCCESS) { | |
1086 | + DMA_COMPLETE) { | |
1087 | 1087 | dev_err(dma_chan->device->dev, |
1088 | 1088 | "Self-test xor timed out, disabling\n"); |
1089 | 1089 | err = -ENODEV; |
... | ... | @@ -1129,7 +1129,7 @@ |
1129 | 1129 | iop_adma_issue_pending(dma_chan); |
1130 | 1130 | msleep(8); |
1131 | 1131 | |
1132 | - if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { | |
1132 | + if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { | |
1133 | 1133 | dev_err(dma_chan->device->dev, |
1134 | 1134 | "Self-test zero sum timed out, disabling\n"); |
1135 | 1135 | err = -ENODEV; |
... | ... | @@ -1158,7 +1158,7 @@ |
1158 | 1158 | iop_adma_issue_pending(dma_chan); |
1159 | 1159 | msleep(8); |
1160 | 1160 | |
1161 | - if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { | |
1161 | + if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { | |
1162 | 1162 | dev_err(dma_chan->device->dev, |
1163 | 1163 | "Self-test non-zero sum timed out, disabling\n"); |
1164 | 1164 | err = -ENODEV; |
... | ... | @@ -1254,7 +1254,7 @@ |
1254 | 1254 | msleep(8); |
1255 | 1255 | |
1256 | 1256 | if (iop_adma_status(dma_chan, cookie, NULL) != |
1257 | - DMA_SUCCESS) { | |
1257 | + DMA_COMPLETE) { | |
1258 | 1258 | dev_err(dev, "Self-test pq timed out, disabling\n"); |
1259 | 1259 | err = -ENODEV; |
1260 | 1260 | goto free_resources; |
... | ... | @@ -1291,7 +1291,7 @@ |
1291 | 1291 | msleep(8); |
1292 | 1292 | |
1293 | 1293 | if (iop_adma_status(dma_chan, cookie, NULL) != |
1294 | - DMA_SUCCESS) { | |
1294 | + DMA_COMPLETE) { | |
1295 | 1295 | dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n"); |
1296 | 1296 | err = -ENODEV; |
1297 | 1297 | goto free_resources; |
... | ... | @@ -1323,7 +1323,7 @@ |
1323 | 1323 | msleep(8); |
1324 | 1324 | |
1325 | 1325 | if (iop_adma_status(dma_chan, cookie, NULL) != |
1326 | - DMA_SUCCESS) { | |
1326 | + DMA_COMPLETE) { | |
1327 | 1327 | dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n"); |
1328 | 1328 | err = -ENODEV; |
1329 | 1329 | goto free_resources; |
drivers/dma/k3dma.c
drivers/dma/mmp_tdma.c
... | ... | @@ -163,7 +163,7 @@ |
163 | 163 | /* disable irq */ |
164 | 164 | writel(0, tdmac->reg_base + TDIMR); |
165 | 165 | |
166 | - tdmac->status = DMA_SUCCESS; | |
166 | + tdmac->status = DMA_COMPLETE; | |
167 | 167 | } |
168 | 168 | |
169 | 169 | static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac) |
... | ... | @@ -398,7 +398,7 @@ |
398 | 398 | int num_periods = buf_len / period_len; |
399 | 399 | int i = 0, buf = 0; |
400 | 400 | |
401 | - if (tdmac->status != DMA_SUCCESS) | |
401 | + if (tdmac->status != DMA_COMPLETE) | |
402 | 402 | return NULL; |
403 | 403 | |
404 | 404 | if (period_len > TDMA_MAX_XFER_BYTES) { |
... | ... | @@ -532,7 +532,7 @@ |
532 | 532 | tdmac->idx = idx; |
533 | 533 | tdmac->type = type; |
534 | 534 | tdmac->reg_base = (unsigned long)tdev->base + idx * 4; |
535 | - tdmac->status = DMA_SUCCESS; | |
535 | + tdmac->status = DMA_COMPLETE; | |
536 | 536 | tdev->tdmac[tdmac->idx] = tdmac; |
537 | 537 | tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); |
538 | 538 |
drivers/dma/mv_xor.c
... | ... | @@ -749,7 +749,7 @@ |
749 | 749 | enum dma_status ret; |
750 | 750 | |
751 | 751 | ret = dma_cookie_status(chan, cookie, txstate); |
752 | - if (ret == DMA_SUCCESS) { | |
752 | + if (ret == DMA_COMPLETE) { | |
753 | 753 | mv_xor_clean_completed_slots(mv_chan); |
754 | 754 | return ret; |
755 | 755 | } |
... | ... | @@ -874,7 +874,7 @@ |
874 | 874 | msleep(1); |
875 | 875 | |
876 | 876 | if (mv_xor_status(dma_chan, cookie, NULL) != |
877 | - DMA_SUCCESS) { | |
877 | + DMA_COMPLETE) { | |
878 | 878 | dev_err(dma_chan->device->dev, |
879 | 879 | "Self-test copy timed out, disabling\n"); |
880 | 880 | err = -ENODEV; |
... | ... | @@ -968,7 +968,7 @@ |
968 | 968 | msleep(8); |
969 | 969 | |
970 | 970 | if (mv_xor_status(dma_chan, cookie, NULL) != |
971 | - DMA_SUCCESS) { | |
971 | + DMA_COMPLETE) { | |
972 | 972 | dev_err(dma_chan->device->dev, |
973 | 973 | "Self-test xor timed out, disabling\n"); |
974 | 974 | err = -ENODEV; |
drivers/dma/mxs-dma.c
... | ... | @@ -224,7 +224,7 @@ |
224 | 224 | |
225 | 225 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) |
226 | 226 | { |
227 | - mxs_chan->status = DMA_SUCCESS; | |
227 | + mxs_chan->status = DMA_COMPLETE; | |
228 | 228 | } |
229 | 229 | |
230 | 230 | static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) |
231 | 231 | |
... | ... | @@ -312,12 +312,12 @@ |
312 | 312 | if (mxs_chan->flags & MXS_DMA_SG_LOOP) |
313 | 313 | mxs_chan->status = DMA_IN_PROGRESS; |
314 | 314 | else |
315 | - mxs_chan->status = DMA_SUCCESS; | |
315 | + mxs_chan->status = DMA_COMPLETE; | |
316 | 316 | } |
317 | 317 | |
318 | 318 | stat1 &= ~(1 << channel); |
319 | 319 | |
320 | - if (mxs_chan->status == DMA_SUCCESS) | |
320 | + if (mxs_chan->status == DMA_COMPLETE) | |
321 | 321 | dma_cookie_complete(&mxs_chan->desc); |
322 | 322 | |
323 | 323 | /* schedule tasklet on this channel */ |
drivers/dma/omap-dma.c
drivers/dma/ppc4xx/adma.c
... | ... | @@ -3891,7 +3891,7 @@ |
3891 | 3891 | |
3892 | 3892 | ppc440spe_chan = to_ppc440spe_adma_chan(chan); |
3893 | 3893 | ret = dma_cookie_status(chan, cookie, txstate); |
3894 | - if (ret == DMA_SUCCESS) | |
3894 | + if (ret == DMA_COMPLETE) | |
3895 | 3895 | return ret; |
3896 | 3896 | |
3897 | 3897 | ppc440spe_adma_slot_cleanup(ppc440spe_chan); |
drivers/dma/sa11x0-dma.c
drivers/dma/sh/shdma-base.c
... | ... | @@ -724,7 +724,7 @@ |
724 | 724 | * If we don't find cookie on the queue, it has been aborted and we have |
725 | 725 | * to report error |
726 | 726 | */ |
727 | - if (status != DMA_SUCCESS) { | |
727 | + if (status != DMA_COMPLETE) { | |
728 | 728 | struct shdma_desc *sdesc; |
729 | 729 | status = DMA_ERROR; |
730 | 730 | list_for_each_entry(sdesc, &schan->ld_queue, node) |
drivers/dma/ste_dma40.c
drivers/dma/tegra20-apb-dma.c
... | ... | @@ -570,7 +570,7 @@ |
570 | 570 | |
571 | 571 | list_del(&sgreq->node); |
572 | 572 | if (sgreq->last_sg) { |
573 | - dma_desc->dma_status = DMA_SUCCESS; | |
573 | + dma_desc->dma_status = DMA_COMPLETE; | |
574 | 574 | dma_cookie_complete(&dma_desc->txd); |
575 | 575 | if (!dma_desc->cb_count) |
576 | 576 | list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); |
... | ... | @@ -768,7 +768,7 @@ |
768 | 768 | unsigned int residual; |
769 | 769 | |
770 | 770 | ret = dma_cookie_status(dc, cookie, txstate); |
771 | - if (ret == DMA_SUCCESS) | |
771 | + if (ret == DMA_COMPLETE) | |
772 | 772 | return ret; |
773 | 773 | |
774 | 774 | spin_lock_irqsave(&tdc->lock, flags); |
drivers/dma/txx9dmac.c
... | ... | @@ -962,8 +962,8 @@ |
962 | 962 | enum dma_status ret; |
963 | 963 | |
964 | 964 | ret = dma_cookie_status(chan, cookie, txstate); |
965 | - if (ret == DMA_SUCCESS) | |
966 | - return DMA_SUCCESS; | |
965 | + if (ret == DMA_COMPLETE) | |
966 | + return DMA_COMPLETE; | |
967 | 967 | |
968 | 968 | spin_lock_bh(&dc->lock); |
969 | 969 | txx9dmac_scan_descriptors(dc); |
drivers/tty/serial/sh-sci.c
... | ... | @@ -1433,7 +1433,7 @@ |
1433 | 1433 | desc = s->desc_rx[new]; |
1434 | 1434 | |
1435 | 1435 | if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != |
1436 | - DMA_SUCCESS) { | |
1436 | + DMA_COMPLETE) { | |
1437 | 1437 | /* Handle incomplete DMA receive */ |
1438 | 1438 | struct dma_chan *chan = s->chan_rx; |
1439 | 1439 | struct shdma_desc *sh_desc = container_of(desc, |
include/linux/dmaengine.h
... | ... | @@ -45,13 +45,13 @@ |
45 | 45 | |
46 | 46 | /** |
47 | 47 | * enum dma_status - DMA transaction status |
48 | - * @DMA_SUCCESS: transaction completed successfully | |
48 | + * @DMA_COMPLETE: transaction completed | |
49 | 49 | * @DMA_IN_PROGRESS: transaction not yet processed |
50 | 50 | * @DMA_PAUSED: transaction is paused |
51 | 51 | * @DMA_ERROR: transaction failed |
52 | 52 | */ |
53 | 53 | enum dma_status { |
54 | - DMA_SUCCESS, | |
54 | + DMA_COMPLETE, | |
55 | 55 | DMA_IN_PROGRESS, |
56 | 56 | DMA_PAUSED, |
57 | 57 | DMA_ERROR, |
58 | 58 | |
... | ... | @@ -979,10 +979,10 @@ |
979 | 979 | { |
980 | 980 | if (last_complete <= last_used) { |
981 | 981 | if ((cookie <= last_complete) || (cookie > last_used)) |
982 | - return DMA_SUCCESS; | |
982 | + return DMA_COMPLETE; | |
983 | 983 | } else { |
984 | 984 | if ((cookie <= last_complete) && (cookie > last_used)) |
985 | - return DMA_SUCCESS; | |
985 | + return DMA_COMPLETE; | |
986 | 986 | } |
987 | 987 | return DMA_IN_PROGRESS; |
988 | 988 | } |
989 | 989 | |
... | ... | @@ -1013,11 +1013,11 @@ |
1013 | 1013 | } |
1014 | 1014 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) |
1015 | 1015 | { |
1016 | - return DMA_SUCCESS; | |
1016 | + return DMA_COMPLETE; | |
1017 | 1017 | } |
1018 | 1018 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
1019 | 1019 | { |
1020 | - return DMA_SUCCESS; | |
1020 | + return DMA_COMPLETE; | |
1021 | 1021 | } |
1022 | 1022 | static inline void dma_issue_pending_all(void) |
1023 | 1023 | { |
net/ipv4/tcp.c
... | ... | @@ -1429,7 +1429,7 @@ |
1429 | 1429 | do { |
1430 | 1430 | if (dma_async_is_tx_complete(tp->ucopy.dma_chan, |
1431 | 1431 | last_issued, &done, |
1432 | - &used) == DMA_SUCCESS) { | |
1432 | + &used) == DMA_COMPLETE) { | |
1433 | 1433 | /* Safe to free early-copied skbs now */ |
1434 | 1434 | __skb_queue_purge(&sk->sk_async_wait_queue); |
1435 | 1435 | break; |
... | ... | @@ -1437,7 +1437,7 @@ |
1437 | 1437 | struct sk_buff *skb; |
1438 | 1438 | while ((skb = skb_peek(&sk->sk_async_wait_queue)) && |
1439 | 1439 | (dma_async_is_complete(skb->dma_cookie, done, |
1440 | - used) == DMA_SUCCESS)) { | |
1440 | + used) == DMA_COMPLETE)) { | |
1441 | 1441 | __skb_dequeue(&sk->sk_async_wait_queue); |
1442 | 1442 | kfree_skb(skb); |
1443 | 1443 | } |