[MIPS] Fix configuration of R2 CPU features and multithreading.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

[MIPS] Fix configuration of R2 CPU features and multithreading.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle
1 parent e73ea273ef
Showing 3 changed files with 61 additions and 46 deletions Side-by-side Diff
arch/mips/Kconfig
arch/mips/kernel/traps.c
include/asm-mips/cpu-features.h
@@ -308,6 +308,7 @@
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
 	help
 	  This enables support for the MIPS Technologies Atlas evaluation
 	  board.
@@ -336,6 +337,7 @@
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_MULTITHREADING
 	help
 	  This enables support for the MIPS Technologies Malta evaluation
 	  board.
  
  
  
  
  
  
  
  
  
@@ -1495,34 +1497,57 @@
 config CPU_HAS_PREFETCH
 	bool
  
-config MIPS_MT
-	bool "Enable MIPS MT"
-	depends on CPU_MIPS32_R2
-	#depends on CPU_MIPS64_R2		# later ...
-
 choice
 	prompt "MIPS MT options"
-	depends on MIPS_MT
  
+config MIPS_MT_DISABLED
+	bool "Disable multithreading support."
+	help
+	  Use this option if your workload can't take advantage of
+	  MIPS hardware multithreading support.  On systems that don't have
+	  the option of an MT-enabled processor this option will be the only
+	  option in this menu.
+
 config MIPS_MT_SMTC
 	bool "SMTC: Use all TCs on all VPEs for SMP"
+	depends on CPU_MIPS32_R2
+	#depends on CPU_MIPS64_R2		# once there is hardware ...
+	depends on SYS_SUPPORTS_MULTITHREADING
 	select CPU_MIPSR2_IRQ_VI
 	select CPU_MIPSR2_SRS
+	select MIPS_MT
 	select SMP
+	help
+	  This is a kernel model which is known a SMTC or lately has been
+	  marketesed into SMVP.
  
 config MIPS_MT_SMP
 	bool "Use 1 TC on each available VPE for SMP"
+	depends on SYS_SUPPORTS_MULTITHREADING
+	select CPU_MIPSR2_IRQ_VI
+	select CPU_MIPSR2_SRS
+	select MIPS_MT
 	select SMP
+	help
+	  This is a kernel model which is also known a VSMP or lately
+	  has been marketesed into SMVP.
  
 config MIPS_VPE_LOADER
 	bool "VPE loader support."
-	depends on MIPS_MT
+	depends on SYS_SUPPORTS_MULTITHREADING
+	select MIPS_MT
 	help
 	  Includes a loader for loading an elf relocatable object
 	  onto another VPE and running it.
  
 endchoice
  
+config MIPS_MT
+	bool
+
+config SYS_SUPPORTS_MULTITHREADING
+	bool
+
 config MIPS_MT_FPAFF
 	bool "Dynamic FPU affinity for FP-intensive threads"
 	depends on MIPS_MT
  
  
  
  
  
@@ -1579,32 +1604,23 @@
 config CPU_HAS_WB
 	bool
  
+#
+# Vectored interrupt mode is an R2 feature
+#
 config CPU_MIPSR2_IRQ_VI
-	bool "Vectored interrupt mode"
-	depends on CPU_MIPSR2
-	help
-	   Vectored interrupt mode allowing faster dispatching of interrupts.
-	   The board support code needs to be written to take advantage of this
-	   mode.  Compatibility code is included to allow the kernel to run on
-	   a CPU that does not support vectored interrupts.  It's safe to
-	   say Y here.
+	bool
  
+#
+# Extended interrupt mode is an R2 feature
+#
 config CPU_MIPSR2_IRQ_EI
-	bool "External interrupt controller mode"
-	depends on CPU_MIPSR2
-	help
-	   Extended interrupt mode takes advantage of an external interrupt
-	   controller to allow fast dispatching from many possible interrupt
-	   sources. Say N unless you know that external interrupt support is
-	   required.
+	bool
  
+#
+# Shadow registers are an R2 feature
+#
 config CPU_MIPSR2_SRS
-	bool "Make shadow set registers available for interrupt handlers"
-	depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
-	help
-	   Allow the kernel to use shadow register sets for fast interrupts.
-	   Interrupt handlers must be specially written to use shadow sets.
-	   Say N unless you know that shadow register set upport is needed.
+	bool
  
 config CPU_HAS_SYNC
 	bool
@@ -1050,7 +1050,7 @@
 	return (void *)old_handler;
 }
  
-#ifdef CONFIG_CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2_SRS
 /*
  * MIPSR2 shadow register set allocation
  * FIXME: SMP...
  
@@ -1069,11 +1069,9 @@
  
 static void mips_srs_init(void)
 {
-#ifdef CONFIG_CPU_MIPSR2_SRS
 	shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
 	printk(KERN_INFO "%d MIPSR2 register sets available\n",
 	       shadow_registers.sr_supported);
-#endif
 	shadow_registers.sr_allocated = 1;	/* Set 0 used by kernel */
 }
  
  
@@ -1198,8 +1196,15 @@
 {
 	return set_vi_srs_handler(n, addr, 0);
 }
-#endif
  
+#else
+
+static inline void mips_srs_init(void)
+{
+}
+
+#endif /* CONFIG_CPU_MIPSR2_SRS */
+
 /*
  * This is used by native signal handling
  */
  
@@ -1388,9 +1393,7 @@
 	else
 		ebase = CAC_BASE;
  
-#ifdef CONFIG_CPU_MIPSR2
 	mips_srs_init();
-#endif
  
 	per_cpu_trap_init();
  
@@ -187,19 +187,15 @@
 # endif
 #endif
  
-#ifdef CONFIG_CPU_MIPSR2
-# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
-#  define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
-# else
-#  define cpu_has_vint			0
-# endif
-# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
-#  define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
-# else
-#  define cpu_has_veic			0
-# endif
-#else
+#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
+#elif !defined(cpu_has_vint)
 # define cpu_has_vint			0
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
+#elif !defined(cpu_has_veic)
 # define cpu_has_veic			0
 #endif
...	...	@@ -308,6 +308,7 @@
308	308	select SYS_SUPPORTS_64BIT_KERNEL
309	309	select SYS_SUPPORTS_BIG_ENDIAN
310	310	select SYS_SUPPORTS_LITTLE_ENDIAN
	311	+ select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
311	312	help
312	313	This enables support for the MIPS Technologies Atlas evaluation
313	314	board.
...	...	@@ -336,6 +337,7 @@
336	337	select SYS_SUPPORTS_64BIT_KERNEL
337	338	select SYS_SUPPORTS_BIG_ENDIAN
338	339	select SYS_SUPPORTS_LITTLE_ENDIAN
	340	+ select SYS_SUPPORTS_MULTITHREADING
339	341	help
340	342	This enables support for the MIPS Technologies Malta evaluation
341	343	board.
342	344
343	345
344	346
345	347
346	348
347	349
348	350
349	351
350	352
...	...	@@ -1495,34 +1497,57 @@
1495	1497	config CPU_HAS_PREFETCH
1496	1498	bool
1497	1499
1498		-config MIPS_MT
1499		- bool "Enable MIPS MT"
1500		- depends on CPU_MIPS32_R2
1501		- #depends on CPU_MIPS64_R2 # later ...
1502		-
1503	1500	choice
1504	1501	prompt "MIPS MT options"
1505		- depends on MIPS_MT
1506	1502
	1503	+config MIPS_MT_DISABLED
	1504	+ bool "Disable multithreading support."
	1505	+ help
	1506	+ Use this option if your workload can't take advantage of
	1507	+ MIPS hardware multithreading support. On systems that don't have
	1508	+ the option of an MT-enabled processor this option will be the only
	1509	+ option in this menu.
	1510	+
1507	1511	config MIPS_MT_SMTC
1508	1512	bool "SMTC: Use all TCs on all VPEs for SMP"
	1513	+ depends on CPU_MIPS32_R2
	1514	+ #depends on CPU_MIPS64_R2 # once there is hardware ...
	1515	+ depends on SYS_SUPPORTS_MULTITHREADING
1509	1516	select CPU_MIPSR2_IRQ_VI
1510	1517	select CPU_MIPSR2_SRS
	1518	+ select MIPS_MT
1511	1519	select SMP
	1520	+ help
	1521	+ This is a kernel model which is known a SMTC or lately has been
	1522	+ marketesed into SMVP.
1512	1523
1513	1524	config MIPS_MT_SMP
1514	1525	bool "Use 1 TC on each available VPE for SMP"
	1526	+ depends on SYS_SUPPORTS_MULTITHREADING
	1527	+ select CPU_MIPSR2_IRQ_VI
	1528	+ select CPU_MIPSR2_SRS
	1529	+ select MIPS_MT
1515	1530	select SMP
	1531	+ help
	1532	+ This is a kernel model which is also known a VSMP or lately
	1533	+ has been marketesed into SMVP.
1516	1534
1517	1535	config MIPS_VPE_LOADER
1518	1536	bool "VPE loader support."
1519		- depends on MIPS_MT
	1537	+ depends on SYS_SUPPORTS_MULTITHREADING
	1538	+ select MIPS_MT
1520	1539	help
1521	1540	Includes a loader for loading an elf relocatable object
1522	1541	onto another VPE and running it.
1523	1542
1524	1543	endchoice
1525	1544
	1545	+config MIPS_MT
	1546	+ bool
	1547	+
	1548	+config SYS_SUPPORTS_MULTITHREADING
	1549	+ bool
	1550	+
1526	1551	config MIPS_MT_FPAFF
1527	1552	bool "Dynamic FPU affinity for FP-intensive threads"
1528	1553	depends on MIPS_MT
1529	1554
1530	1555
1531	1556
1532	1557
1533	1558
...	...	@@ -1579,32 +1604,23 @@
1579	1604	config CPU_HAS_WB
1580	1605	bool
1581	1606
	1607	+#
	1608	+# Vectored interrupt mode is an R2 feature
	1609	+#
1582	1610	config CPU_MIPSR2_IRQ_VI
1583		- bool "Vectored interrupt mode"
1584		- depends on CPU_MIPSR2
1585		- help
1586		- Vectored interrupt mode allowing faster dispatching of interrupts.
1587		- The board support code needs to be written to take advantage of this
1588		- mode. Compatibility code is included to allow the kernel to run on
1589		- a CPU that does not support vectored interrupts. It's safe to
1590		- say Y here.
	1611	+ bool
1591	1612
	1613	+#
	1614	+# Extended interrupt mode is an R2 feature
	1615	+#
1592	1616	config CPU_MIPSR2_IRQ_EI
1593		- bool "External interrupt controller mode"
1594		- depends on CPU_MIPSR2
1595		- help
1596		- Extended interrupt mode takes advantage of an external interrupt
1597		- controller to allow fast dispatching from many possible interrupt
1598		- sources. Say N unless you know that external interrupt support is
1599		- required.
	1617	+ bool
1600	1618
	1619	+#
	1620	+# Shadow registers are an R2 feature
	1621	+#
1601	1622	config CPU_MIPSR2_SRS
1602		- bool "Make shadow set registers available for interrupt handlers"
1603		- depends on CPU_MIPSR2_IRQ_VI \|\| CPU_MIPSR2_IRQ_EI
1604		- help
1605		- Allow the kernel to use shadow register sets for fast interrupts.
1606		- Interrupt handlers must be specially written to use shadow sets.
1607		- Say N unless you know that shadow register set upport is needed.
	1623	+ bool
1608	1624
1609	1625	config CPU_HAS_SYNC
1610	1626	bool
...	...	@@ -1050,7 +1050,7 @@
1050	1050	return (void *)old_handler;
1051	1051	}
1052	1052
1053		-#ifdef CONFIG_CPU_MIPSR2
	1053	+#ifdef CONFIG_CPU_MIPSR2_SRS
1054	1054	/*
1055	1055	* MIPSR2 shadow register set allocation
1056	1056	* FIXME: SMP...
1057	1057
...	...	@@ -1069,11 +1069,9 @@
1069	1069
1070	1070	static void mips_srs_init(void)
1071	1071	{
1072		-#ifdef CONFIG_CPU_MIPSR2_SRS
1073	1072	shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1074	1073	printk(KERN_INFO "%d MIPSR2 register sets available\n",
1075	1074	shadow_registers.sr_supported);
1076		-#endif
1077	1075	shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1078	1076	}
1079	1077
1080	1078
...	...	@@ -1198,8 +1196,15 @@
1198	1196	{
1199	1197	return set_vi_srs_handler(n, addr, 0);
1200	1198	}
1201		-#endif
1202	1199
	1200	+#else
	1201	+
	1202	+static inline void mips_srs_init(void)
	1203	+{
	1204	+}
	1205	+
	1206	+#endif /* CONFIG_CPU_MIPSR2_SRS */
	1207	+
1203	1208	/*
1204	1209	* This is used by native signal handling
1205	1210	*/
1206	1211
...	...	@@ -1388,9 +1393,7 @@
1388	1393	else
1389	1394	ebase = CAC_BASE;
1390	1395
1391		-#ifdef CONFIG_CPU_MIPSR2
1392	1396	mips_srs_init();
1393		-#endif
1394	1397
1395	1398	per_cpu_trap_init();
1396	1399
...	...	@@ -187,19 +187,15 @@
187	187	# endif
188	188	#endif
189	189
190		-#ifdef CONFIG_CPU_MIPSR2
191		-# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
192		-# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
193		-# else
194		-# define cpu_has_vint 0
195		-# endif
196		-# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
197		-# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
198		-# else
199		-# define cpu_has_veic 0
200		-# endif
201		-#else
	190	+#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
	191	+# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
	192	+#elif !defined(cpu_has_vint)
202	193	# define cpu_has_vint 0
	194	+#endif
	195	+
	196	+#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
	197	+# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
	198	+#elif !defined(cpu_has_veic)
203	199	# define cpu_has_veic 0
204	200	#endif
205	201