Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit f468400664e3ae79e6e001bb2820c79bebe6aa41

Authored by Dave Airlie 2013-05-02 15:33:25 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

Add GK110 modesetting suport.

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nve0: recognise nvf0 as a kepler board (GK110)
  drm/nouveau: force noaccel when no PFIFO support present
  drm/nvf0/disp: expose display class 2.2

Showing 9 changed files Inline Diff

drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/core/engine/device/base.c
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
drivers/gpu/drm/nouveau/core/include/core/class.h
drivers/gpu/drm/nouveau/core/include/engine/disp.h
drivers/gpu/drm/nouveau/nouveau_drm.c
drivers/gpu/drm/nouveau/nv50_display.c

drivers/gpu/drm/nouveau/Makefile

Diff comments View file @ f468400

 #
 # Makefile for the drm device driver.  This driver provides support for the
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 ccflags-y := -Iinclude/drm
 ccflags-y += -I$(src)/core/include
 ccflags-y += -I$(src)/core
 ccflags-y += -I$(src)
 nouveau-y := core/core/client.o
 nouveau-y += core/core/engctx.o
 nouveau-y += core/core/engine.o
 nouveau-y += core/core/enum.o
 nouveau-y += core/core/event.o
 nouveau-y += core/core/falcon.o
 nouveau-y += core/core/gpuobj.o
 nouveau-y += core/core/handle.o
 nouveau-y += core/core/mm.o
 nouveau-y += core/core/namedb.o
 nouveau-y += core/core/object.o
 nouveau-y += core/core/option.o
 nouveau-y += core/core/parent.o
 nouveau-y += core/core/printk.o
 nouveau-y += core/core/ramht.o
 nouveau-y += core/core/subdev.o
 nouveau-y += core/subdev/bar/base.o
 nouveau-y += core/subdev/bar/nv50.o
 nouveau-y += core/subdev/bar/nvc0.o
 nouveau-y += core/subdev/bios/base.o
 nouveau-y += core/subdev/bios/bit.o
 nouveau-y += core/subdev/bios/conn.o
 nouveau-y += core/subdev/bios/dcb.o
 nouveau-y += core/subdev/bios/disp.o
 nouveau-y += core/subdev/bios/dp.o
 nouveau-y += core/subdev/bios/extdev.o
 nouveau-y += core/subdev/bios/gpio.o
 nouveau-y += core/subdev/bios/i2c.o
 nouveau-y += core/subdev/bios/init.o
 nouveau-y += core/subdev/bios/mxm.o
 nouveau-y += core/subdev/bios/perf.o
 nouveau-y += core/subdev/bios/pll.o
 nouveau-y += core/subdev/bios/therm.o
 nouveau-y += core/subdev/bios/xpio.o
 nouveau-y += core/subdev/bus/nv04.o
 nouveau-y += core/subdev/bus/nv31.o
 nouveau-y += core/subdev/bus/nv50.o
 nouveau-y += core/subdev/bus/nvc0.o
 nouveau-y += core/subdev/clock/nv04.o
 nouveau-y += core/subdev/clock/nv40.o
 nouveau-y += core/subdev/clock/nv50.o
 nouveau-y += core/subdev/clock/nva3.o
 nouveau-y += core/subdev/clock/nvc0.o
 nouveau-y += core/subdev/clock/pllnv04.o
 nouveau-y += core/subdev/clock/pllnva3.o
 nouveau-y += core/subdev/devinit/base.o
 nouveau-y += core/subdev/devinit/nv04.o
 nouveau-y += core/subdev/devinit/nv05.o
 nouveau-y += core/subdev/devinit/nv10.o
 nouveau-y += core/subdev/devinit/nv1a.o
 nouveau-y += core/subdev/devinit/nv20.o
 nouveau-y += core/subdev/devinit/nv50.o
 nouveau-y += core/subdev/fb/base.o
 nouveau-y += core/subdev/fb/nv04.o
 nouveau-y += core/subdev/fb/nv10.o
 nouveau-y += core/subdev/fb/nv1a.o
 nouveau-y += core/subdev/fb/nv20.o
 nouveau-y += core/subdev/fb/nv25.o
 nouveau-y += core/subdev/fb/nv30.o
 nouveau-y += core/subdev/fb/nv35.o
 nouveau-y += core/subdev/fb/nv36.o
 nouveau-y += core/subdev/fb/nv40.o
 nouveau-y += core/subdev/fb/nv41.o
 nouveau-y += core/subdev/fb/nv44.o
 nouveau-y += core/subdev/fb/nv46.o
 nouveau-y += core/subdev/fb/nv47.o
 nouveau-y += core/subdev/fb/nv49.o
 nouveau-y += core/subdev/fb/nv4e.o
 nouveau-y += core/subdev/fb/nv50.o
 nouveau-y += core/subdev/fb/nvc0.o
 nouveau-y += core/subdev/gpio/base.o
 nouveau-y += core/subdev/gpio/nv10.o
 nouveau-y += core/subdev/gpio/nv50.o
 nouveau-y += core/subdev/gpio/nvd0.o
 nouveau-y += core/subdev/gpio/nve0.o
 nouveau-y += core/subdev/i2c/base.o
 nouveau-y += core/subdev/i2c/anx9805.o
 nouveau-y += core/subdev/i2c/aux.o
 nouveau-y += core/subdev/i2c/bit.o
 nouveau-y += core/subdev/i2c/nv04.o
 nouveau-y += core/subdev/i2c/nv4e.o
 nouveau-y += core/subdev/i2c/nv50.o
 nouveau-y += core/subdev/i2c/nv94.o
 nouveau-y += core/subdev/i2c/nvd0.o
 nouveau-y += core/subdev/ibus/nvc0.o
 nouveau-y += core/subdev/ibus/nve0.o
 nouveau-y += core/subdev/instmem/base.o
 nouveau-y += core/subdev/instmem/nv04.o
 nouveau-y += core/subdev/instmem/nv40.o
 nouveau-y += core/subdev/instmem/nv50.o
 nouveau-y += core/subdev/ltcg/nvc0.o
 nouveau-y += core/subdev/mc/base.o
 nouveau-y += core/subdev/mc/nv04.o
 nouveau-y += core/subdev/mc/nv44.o
 nouveau-y += core/subdev/mc/nv50.o
 nouveau-y += core/subdev/mc/nv98.o
 nouveau-y += core/subdev/mc/nvc0.o
 nouveau-y += core/subdev/mxm/base.o
 nouveau-y += core/subdev/mxm/mxms.o
 nouveau-y += core/subdev/mxm/nv50.o
 nouveau-y += core/subdev/therm/base.o
 nouveau-y += core/subdev/therm/fan.o
 nouveau-y += core/subdev/therm/fannil.o
 nouveau-y += core/subdev/therm/fanpwm.o
 nouveau-y += core/subdev/therm/fantog.o
 nouveau-y += core/subdev/therm/ic.o
 nouveau-y += core/subdev/therm/temp.o
 nouveau-y += core/subdev/therm/nv40.o
 nouveau-y += core/subdev/therm/nv50.o
 nouveau-y += core/subdev/therm/nv84.o
 nouveau-y += core/subdev/therm/nva3.o
 nouveau-y += core/subdev/therm/nvd0.o
 nouveau-y += core/subdev/timer/base.o
 nouveau-y += core/subdev/timer/nv04.o
 nouveau-y += core/subdev/vm/base.o
 nouveau-y += core/subdev/vm/nv04.o
 nouveau-y += core/subdev/vm/nv41.o
 nouveau-y += core/subdev/vm/nv44.o
 nouveau-y += core/subdev/vm/nv50.o
 nouveau-y += core/subdev/vm/nvc0.o
 nouveau-y += core/engine/dmaobj/base.o
 nouveau-y += core/engine/dmaobj/nv04.o
 nouveau-y += core/engine/dmaobj/nv50.o
 nouveau-y += core/engine/dmaobj/nvc0.o
 nouveau-y += core/engine/dmaobj/nvd0.o
 nouveau-y += core/engine/bsp/nv84.o
 nouveau-y += core/engine/bsp/nvc0.o
 nouveau-y += core/engine/bsp/nve0.o
 nouveau-y += core/engine/copy/nva3.o
 nouveau-y += core/engine/copy/nvc0.o
 nouveau-y += core/engine/copy/nve0.o
 nouveau-y += core/engine/crypt/nv84.o
 nouveau-y += core/engine/crypt/nv98.o
 nouveau-y += core/engine/device/base.o
 nouveau-y += core/engine/device/nv04.o
 nouveau-y += core/engine/device/nv10.o
 nouveau-y += core/engine/device/nv20.o
 nouveau-y += core/engine/device/nv30.o
 nouveau-y += core/engine/device/nv40.o
 nouveau-y += core/engine/device/nv50.o
 nouveau-y += core/engine/device/nvc0.o
 nouveau-y += core/engine/device/nve0.o
 nouveau-y += core/engine/disp/base.o
 nouveau-y += core/engine/disp/nv04.o
 nouveau-y += core/engine/disp/nv50.o
 nouveau-y += core/engine/disp/nv84.o
 nouveau-y += core/engine/disp/nv94.o
 nouveau-y += core/engine/disp/nva0.o
 nouveau-y += core/engine/disp/nva3.o
 nouveau-y += core/engine/disp/nvd0.o
 nouveau-y += core/engine/disp/nve0.o
+nouveau-y += core/engine/disp/nvf0.o
 nouveau-y += core/engine/disp/dacnv50.o
 nouveau-y += core/engine/disp/dport.o
 nouveau-y += core/engine/disp/hdanva3.o
 nouveau-y += core/engine/disp/hdanvd0.o
 nouveau-y += core/engine/disp/hdminv84.o
 nouveau-y += core/engine/disp/hdminva3.o
 nouveau-y += core/engine/disp/hdminvd0.o
 nouveau-y += core/engine/disp/piornv50.o
 nouveau-y += core/engine/disp/sornv50.o
 nouveau-y += core/engine/disp/sornv94.o
 nouveau-y += core/engine/disp/sornvd0.o
 nouveau-y += core/engine/disp/vga.o
 nouveau-y += core/engine/fifo/base.o
 nouveau-y += core/engine/fifo/nv04.o
 nouveau-y += core/engine/fifo/nv10.o
 nouveau-y += core/engine/fifo/nv17.o
 nouveau-y += core/engine/fifo/nv40.o
 nouveau-y += core/engine/fifo/nv50.o
 nouveau-y += core/engine/fifo/nv84.o
 nouveau-y += core/engine/fifo/nvc0.o
 nouveau-y += core/engine/fifo/nve0.o
 nouveau-y += core/engine/graph/ctxnv40.o
 nouveau-y += core/engine/graph/ctxnv50.o
 nouveau-y += core/engine/graph/ctxnvc0.o
 nouveau-y += core/engine/graph/ctxnve0.o
 nouveau-y += core/engine/graph/nv04.o
 nouveau-y += core/engine/graph/nv10.o
 nouveau-y += core/engine/graph/nv20.o
 nouveau-y += core/engine/graph/nv25.o
 nouveau-y += core/engine/graph/nv2a.o
 nouveau-y += core/engine/graph/nv30.o
 nouveau-y += core/engine/graph/nv34.o
 nouveau-y += core/engine/graph/nv35.o
 nouveau-y += core/engine/graph/nv40.o
 nouveau-y += core/engine/graph/nv50.o
 nouveau-y += core/engine/graph/nvc0.o
 nouveau-y += core/engine/graph/nve0.o
 nouveau-y += core/engine/mpeg/nv31.o
 nouveau-y += core/engine/mpeg/nv40.o
 nouveau-y += core/engine/mpeg/nv50.o
 nouveau-y += core/engine/mpeg/nv84.o
 nouveau-y += core/engine/ppp/nv98.o
 nouveau-y += core/engine/ppp/nvc0.o
 nouveau-y += core/engine/software/nv04.o
 nouveau-y += core/engine/software/nv10.o
 nouveau-y += core/engine/software/nv50.o
 nouveau-y += core/engine/software/nvc0.o
 nouveau-y += core/engine/vp/nv84.o
 nouveau-y += core/engine/vp/nvc0.o
 nouveau-y += core/engine/vp/nve0.o
 # drm/core
 nouveau-y += nouveau_drm.o nouveau_chan.o nouveau_dma.o nouveau_fence.o
 nouveau-y += nouveau_vga.o nouveau_agp.o
 nouveau-y += nouveau_ttm.o nouveau_sgdma.o nouveau_bo.o nouveau_gem.o
 nouveau-y += nouveau_prime.o nouveau_abi16.o
 nouveau-y += nv04_fence.o nv10_fence.o nv17_fence.o
 nouveau-y += nv50_fence.o nv84_fence.o nvc0_fence.o
 # drm/kms
 nouveau-y += nouveau_bios.o nouveau_fbcon.o nouveau_display.o
 nouveau-y += nouveau_connector.o nouveau_dp.o
 nouveau-y += nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o
 # drm/kms/nv04:nv50
 include $(src)/dispnv04/Makefile
 # drm/kms/nv50-
 nouveau-y += nv50_display.o
 # drm/pm
 nouveau-y += nouveau_pm.o nouveau_volt.o nouveau_perf.o
 nouveau-y += nv04_pm.o nv40_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o
 nouveau-y += nouveau_mem.o
 # other random bits
 nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
 ifdef CONFIG_X86
 nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
 endif
 nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o
 nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
 obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o

drivers/gpu/drm/nouveau/core/engine/device/base.c

Diff comments View file @ f468400

 /*
  * Copyright 2012 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Ben Skeggs
  */
 #include <core/object.h>
 #include <core/device.h>
 #include <core/client.h>
 #include <core/option.h>
 #include <core/class.h>
 #include <engine/device.h>
 static DEFINE_MUTEX(nv_devices_mutex);
 static LIST_HEAD(nv_devices);
 struct nouveau_device *
 nouveau_device_find(u64 name)
 {
 	struct nouveau_device *device, *match = NULL;
 	mutex_lock(&nv_devices_mutex);
 	list_for_each_entry(device, &nv_devices, head) {
 		if (device->handle == name) {
 			match = device;
 			break;
 		}
 	}
 	mutex_unlock(&nv_devices_mutex);
 	return match;
 }
 /******************************************************************************
  * nouveau_devobj (0x0080): class implementation
  *****************************************************************************/
 struct nouveau_devobj {
 	struct nouveau_parent base;
 	struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
 };
 static const u64 disable_map[] = {
 	[NVDEV_SUBDEV_VBIOS]	= NV_DEVICE_DISABLE_VBIOS,
 	[NVDEV_SUBDEV_DEVINIT]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_GPIO]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_I2C]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_CLOCK]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_MXM]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_MC]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_BUS]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_TIMER]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_FB]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_LTCG]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_IBUS]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_INSTMEM]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_VM]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_BAR]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_VOLT]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_SUBDEV_THERM]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_ENGINE_DMAOBJ]	= NV_DEVICE_DISABLE_CORE,
 	[NVDEV_ENGINE_FIFO]	= NV_DEVICE_DISABLE_FIFO,
 	[NVDEV_ENGINE_SW]	= NV_DEVICE_DISABLE_FIFO,
 	[NVDEV_ENGINE_GR]	= NV_DEVICE_DISABLE_GRAPH,
 	[NVDEV_ENGINE_MPEG]	= NV_DEVICE_DISABLE_MPEG,
 	[NVDEV_ENGINE_ME]	= NV_DEVICE_DISABLE_ME,
 	[NVDEV_ENGINE_VP]	= NV_DEVICE_DISABLE_VP,
 	[NVDEV_ENGINE_CRYPT]	= NV_DEVICE_DISABLE_CRYPT,
 	[NVDEV_ENGINE_BSP]	= NV_DEVICE_DISABLE_BSP,
 	[NVDEV_ENGINE_PPP]	= NV_DEVICE_DISABLE_PPP,
 	[NVDEV_ENGINE_COPY0]	= NV_DEVICE_DISABLE_COPY0,
 	[NVDEV_ENGINE_COPY1]	= NV_DEVICE_DISABLE_COPY1,
 	[NVDEV_ENGINE_UNK1C1]	= NV_DEVICE_DISABLE_UNK1C1,
 	[NVDEV_ENGINE_VENC]	= NV_DEVICE_DISABLE_VENC,
 	[NVDEV_ENGINE_DISP]	= NV_DEVICE_DISABLE_DISP,
 	[NVDEV_SUBDEV_NR]	= 0,
 };
 static int
 nouveau_devobj_ctor(struct nouveau_object *parent,
 		    struct nouveau_object *engine,
 		    struct nouveau_oclass *oclass, void *data, u32 size,
 		    struct nouveau_object **pobject)
 {
 	struct nouveau_client *client = nv_client(parent);
 	struct nouveau_device *device;
 	struct nouveau_devobj *devobj;
 	struct nv_device_class *args = data;
 	u32 boot0, strap;
 	u64 disable, mmio_base, mmio_size;
 	void __iomem *map;
 	int ret, i, c;
 	if (size < sizeof(struct nv_device_class))
 		return -EINVAL;
 	/* find the device subdev that matches what the client requested */
 	device = nv_device(client->device);
 	if (args->device != ~0) {
 		device = nouveau_device_find(args->device);
 		if (!device)
 			return -ENODEV;
 	}
 	ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL,
 				    (1ULL << NVDEV_ENGINE_DMAOBJ) |
 				    (1ULL << NVDEV_ENGINE_FIFO) |
 				    (1ULL << NVDEV_ENGINE_DISP), &devobj);
 	*pobject = nv_object(devobj);
 	if (ret)
 		return ret;
 	mmio_base = pci_resource_start(device->pdev, 0);
 	mmio_size = pci_resource_len(device->pdev, 0);
 	/* translate api disable mask into internal mapping */
 	disable = args->debug0;
 	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
 		if (args->disable & disable_map[i])
 			disable |= (1ULL << i);
 	}
 	/* identify the chipset, and determine classes of subdev/engines */
 	if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) &&
 	    !device->card_type) {
 		map = ioremap(mmio_base, 0x102000);
 		if (map == NULL)
 			return -ENOMEM;
 		/* switch mmio to cpu's native endianness */
 #ifndef __BIG_ENDIAN
 		if (ioread32_native(map + 0x000004) != 0x00000000)
 #else
 		if (ioread32_native(map + 0x000004) == 0x00000000)
 #endif
 			iowrite32_native(0x01000001, map + 0x000004);
 		/* read boot0 and strapping information */
 		boot0 = ioread32_native(map + 0x000000);
 		strap = ioread32_native(map + 0x101000);
 		iounmap(map);
 		/* determine chipset and derive architecture from it */
 		if ((boot0 & 0x0f000000) > 0) {
 			device->chipset = (boot0 & 0xff00000) >> 20;
 			switch (device->chipset & 0xf0) {
 			case 0x10: device->card_type = NV_10; break;
 			case 0x20: device->card_type = NV_20; break;
 			case 0x30: device->card_type = NV_30; break;
 			case 0x40:
 			case 0x60: device->card_type = NV_40; break;
 			case 0x50:
 			case 0x80:
 			case 0x90:
 			case 0xa0: device->card_type = NV_50; break;
 			case 0xc0: device->card_type = NV_C0; break;
 			case 0xd0: device->card_type = NV_D0; break;
-			case 0xe0: device->card_type = NV_E0; break;
+			case 0xe0:
+			case 0xf0: device->card_type = NV_E0; break;
 			default:
 				break;
 			}
 		} else
 		if ((boot0 & 0xff00fff0) == 0x20004000) {
 			if (boot0 & 0x00f00000)
 				device->chipset = 0x05;
 			else
 				device->chipset = 0x04;
 			device->card_type = NV_04;
 		}
 		switch (device->card_type) {
 		case NV_04: ret = nv04_identify(device); break;
 		case NV_10: ret = nv10_identify(device); break;
 		case NV_20: ret = nv20_identify(device); break;
 		case NV_30: ret = nv30_identify(device); break;
 		case NV_40: ret = nv40_identify(device); break;
 		case NV_50: ret = nv50_identify(device); break;
 		case NV_C0:
 		case NV_D0: ret = nvc0_identify(device); break;
 		case NV_E0: ret = nve0_identify(device); break;
 		default:
 			ret = -EINVAL;
 			break;
 		}
 		if (ret) {
 			nv_error(device, "unknown chipset, 0x%08x\n", boot0);
 			return ret;
 		}
 		nv_info(device, "BOOT0  : 0x%08x\n", boot0);
 		nv_info(device, "Chipset: %s (NV%02X)\n",
 			device->cname, device->chipset);
 		nv_info(device, "Family : NV%02X\n", device->card_type);
 		/* determine frequency of timing crystal */
 		if ( device->chipset < 0x17 ||
 		    (device->chipset >= 0x20 && device->chipset < 0x25))
 			strap &= 0x00000040;
 		else
 			strap &= 0x00400040;
 		switch (strap) {
 		case 0x00000000: device->crystal = 13500; break;
 		case 0x00000040: device->crystal = 14318; break;
 		case 0x00400000: device->crystal = 27000; break;
 		case 0x00400040: device->crystal = 25000; break;
 		}
 		nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
 	}
 	if (!(args->disable & NV_DEVICE_DISABLE_MMIO) &&
 	    !nv_subdev(device)->mmio) {
 		nv_subdev(device)->mmio  = ioremap(mmio_base, mmio_size);
 		if (!nv_subdev(device)->mmio) {
 			nv_error(device, "unable to map device registers\n");
 			return -ENOMEM;
 		}
 	}
 	/* ensure requested subsystems are available for use */
 	for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) {
 		if (!(oclass = device->oclass[i]) || (disable & (1ULL << i)))
 			continue;
 		if (device->subdev[i]) {
 			nouveau_object_ref(device->subdev[i],
 					  &devobj->subdev[i]);
 			continue;
 		}
 		ret = nouveau_object_ctor(nv_object(device), NULL,
 					  oclass, NULL, i,
 					  &devobj->subdev[i]);
 		if (ret == -ENODEV)
 			continue;
 		if (ret)
 			return ret;
 		/* note: can't init *any* subdevs until devinit has been run
 		 * due to not knowing exactly what the vbios init tables will
 		 * mess with.  devinit also can't be run until all of its
 		 * dependencies have been created.
 		 *
 		 * this code delays init of any subdev until all of devinit's
 		 * dependencies have been created, and then initialises each
 		 * subdev in turn as they're created.
 		 */
 		while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
 			struct nouveau_object *subdev = devobj->subdev[c++];
 			if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
 				ret = nouveau_object_inc(subdev);
 				if (ret)
 					return ret;
 				atomic_dec(&nv_object(device)->usecount);
 			} else
 			if (subdev) {
 				nouveau_subdev_reset(subdev);
 			}
 		}
 	}
 	return 0;
 }
 static void
 nouveau_devobj_dtor(struct nouveau_object *object)
 {
 	struct nouveau_devobj *devobj = (void *)object;
 	int i;
 	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
 		nouveau_object_ref(NULL, &devobj->subdev[i]);
 	nouveau_parent_destroy(&devobj->base);
 }
 static u8
 nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
 {
 	return nv_rd08(object->engine, addr);
 }
 static u16
 nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
 {
 	return nv_rd16(object->engine, addr);
 }
 static u32
 nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
 {
 	return nv_rd32(object->engine, addr);
 }
 static void
 nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
 {
 	nv_wr08(object->engine, addr, data);
 }
 static void
 nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
 {
 	nv_wr16(object->engine, addr, data);
 }
 static void
 nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
 {
 	nv_wr32(object->engine, addr, data);
 }
 static struct nouveau_ofuncs
 nouveau_devobj_ofuncs = {
 	.ctor = nouveau_devobj_ctor,
 	.dtor = nouveau_devobj_dtor,
 	.init = _nouveau_parent_init,
 	.fini = _nouveau_parent_fini,
 	.rd08 = nouveau_devobj_rd08,
 	.rd16 = nouveau_devobj_rd16,
 	.rd32 = nouveau_devobj_rd32,
 	.wr08 = nouveau_devobj_wr08,
 	.wr16 = nouveau_devobj_wr16,
 	.wr32 = nouveau_devobj_wr32,
 };
 /******************************************************************************
  * nouveau_device: engine functions
  *****************************************************************************/
 static struct nouveau_oclass
 nouveau_device_sclass[] = {
 	{ 0x0080, &nouveau_devobj_ofuncs },
 	{}
 };
 static int
 nouveau_device_fini(struct nouveau_object *object, bool suspend)
 {
 	struct nouveau_device *device = (void *)object;
 	struct nouveau_object *subdev;
 	int ret, i;
 	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
 		if ((subdev = device->subdev[i])) {
 			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
 				ret = nouveau_object_dec(subdev, suspend);
 				if (ret && suspend)
 					goto fail;
 			}
 		}
 	}
 	ret = 0;
 fail:
 	for (; ret && i < NVDEV_SUBDEV_NR; i++) {
 		if ((subdev = device->subdev[i])) {
 			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
 				ret = nouveau_object_inc(subdev);
 				if (ret) {
 					/* XXX */
 				}
 			}
 		}
 	}
 	return ret;
 }
 static int
 nouveau_device_init(struct nouveau_object *object)
 {
 	struct nouveau_device *device = (void *)object;
 	struct nouveau_object *subdev;
 	int ret, i;
 	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
 		if ((subdev = device->subdev[i])) {
 			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
 				ret = nouveau_object_inc(subdev);
 				if (ret)
 					goto fail;
 			} else {
 				nouveau_subdev_reset(subdev);
 			}
 		}
 	}
 	ret = 0;
 fail:
 	for (--i; ret && i >= 0; i--) {
 		if ((subdev = device->subdev[i])) {
 			if (!nv_iclass(subdev, NV_ENGINE_CLASS))
 				nouveau_object_dec(subdev, false);
 		}
 	}
 	return ret;
 }
 static void
 nouveau_device_dtor(struct nouveau_object *object)
 {
 	struct nouveau_device *device = (void *)object;
 	mutex_lock(&nv_devices_mutex);
 	list_del(&device->head);
 	mutex_unlock(&nv_devices_mutex);
 	if (nv_subdev(device)->mmio)
 		iounmap(nv_subdev(device)->mmio);
 	nouveau_engine_destroy(&device->base);
 }
 static struct nouveau_oclass
 nouveau_device_oclass = {
 	.handle = NV_ENGINE(DEVICE, 0x00),
 	.ofuncs = &(struct nouveau_ofuncs) {
 		.dtor = nouveau_device_dtor,
 		.init = nouveau_device_init,
 		.fini = nouveau_device_fini,
 	},
 };
 int
 nouveau_device_create_(struct pci_dev *pdev, u64 name, const char *sname,
 		       const char *cfg, const char *dbg,
 		       int length, void **pobject)
 {
 	struct nouveau_device *device;
 	int ret = -EEXIST;
 	mutex_lock(&nv_devices_mutex);
 	list_for_each_entry(device, &nv_devices, head) {
 		if (device->handle == name)
 			goto done;
 	}
 	ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
 				     "DEVICE", "device", length, pobject);
 	device = *pobject;
 	if (ret)
 		goto done;
 	device->pdev = pdev;
 	device->handle = name;
 	device->cfgopt = cfg;
 	device->dbgopt = dbg;
 	device->name = sname;
 	nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
 	nv_engine(device)->sclass = nouveau_device_sclass;
 	list_add(&device->head, &nv_devices);
 done:
 	mutex_unlock(&nv_devices_mutex);
 	return ret;
 }

drivers/gpu/drm/nouveau/core/engine/device/nve0.c

Diff comments View file @ f468400

 /*
  * Copyright 2012 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Ben Skeggs
  */
 #include <subdev/bios.h>
 #include <subdev/bus.h>
 #include <subdev/gpio.h>
 #include <subdev/i2c.h>
 #include <subdev/clock.h>
 #include <subdev/therm.h>
 #include <subdev/mxm.h>
 #include <subdev/devinit.h>
 #include <subdev/mc.h>
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 #include <subdev/ltcg.h>
 #include <subdev/ibus.h>
 #include <subdev/instmem.h>
 #include <subdev/vm.h>
 #include <subdev/bar.h>
 #include <engine/device.h>
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
 #include <engine/graph.h>
 #include <engine/disp.h>
 #include <engine/copy.h>
 #include <engine/bsp.h>
 #include <engine/vp.h>
 #include <engine/ppp.h>
 int
 nve0_identify(struct nouveau_device *device)
 {
 	switch (device->chipset) {
 	case 0xe4:
 		device->cname = "GK104";
 		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
 		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
 		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
 		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
 		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 		break;
 	case 0xe7:
 		device->cname = "GK107";
 		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
 		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
 		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
 		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
 		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 		break;
 	case 0xe6:
 		device->cname = "GK106";
 		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
 		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
 		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
 		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
 		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
 		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 		break;
+	case 0xf0:
+		device->cname = "GK110";
+		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
+		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
+		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
+		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
+		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
+		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
+		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
+		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
+		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
+		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
+		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
+		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
+		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
+		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
+		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
+		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
+#if 0
+		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
+#endif
+		device->oclass[NVDEV_ENGINE_DISP   ] = &nvf0_disp_oclass;
+#if 0
+		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
+		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
+		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
+		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
+		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
+		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+#endif
+		break;
 	default:
 		nv_fatal(device, "unknown Kepler chipset\n");
 		return -EINVAL;
 	}
 	return 0;
 }

drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c

Diff comments View file @ f468400

File was created	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <engine/software.h>
	26	#include <engine/disp.h>
	27
	28	#include <core/class.h>
	29
	30	#include "nv50.h"
	31
	32	static struct nouveau_oclass
	33	nvf0_disp_sclass[] = {
	34	{ NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
	35	{ NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
	36	{ NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
	37	{ NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
	38	{ NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
	39	{}
	40	};
	41
	42	static struct nouveau_oclass
	43	nvf0_disp_base_oclass[] = {
	44	{ NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
	45	{}
	46	};
	47
	48	static int
	49	nvf0_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
	50	struct nouveau_oclass oclass, void data, u32 size,
	51	struct nouveau_object **pobject)
	52	{
	53	struct nv50_disp_priv *priv;
	54	int heads = nv_rd32(parent, 0x022448);
	55	int ret;
	56
	57	ret = nouveau_disp_create(parent, engine, oclass, heads,
	58	"PDISP", "display", &priv);
	59	*pobject = nv_object(priv);
	60	if (ret)
	61	return ret;
	62
	63	nv_engine(priv)->sclass = nvf0_disp_base_oclass;
	64	nv_engine(priv)->cclass = &nv50_disp_cclass;
	65	nv_subdev(priv)->intr = nvd0_disp_intr;
	66	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
	67	priv->sclass = nvf0_disp_sclass;
	68	priv->head.nr = heads;
	69	priv->dac.nr = 3;
	70	priv->sor.nr = 4;
	71	priv->dac.power = nv50_dac_power;
	72	priv->dac.sense = nv50_dac_sense;
	73	priv->sor.power = nv50_sor_power;
	74	priv->sor.hda_eld = nvd0_hda_eld;
	75	priv->sor.hdmi = nvd0_hdmi_ctrl;
	76	priv->sor.dp = &nvd0_sor_dp_func;
	77	return 0;
	78	}
	79
	80	struct nouveau_oclass
	81	nvf0_disp_oclass = {
	82	.handle = NV_ENGINE(DISP, 0x92),
	83	.ofuncs = &(struct nouveau_ofuncs) {
	84	.ctor = nvf0_disp_ctor,
	85	.dtor = _nouveau_disp_dtor,
	86	.init = _nouveau_disp_init,
	87	.fini = _nouveau_disp_fini,
	88	},
	89	};
	90

drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c

Diff comments View file @ f468400

 /*
  * Copyright 2012 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Ben Skeggs
  */
 #include <core/device.h>
 #include <core/gpuobj.h>
 #include <core/class.h>
 #include <subdev/fb.h>
 #include <engine/dmaobj.h>
 struct nvd0_dmaeng_priv {
 	struct nouveau_dmaeng base;
 };
 static int
 nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
 		 struct nouveau_object *parent,
 		 struct nouveau_dmaobj *dmaobj,
 		 struct nouveau_gpuobj **pgpuobj)
 {
 	u32 flags0 = 0x00000000;
 	int ret;
 	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
 		switch (nv_mclass(parent->parent)) {
 		case NVD0_DISP_MAST_CLASS:
 		case NVD0_DISP_SYNC_CLASS:
 		case NVD0_DISP_OVLY_CLASS:
 		case NVE0_DISP_MAST_CLASS:
 		case NVE0_DISP_SYNC_CLASS:
 		case NVE0_DISP_OVLY_CLASS:
+		case NVF0_DISP_MAST_CLASS:
+		case NVF0_DISP_SYNC_CLASS:
+		case NVF0_DISP_OVLY_CLASS:
 			break;
 		default:
 			return -EINVAL;
 		}
 	} else
 		return 0;
 	if (!(dmaobj->conf0 & NVD0_DMA_CONF0_ENABLE)) {
 		if (dmaobj->target == NV_MEM_TARGET_VM) {
 			dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_VM;
 			dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_LP;
 		} else {
 			dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_LINEAR;
 			dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_SP;
 		}
 	}
 	flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_TYPE) << 20;
 	flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_PAGE) >> 4;
 	switch (dmaobj->target) {
 	case NV_MEM_TARGET_VRAM:
 		flags0 |= 0x00000009;
 		break;
 	default:
 		return -EINVAL;
 		break;
 	}
 	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
 	if (ret == 0) {
 		nv_wo32(*pgpuobj, 0x00, flags0);
 		nv_wo32(*pgpuobj, 0x04, dmaobj->start >> 8);
 		nv_wo32(*pgpuobj, 0x08, dmaobj->limit >> 8);
 		nv_wo32(*pgpuobj, 0x0c, 0x00000000);
 		nv_wo32(*pgpuobj, 0x10, 0x00000000);
 		nv_wo32(*pgpuobj, 0x14, 0x00000000);
 	}
 	return ret;
 }
 static int
 nvd0_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 		 struct nouveau_oclass *oclass, void *data, u32 size,
 		 struct nouveau_object **pobject)
 {
 	struct nvd0_dmaeng_priv *priv;
 	int ret;
 	ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 	nv_engine(priv)->sclass = nouveau_dmaobj_sclass;
 	priv->base.bind = nvd0_dmaobj_bind;
 	return 0;
 }
 struct nouveau_oclass
 nvd0_dmaeng_oclass = {
 	.handle = NV_ENGINE(DMAOBJ, 0xd0),
 	.ofuncs = &(struct nouveau_ofuncs) {
 		.ctor = nvd0_dmaeng_ctor,
 		.dtor = _nouveau_dmaeng_dtor,
 		.init = _nouveau_dmaeng_init,
 		.fini = _nouveau_dmaeng_fini,
 	},
 };

drivers/gpu/drm/nouveau/core/include/core/class.h

Diff comments View file @ f468400

 #ifndef __NOUVEAU_CLASS_H__
 #define __NOUVEAU_CLASS_H__
 /* Device class
  *
  * 0080: NV_DEVICE
  */
 #define NV_DEVICE_CLASS                                              0x00000080
 #define NV_DEVICE_DISABLE_IDENTIFY                        0x0000000000000001ULL
 #define NV_DEVICE_DISABLE_MMIO                            0x0000000000000002ULL
 #define NV_DEVICE_DISABLE_VBIOS                           0x0000000000000004ULL
 #define NV_DEVICE_DISABLE_CORE                            0x0000000000000008ULL
 #define NV_DEVICE_DISABLE_DISP                            0x0000000000010000ULL
 #define NV_DEVICE_DISABLE_FIFO                            0x0000000000020000ULL
 #define NV_DEVICE_DISABLE_GRAPH                           0x0000000100000000ULL
 #define NV_DEVICE_DISABLE_MPEG                            0x0000000200000000ULL
 #define NV_DEVICE_DISABLE_ME                              0x0000000400000000ULL
 #define NV_DEVICE_DISABLE_VP                              0x0000000800000000ULL
 #define NV_DEVICE_DISABLE_CRYPT                           0x0000001000000000ULL
 #define NV_DEVICE_DISABLE_BSP                             0x0000002000000000ULL
 #define NV_DEVICE_DISABLE_PPP                             0x0000004000000000ULL
 #define NV_DEVICE_DISABLE_COPY0                           0x0000008000000000ULL
 #define NV_DEVICE_DISABLE_COPY1                           0x0000010000000000ULL
 #define NV_DEVICE_DISABLE_UNK1C1                          0x0000020000000000ULL
 #define NV_DEVICE_DISABLE_VENC                            0x0000040000000000ULL
 struct nv_device_class {
 	u64 device;	/* device identifier, ~0 for client default */
 	u64 disable;	/* disable particular subsystems */
 	u64 debug0;	/* as above, but *internal* ids, and *NOT* ABI */
 };
 /* DMA object classes
  *
  * 0002: NV_DMA_FROM_MEMORY
  * 0003: NV_DMA_TO_MEMORY
  * 003d: NV_DMA_IN_MEMORY
  */
 #define NV_DMA_FROM_MEMORY_CLASS                                     0x00000002
 #define NV_DMA_TO_MEMORY_CLASS                                       0x00000003
 #define NV_DMA_IN_MEMORY_CLASS                                       0x0000003d
 #define NV_DMA_TARGET_MASK                                           0x000000ff
 #define NV_DMA_TARGET_VM                                             0x00000000
 #define NV_DMA_TARGET_VRAM                                           0x00000001
 #define NV_DMA_TARGET_PCI                                            0x00000002
 #define NV_DMA_TARGET_PCI_US                                         0x00000003
 #define NV_DMA_TARGET_AGP                                            0x00000004
 #define NV_DMA_ACCESS_MASK                                           0x00000f00
 #define NV_DMA_ACCESS_VM                                             0x00000000
 #define NV_DMA_ACCESS_RD                                             0x00000100
 #define NV_DMA_ACCESS_WR                                             0x00000200
 #define NV_DMA_ACCESS_RDWR                                           0x00000300
 /* NV50:NVC0 */
 #define NV50_DMA_CONF0_ENABLE                                        0x80000000
 #define NV50_DMA_CONF0_PRIV                                          0x00300000
 #define NV50_DMA_CONF0_PRIV_VM                                       0x00000000
 #define NV50_DMA_CONF0_PRIV_US                                       0x00100000
 #define NV50_DMA_CONF0_PRIV__S                                       0x00200000
 #define NV50_DMA_CONF0_PART                                          0x00030000
 #define NV50_DMA_CONF0_PART_VM                                       0x00000000
 #define NV50_DMA_CONF0_PART_256                                      0x00010000
 #define NV50_DMA_CONF0_PART_1KB                                      0x00020000
 #define NV50_DMA_CONF0_COMP                                          0x00000180
 #define NV50_DMA_CONF0_COMP_NONE                                     0x00000000
 #define NV50_DMA_CONF0_COMP_VM                                       0x00000180
 #define NV50_DMA_CONF0_TYPE                                          0x0000007f
 #define NV50_DMA_CONF0_TYPE_LINEAR                                   0x00000000
 #define NV50_DMA_CONF0_TYPE_VM                                       0x0000007f
 /* NVC0:NVD9 */
 #define NVC0_DMA_CONF0_ENABLE                                        0x80000000
 #define NVC0_DMA_CONF0_PRIV                                          0x00300000
 #define NVC0_DMA_CONF0_PRIV_VM                                       0x00000000
 #define NVC0_DMA_CONF0_PRIV_US                                       0x00100000
 #define NVC0_DMA_CONF0_PRIV__S                                       0x00200000
 #define NVC0_DMA_CONF0_UNKN /* PART? */                              0x00030000
 #define NVC0_DMA_CONF0_TYPE                                          0x000000ff
 #define NVC0_DMA_CONF0_TYPE_LINEAR                                   0x00000000
 #define NVC0_DMA_CONF0_TYPE_VM                                       0x000000ff
 /* NVD9- */
 #define NVD0_DMA_CONF0_ENABLE                                        0x80000000
 #define NVD0_DMA_CONF0_PAGE                                          0x00000400
 #define NVD0_DMA_CONF0_PAGE_LP                                       0x00000000
 #define NVD0_DMA_CONF0_PAGE_SP                                       0x00000400
 #define NVD0_DMA_CONF0_TYPE                                          0x000000ff
 #define NVD0_DMA_CONF0_TYPE_LINEAR                                   0x00000000
 #define NVD0_DMA_CONF0_TYPE_VM                                       0x000000ff
 struct nv_dma_class {
 	u32 flags;
 	u32 pad0;
 	u64 start;
 	u64 limit;
 	u32 conf0;
 };
 /* DMA FIFO channel classes
  *
  * 006b: NV03_CHANNEL_DMA
  * 006e: NV10_CHANNEL_DMA
  * 176e: NV17_CHANNEL_DMA
  * 406e: NV40_CHANNEL_DMA
  * 506e: NV50_CHANNEL_DMA
  * 826e: NV84_CHANNEL_DMA
  */
 #define NV03_CHANNEL_DMA_CLASS                                       0x0000006b
 #define NV10_CHANNEL_DMA_CLASS                                       0x0000006e
 #define NV17_CHANNEL_DMA_CLASS                                       0x0000176e
 #define NV40_CHANNEL_DMA_CLASS                                       0x0000406e
 #define NV50_CHANNEL_DMA_CLASS                                       0x0000506e
 #define NV84_CHANNEL_DMA_CLASS                                       0x0000826e
 struct nv03_channel_dma_class {
 	u32 pushbuf;
 	u32 pad0;
 	u64 offset;
 };
 /* Indirect FIFO channel classes
  *
  * 506f: NV50_CHANNEL_IND
  * 826f: NV84_CHANNEL_IND
  * 906f: NVC0_CHANNEL_IND
  * a06f: NVE0_CHANNEL_IND
  */
 #define NV50_CHANNEL_IND_CLASS                                       0x0000506f
 #define NV84_CHANNEL_IND_CLASS                                       0x0000826f
 #define NVC0_CHANNEL_IND_CLASS                                       0x0000906f
 #define NVE0_CHANNEL_IND_CLASS                                       0x0000a06f
 struct nv50_channel_ind_class {
 	u32 pushbuf;
 	u32 ilength;
 	u64 ioffset;
 };
 #define NVE0_CHANNEL_IND_ENGINE_GR                                   0x00000001
 #define NVE0_CHANNEL_IND_ENGINE_VP                                   0x00000002
 #define NVE0_CHANNEL_IND_ENGINE_PPP                                  0x00000004
 #define NVE0_CHANNEL_IND_ENGINE_BSP                                  0x00000008
 #define NVE0_CHANNEL_IND_ENGINE_CE0                                  0x00000010
 #define NVE0_CHANNEL_IND_ENGINE_CE1                                  0x00000020
 #define NVE0_CHANNEL_IND_ENGINE_ENC                                  0x00000040
 struct nve0_channel_ind_class {
 	u32 pushbuf;
 	u32 ilength;
 	u64 ioffset;
 	u32 engine;
 };
 /* 0046: NV04_DISP
  */
 #define NV04_DISP_CLASS                                              0x00000046
 struct nv04_display_class {
 };
 /* 5070: NV50_DISP
  * 8270: NV84_DISP
  * 8370: NVA0_DISP
  * 8870: NV94_DISP
  * 8570: NVA3_DISP
  * 9070: NVD0_DISP
  * 9170: NVE0_DISP
+ * 9270: NVF0_DISP
  */
 #define NV50_DISP_CLASS                                              0x00005070
 #define NV84_DISP_CLASS                                              0x00008270
 #define NVA0_DISP_CLASS                                              0x00008370
 #define NV94_DISP_CLASS                                              0x00008870
 #define NVA3_DISP_CLASS                                              0x00008570
 #define NVD0_DISP_CLASS                                              0x00009070
 #define NVE0_DISP_CLASS                                              0x00009170
+#define NVF0_DISP_CLASS                                              0x00009270
 #define NV50_DISP_SOR_MTHD                                           0x00010000
 #define NV50_DISP_SOR_MTHD_TYPE                                      0x0000f000
 #define NV50_DISP_SOR_MTHD_HEAD                                      0x00000018
 #define NV50_DISP_SOR_MTHD_LINK                                      0x00000004
 #define NV50_DISP_SOR_MTHD_OR                                        0x00000003
 #define NV50_DISP_SOR_PWR                                            0x00010000
 #define NV50_DISP_SOR_PWR_STATE                                      0x00000001
 #define NV50_DISP_SOR_PWR_STATE_ON                                   0x00000001
 #define NV50_DISP_SOR_PWR_STATE_OFF                                  0x00000000
 #define NVA3_DISP_SOR_HDA_ELD                                        0x00010100
 #define NV84_DISP_SOR_HDMI_PWR                                       0x00012000
 #define NV84_DISP_SOR_HDMI_PWR_STATE                                 0x40000000
 #define NV84_DISP_SOR_HDMI_PWR_STATE_OFF                             0x00000000
 #define NV84_DISP_SOR_HDMI_PWR_STATE_ON                              0x40000000
 #define NV84_DISP_SOR_HDMI_PWR_MAX_AC_PACKET                         0x001f0000
 #define NV84_DISP_SOR_HDMI_PWR_REKEY                                 0x0000007f
 #define NV50_DISP_SOR_LVDS_SCRIPT                                    0x00013000
 #define NV50_DISP_SOR_LVDS_SCRIPT_ID                                 0x0000ffff
 #define NV50_DISP_DAC_MTHD                                           0x00020000
 #define NV50_DISP_DAC_MTHD_TYPE                                      0x0000f000
 #define NV50_DISP_DAC_MTHD_OR                                        0x00000003
 #define NV50_DISP_DAC_PWR                                            0x00020000
 #define NV50_DISP_DAC_PWR_HSYNC                                      0x00000001
 #define NV50_DISP_DAC_PWR_HSYNC_ON                                   0x00000000
 #define NV50_DISP_DAC_PWR_HSYNC_LO                                   0x00000001
 #define NV50_DISP_DAC_PWR_VSYNC                                      0x00000004
 #define NV50_DISP_DAC_PWR_VSYNC_ON                                   0x00000000
 #define NV50_DISP_DAC_PWR_VSYNC_LO                                   0x00000004
 #define NV50_DISP_DAC_PWR_DATA                                       0x00000010
 #define NV50_DISP_DAC_PWR_DATA_ON                                    0x00000000
 #define NV50_DISP_DAC_PWR_DATA_LO                                    0x00000010
 #define NV50_DISP_DAC_PWR_STATE                                      0x00000040
 #define NV50_DISP_DAC_PWR_STATE_ON                                   0x00000000
 #define NV50_DISP_DAC_PWR_STATE_OFF                                  0x00000040
 #define NV50_DISP_DAC_LOAD                                           0x0002000c
 #define NV50_DISP_DAC_LOAD_VALUE                                     0x00000007
 #define NV50_DISP_PIOR_MTHD                                          0x00030000
 #define NV50_DISP_PIOR_MTHD_TYPE                                     0x0000f000
 #define NV50_DISP_PIOR_MTHD_OR                                       0x00000003
 #define NV50_DISP_PIOR_PWR                                           0x00030000
 #define NV50_DISP_PIOR_PWR_STATE                                     0x00000001
 #define NV50_DISP_PIOR_PWR_STATE_ON                                  0x00000001
 #define NV50_DISP_PIOR_PWR_STATE_OFF                                 0x00000000
 #define NV50_DISP_PIOR_TMDS_PWR                                      0x00032000
 #define NV50_DISP_PIOR_TMDS_PWR_STATE                                0x00000001
 #define NV50_DISP_PIOR_TMDS_PWR_STATE_ON                             0x00000001
 #define NV50_DISP_PIOR_TMDS_PWR_STATE_OFF                            0x00000000
 #define NV50_DISP_PIOR_DP_PWR                                        0x00036000
 #define NV50_DISP_PIOR_DP_PWR_STATE                                  0x00000001
 #define NV50_DISP_PIOR_DP_PWR_STATE_ON                               0x00000001
 #define NV50_DISP_PIOR_DP_PWR_STATE_OFF                              0x00000000
 struct nv50_display_class {
 };
 /* 507a: NV50_DISP_CURS
  * 827a: NV84_DISP_CURS
  * 837a: NVA0_DISP_CURS
  * 887a: NV94_DISP_CURS
  * 857a: NVA3_DISP_CURS
  * 907a: NVD0_DISP_CURS
  * 917a: NVE0_DISP_CURS
+ * 927a: NVF0_DISP_CURS
  */
 #define NV50_DISP_CURS_CLASS                                         0x0000507a
 #define NV84_DISP_CURS_CLASS                                         0x0000827a
 #define NVA0_DISP_CURS_CLASS                                         0x0000837a
 #define NV94_DISP_CURS_CLASS                                         0x0000887a
 #define NVA3_DISP_CURS_CLASS                                         0x0000857a
 #define NVD0_DISP_CURS_CLASS                                         0x0000907a
 #define NVE0_DISP_CURS_CLASS                                         0x0000917a
+#define NVF0_DISP_CURS_CLASS                                         0x0000927a
 struct nv50_display_curs_class {
 	u32 head;
 };
 /* 507b: NV50_DISP_OIMM
  * 827b: NV84_DISP_OIMM
  * 837b: NVA0_DISP_OIMM
  * 887b: NV94_DISP_OIMM
  * 857b: NVA3_DISP_OIMM
  * 907b: NVD0_DISP_OIMM
  * 917b: NVE0_DISP_OIMM
+ * 927b: NVE0_DISP_OIMM
  */
 #define NV50_DISP_OIMM_CLASS                                         0x0000507b
 #define NV84_DISP_OIMM_CLASS                                         0x0000827b
 #define NVA0_DISP_OIMM_CLASS                                         0x0000837b
 #define NV94_DISP_OIMM_CLASS                                         0x0000887b
 #define NVA3_DISP_OIMM_CLASS                                         0x0000857b
 #define NVD0_DISP_OIMM_CLASS                                         0x0000907b
 #define NVE0_DISP_OIMM_CLASS                                         0x0000917b
+#define NVF0_DISP_OIMM_CLASS                                         0x0000927b
 struct nv50_display_oimm_class {
 	u32 head;
 };
 /* 507c: NV50_DISP_SYNC
  * 827c: NV84_DISP_SYNC
  * 837c: NVA0_DISP_SYNC
  * 887c: NV94_DISP_SYNC
  * 857c: NVA3_DISP_SYNC
  * 907c: NVD0_DISP_SYNC
  * 917c: NVE0_DISP_SYNC
+ * 927c: NVF0_DISP_SYNC
  */
 #define NV50_DISP_SYNC_CLASS                                         0x0000507c
 #define NV84_DISP_SYNC_CLASS                                         0x0000827c
 #define NVA0_DISP_SYNC_CLASS                                         0x0000837c
 #define NV94_DISP_SYNC_CLASS                                         0x0000887c
 #define NVA3_DISP_SYNC_CLASS                                         0x0000857c
 #define NVD0_DISP_SYNC_CLASS                                         0x0000907c
 #define NVE0_DISP_SYNC_CLASS                                         0x0000917c
+#define NVF0_DISP_SYNC_CLASS                                         0x0000927c
 struct nv50_display_sync_class {
 	u32 pushbuf;
 	u32 head;
 };
 /* 507d: NV50_DISP_MAST
  * 827d: NV84_DISP_MAST
  * 837d: NVA0_DISP_MAST
  * 887d: NV94_DISP_MAST
  * 857d: NVA3_DISP_MAST
  * 907d: NVD0_DISP_MAST
  * 917d: NVE0_DISP_MAST
+ * 927d: NVF0_DISP_MAST
  */
 #define NV50_DISP_MAST_CLASS                                         0x0000507d
 #define NV84_DISP_MAST_CLASS                                         0x0000827d
 #define NVA0_DISP_MAST_CLASS                                         0x0000837d
 #define NV94_DISP_MAST_CLASS                                         0x0000887d
 #define NVA3_DISP_MAST_CLASS                                         0x0000857d
 #define NVD0_DISP_MAST_CLASS                                         0x0000907d
 #define NVE0_DISP_MAST_CLASS                                         0x0000917d
+#define NVF0_DISP_MAST_CLASS                                         0x0000927d
 struct nv50_display_mast_class {
 	u32 pushbuf;
 };
 /* 507e: NV50_DISP_OVLY
  * 827e: NV84_DISP_OVLY
  * 837e: NVA0_DISP_OVLY
  * 887e: NV94_DISP_OVLY
  * 857e: NVA3_DISP_OVLY
  * 907e: NVD0_DISP_OVLY
  * 917e: NVE0_DISP_OVLY
+ * 927e: NVF0_DISP_OVLY
  */
 #define NV50_DISP_OVLY_CLASS                                         0x0000507e
 #define NV84_DISP_OVLY_CLASS                                         0x0000827e
 #define NVA0_DISP_OVLY_CLASS                                         0x0000837e
 #define NV94_DISP_OVLY_CLASS                                         0x0000887e
 #define NVA3_DISP_OVLY_CLASS                                         0x0000857e
 #define NVD0_DISP_OVLY_CLASS                                         0x0000907e
 #define NVE0_DISP_OVLY_CLASS                                         0x0000917e
+#define NVF0_DISP_OVLY_CLASS                                         0x0000927e
 struct nv50_display_ovly_class {
 	u32 pushbuf;
 	u32 head;
 };
 #endif

drivers/gpu/drm/nouveau/core/include/engine/disp.h

Diff comments View file @ f468400

 #ifndef __NOUVEAU_DISP_H__
 #define __NOUVEAU_DISP_H__
 #include <core/object.h>
 #include <core/engine.h>
 #include <core/device.h>
 #include <core/event.h>
 struct nouveau_disp {
 	struct nouveau_engine base;
 	struct nouveau_event *vblank;
 };
 static inline struct nouveau_disp *
 nouveau_disp(void *obj)
 {
 	return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_DISP];
 }
 #define nouveau_disp_create(p,e,c,h,i,x,d)                                     \
 	nouveau_disp_create_((p), (e), (c), (h), (i), (x),                     \
 			     sizeof(**d), (void **)d)
 #define nouveau_disp_destroy(d) ({                                             \
 	struct nouveau_disp *disp = (d);                                       \
 	_nouveau_disp_dtor(nv_object(disp));                                   \
 })
 #define nouveau_disp_init(d)                                                   \
 	nouveau_engine_init(&(d)->base)
 #define nouveau_disp_fini(d,s)                                                 \
 	nouveau_engine_fini(&(d)->base, (s))
 int  nouveau_disp_create_(struct nouveau_object *, struct nouveau_object *,
 			  struct nouveau_oclass *, int heads,
 			  const char *, const char *, int, void **);
 void _nouveau_disp_dtor(struct nouveau_object *);
 #define _nouveau_disp_init _nouveau_engine_init
 #define _nouveau_disp_fini _nouveau_engine_fini
 extern struct nouveau_oclass nv04_disp_oclass;
 extern struct nouveau_oclass nv50_disp_oclass;
 extern struct nouveau_oclass nv84_disp_oclass;
 extern struct nouveau_oclass nva0_disp_oclass;
 extern struct nouveau_oclass nv94_disp_oclass;
 extern struct nouveau_oclass nva3_disp_oclass;
 extern struct nouveau_oclass nvd0_disp_oclass;
 extern struct nouveau_oclass nve0_disp_oclass;
+extern struct nouveau_oclass nvf0_disp_oclass;
 #endif

drivers/gpu/drm/nouveau/nouveau_drm.c

Diff comments View file @ f468400

 /*
  * Copyright 2012 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Ben Skeggs
  */
 #include <linux/console.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <core/device.h>
 #include <core/client.h>
 #include <core/gpuobj.h>
 #include <core/class.h>
 #include <engine/device.h>
 #include <engine/disp.h>
+#include <engine/fifo.h>
 #include <subdev/vm.h>
 #include "nouveau_drm.h"
 #include "nouveau_dma.h"
 #include "nouveau_ttm.h"
 #include "nouveau_gem.h"
 #include "nouveau_agp.h"
 #include "nouveau_vga.h"
 #include "nouveau_pm.h"
 #include "nouveau_acpi.h"
 #include "nouveau_bios.h"
 #include "nouveau_ioctl.h"
 #include "nouveau_abi16.h"
 #include "nouveau_fbcon.h"
 #include "nouveau_fence.h"
 #include "nouveau_debugfs.h"
 MODULE_PARM_DESC(config, "option string to pass to driver core");
 static char *nouveau_config;
 module_param_named(config, nouveau_config, charp, 0400);
 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
 static char *nouveau_debug;
 module_param_named(debug, nouveau_debug, charp, 0400);
 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
 static int nouveau_noaccel = 0;
 module_param_named(noaccel, nouveau_noaccel, int, 0400);
 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
 		          "0 = disabled, 1 = enabled, 2 = headless)");
 int nouveau_modeset = -1;
 module_param_named(modeset, nouveau_modeset, int, 0400);
 static struct drm_driver driver;
 static int
 nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head)
 {
 	struct nouveau_drm *drm =
 		container_of(event, struct nouveau_drm, vblank[head]);
 	drm_handle_vblank(drm->dev, head);
 	return NVKM_EVENT_KEEP;
 }
 static int
 nouveau_drm_vblank_enable(struct drm_device *dev, int head)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_disp *pdisp = nouveau_disp(drm->device);
 	if (WARN_ON_ONCE(head > ARRAY_SIZE(drm->vblank)))
 		return -EIO;
 	WARN_ON_ONCE(drm->vblank[head].func);
 	drm->vblank[head].func = nouveau_drm_vblank_handler;
 	nouveau_event_get(pdisp->vblank, head, &drm->vblank[head]);
 	return 0;
 }
 static void
 nouveau_drm_vblank_disable(struct drm_device *dev, int head)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_disp *pdisp = nouveau_disp(drm->device);
 	if (drm->vblank[head].func)
 		nouveau_event_put(pdisp->vblank, head, &drm->vblank[head]);
 	else
 		WARN_ON_ONCE(1);
 	drm->vblank[head].func = NULL;
 }
 static u64
 nouveau_name(struct pci_dev *pdev)
 {
 	u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
 	name |= pdev->bus->number << 16;
 	name |= PCI_SLOT(pdev->devfn) << 8;
 	return name | PCI_FUNC(pdev->devfn);
 }
 static int
 nouveau_cli_create(struct pci_dev *pdev, const char *name,
 		   int size, void **pcli)
 {
 	struct nouveau_cli *cli;
 	int ret;
 	*pcli = NULL;
 	ret = nouveau_client_create_(name, nouveau_name(pdev), nouveau_config,
 				     nouveau_debug, size, pcli);
 	cli = *pcli;
 	if (ret) {
 		if (cli)
 			nouveau_client_destroy(&cli->base);
 		*pcli = NULL;
 		return ret;
 	}
 	mutex_init(&cli->mutex);
 	return 0;
 }
 static void
 nouveau_cli_destroy(struct nouveau_cli *cli)
 {
 	struct nouveau_object *client = nv_object(cli);
 	nouveau_vm_ref(NULL, &cli->base.vm, NULL);
 	nouveau_client_fini(&cli->base, false);
 	atomic_set(&client->refcount, 1);
 	nouveau_object_ref(NULL, &client);
 }
 static void
 nouveau_accel_fini(struct nouveau_drm *drm)
 {
 	nouveau_gpuobj_ref(NULL, &drm->notify);
 	nouveau_channel_del(&drm->channel);
 	nouveau_channel_del(&drm->cechan);
 	if (drm->fence)
 		nouveau_fence(drm)->dtor(drm);
 }
 static void
 nouveau_accel_init(struct nouveau_drm *drm)
 {
 	struct nouveau_device *device = nv_device(drm->device);
 	struct nouveau_object *object;
 	u32 arg0, arg1;
 	int ret;
-	if (nouveau_noaccel)
+	if (nouveau_noaccel || !nouveau_fifo(device) /*XXX*/)
 		return;
 	/* initialise synchronisation routines */
 	if      (device->card_type < NV_10) ret = nv04_fence_create(drm);
 	else if (device->chipset   <  0x17) ret = nv10_fence_create(drm);
 	else if (device->card_type < NV_50) ret = nv17_fence_create(drm);
 	else if (device->chipset   <  0x84) ret = nv50_fence_create(drm);
 	else if (device->card_type < NV_C0) ret = nv84_fence_create(drm);
 	else                                ret = nvc0_fence_create(drm);
 	if (ret) {
 		NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
 		nouveau_accel_fini(drm);
 		return;
 	}
 	if (device->card_type >= NV_E0) {
 		ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE,
 					  NVDRM_CHAN + 1,
 					  NVE0_CHANNEL_IND_ENGINE_CE0 |
 					  NVE0_CHANNEL_IND_ENGINE_CE1, 0,
 					  &drm->cechan);
 		if (ret)
 			NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
 		arg0 = NVE0_CHANNEL_IND_ENGINE_GR;
 		arg1 = 1;
 	} else {
 		arg0 = NvDmaFB;
 		arg1 = NvDmaTT;
 	}
 	ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN,
 				  arg0, arg1, &drm->channel);
 	if (ret) {
 		NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
 		nouveau_accel_fini(drm);
 		return;
 	}
 	if (device->card_type < NV_C0) {
 		ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0,
 					&drm->notify);
 		if (ret) {
 			NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
 			nouveau_accel_fini(drm);
 			return;
 		}
 		ret = nouveau_object_new(nv_object(drm),
 					 drm->channel->handle, NvNotify0,
 					 0x003d, &(struct nv_dma_class) {
 						.flags = NV_DMA_TARGET_VRAM |
 							 NV_DMA_ACCESS_RDWR,
 						.start = drm->notify->addr,
 						.limit = drm->notify->addr + 31
 						}, sizeof(struct nv_dma_class),
 					 &object);
 		if (ret) {
 			nouveau_accel_fini(drm);
 			return;
 		}
 	}
 	nouveau_bo_move_init(drm);
 }
 static int nouveau_drm_probe(struct pci_dev *pdev,
 			     const struct pci_device_id *pent)
 {
 	struct nouveau_device *device;
 	struct apertures_struct *aper;
 	bool boot = false;
 	int ret;
 	/* remove conflicting drivers (vesafb, efifb etc) */
 	aper = alloc_apertures(3);
 	if (!aper)
 		return -ENOMEM;
 	aper->ranges[0].base = pci_resource_start(pdev, 1);
 	aper->ranges[0].size = pci_resource_len(pdev, 1);
 	aper->count = 1;
 	if (pci_resource_len(pdev, 2)) {
 		aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 		aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 		aper->count++;
 	}
 	if (pci_resource_len(pdev, 3)) {
 		aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 		aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 		aper->count++;
 	}
 #ifdef CONFIG_X86
 	boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 #endif
 	remove_conflicting_framebuffers(aper, "nouveaufb", boot);
 	kfree(aper);
 	ret = nouveau_device_create(pdev, nouveau_name(pdev), pci_name(pdev),
 				    nouveau_config, nouveau_debug, &device);
 	if (ret)
 		return ret;
 	pci_set_master(pdev);
 	ret = drm_get_pci_dev(pdev, pent, &driver);
 	if (ret) {
 		nouveau_object_ref(NULL, (struct nouveau_object **)&device);
 		return ret;
 	}
 	return 0;
 }
 static struct lock_class_key drm_client_lock_class_key;
 static int
 nouveau_drm_load(struct drm_device *dev, unsigned long flags)
 {
 	struct pci_dev *pdev = dev->pdev;
 	struct nouveau_device *device;
 	struct nouveau_drm *drm;
 	int ret;
 	ret = nouveau_cli_create(pdev, "DRM", sizeof(*drm), (void**)&drm);
 	if (ret)
 		return ret;
 	lockdep_set_class(&drm->client.mutex, &drm_client_lock_class_key);
 	dev->dev_private = drm;
 	drm->dev = dev;
 	INIT_LIST_HEAD(&drm->clients);
 	spin_lock_init(&drm->tile.lock);
 	/* make sure AGP controller is in a consistent state before we
 	 * (possibly) execute vbios init tables (see nouveau_agp.h)
 	 */
 	if (drm_pci_device_is_agp(dev) && dev->agp) {
 		/* dummy device object, doesn't init anything, but allows
 		 * agp code access to registers
 		 */
 		ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT,
 					 NVDRM_DEVICE, 0x0080,
 					 &(struct nv_device_class) {
 						.device = ~0,
 						.disable =
 						 ~(NV_DEVICE_DISABLE_MMIO |
 						   NV_DEVICE_DISABLE_IDENTIFY),
 						.debug0 = ~0,
 					 }, sizeof(struct nv_device_class),
 					 &drm->device);
 		if (ret)
 			goto fail_device;
 		nouveau_agp_reset(drm);
 		nouveau_object_del(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE);
 	}
 	ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE,
 				 0x0080, &(struct nv_device_class) {
 					.device = ~0,
 					.disable = 0,
 					.debug0 = 0,
 				 }, sizeof(struct nv_device_class),
 				 &drm->device);
 	if (ret)
 		goto fail_device;
 	/* workaround an odd issue on nvc1 by disabling the device's
 	 * nosnoop capability.  hopefully won't cause issues until a
 	 * better fix is found - assuming there is one...
 	 */
 	device = nv_device(drm->device);
 	if (nv_device(drm->device)->chipset == 0xc1)
 		nv_mask(device, 0x00088080, 0x00000800, 0x00000000);
 	nouveau_vga_init(drm);
 	nouveau_agp_init(drm);
 	if (device->card_type >= NV_50) {
 		ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40),
 				     0x1000, &drm->client.base.vm);
 		if (ret)
 			goto fail_device;
 	}
 	ret = nouveau_ttm_init(drm);
 	if (ret)
 		goto fail_ttm;
 	ret = nouveau_bios_init(dev);
 	if (ret)
 		goto fail_bios;
 	ret = nouveau_display_create(dev);
 	if (ret)
 		goto fail_dispctor;
 	if (dev->mode_config.num_crtc) {
 		ret = nouveau_display_init(dev);
 		if (ret)
 			goto fail_dispinit;
 	}
 	nouveau_pm_init(dev);
 	nouveau_accel_init(drm);
 	nouveau_fbcon_init(dev);
 	return 0;
 fail_dispinit:
 	nouveau_display_destroy(dev);
 fail_dispctor:
 	nouveau_bios_takedown(dev);
 fail_bios:
 	nouveau_ttm_fini(drm);
 fail_ttm:
 	nouveau_agp_fini(drm);
 	nouveau_vga_fini(drm);
 fail_device:
 	nouveau_cli_destroy(&drm->client);
 	return ret;
 }
 static int
 nouveau_drm_unload(struct drm_device *dev)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	nouveau_fbcon_fini(dev);
 	nouveau_accel_fini(drm);
 	nouveau_pm_fini(dev);
 	if (dev->mode_config.num_crtc)
 		nouveau_display_fini(dev);
 	nouveau_display_destroy(dev);
 	nouveau_bios_takedown(dev);
 	nouveau_ttm_fini(drm);
 	nouveau_agp_fini(drm);
 	nouveau_vga_fini(drm);
 	nouveau_cli_destroy(&drm->client);
 	return 0;
 }
 static void
 nouveau_drm_remove(struct pci_dev *pdev)
 {
 	struct drm_device *dev = pci_get_drvdata(pdev);
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_object *device;
 	device = drm->client.base.device;
 	drm_put_dev(dev);
 	nouveau_object_ref(NULL, &device);
 	nouveau_object_debug();
 }
 static int
 nouveau_do_suspend(struct drm_device *dev)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_cli *cli;
 	int ret;
 	if (dev->mode_config.num_crtc) {
 		NV_INFO(drm, "suspending fbcon...\n");
 		nouveau_fbcon_set_suspend(dev, 1);
 		NV_INFO(drm, "suspending display...\n");
 		ret = nouveau_display_suspend(dev);
 		if (ret)
 			return ret;
 	}
 	NV_INFO(drm, "evicting buffers...\n");
 	ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
 	if (drm->fence && nouveau_fence(drm)->suspend) {
 		if (!nouveau_fence(drm)->suspend(drm))
 			return -ENOMEM;
 	}
 	NV_INFO(drm, "suspending client object trees...\n");
 	list_for_each_entry(cli, &drm->clients, head) {
 		ret = nouveau_client_fini(&cli->base, true);
 		if (ret)
 			goto fail_client;
 	}
 	ret = nouveau_client_fini(&drm->client.base, true);
 	if (ret)
 		goto fail_client;
 	nouveau_agp_fini(drm);
 	return 0;
 fail_client:
 	list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
 		nouveau_client_init(&cli->base);
 	}
 	if (dev->mode_config.num_crtc) {
 		NV_INFO(drm, "resuming display...\n");
 		nouveau_display_resume(dev);
 	}
 	return ret;
 }
 int nouveau_pmops_suspend(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	int ret;
 	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	ret = nouveau_do_suspend(drm_dev);
 	if (ret)
 		return ret;
 	pci_save_state(pdev);
 	pci_disable_device(pdev);
 	pci_set_power_state(pdev, PCI_D3hot);
 	return 0;
 }
 static int
 nouveau_do_resume(struct drm_device *dev)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_cli *cli;
 	NV_INFO(drm, "re-enabling device...\n");
 	nouveau_agp_reset(drm);
 	NV_INFO(drm, "resuming client object trees...\n");
 	nouveau_client_init(&drm->client.base);
 	nouveau_agp_init(drm);
 	list_for_each_entry(cli, &drm->clients, head) {
 		nouveau_client_init(&cli->base);
 	}
 	if (drm->fence && nouveau_fence(drm)->resume)
 		nouveau_fence(drm)->resume(drm);
 	nouveau_run_vbios_init(dev);
 	nouveau_pm_resume(dev);
 	if (dev->mode_config.num_crtc) {
 		NV_INFO(drm, "resuming display...\n");
 		nouveau_display_resume(dev);
 	}
 	return 0;
 }
 int nouveau_pmops_resume(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	int ret;
 	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	pci_set_power_state(pdev, PCI_D0);
 	pci_restore_state(pdev);
 	ret = pci_enable_device(pdev);
 	if (ret)
 		return ret;
 	pci_set_master(pdev);
 	return nouveau_do_resume(drm_dev);
 }
 static int nouveau_pmops_freeze(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	return nouveau_do_suspend(drm_dev);
 }
 static int nouveau_pmops_thaw(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	return nouveau_do_resume(drm_dev);
 }
 static int
 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
 {
 	struct pci_dev *pdev = dev->pdev;
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_cli *cli;
 	char name[32], tmpname[TASK_COMM_LEN];
 	int ret;
 	get_task_comm(tmpname, current);
 	snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
 	ret = nouveau_cli_create(pdev, name, sizeof(*cli), (void **)&cli);
 	if (ret)
 		return ret;
 	if (nv_device(drm->device)->card_type >= NV_50) {
 		ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40),
 				     0x1000, &cli->base.vm);
 		if (ret) {
 			nouveau_cli_destroy(cli);
 			return ret;
 		}
 	}
 	fpriv->driver_priv = cli;
 	mutex_lock(&drm->client.mutex);
 	list_add(&cli->head, &drm->clients);
 	mutex_unlock(&drm->client.mutex);
 	return 0;
 }
 static void
 nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
 {
 	struct nouveau_cli *cli = nouveau_cli(fpriv);
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	if (cli->abi16)
 		nouveau_abi16_fini(cli->abi16);
 	mutex_lock(&drm->client.mutex);
 	list_del(&cli->head);
 	mutex_unlock(&drm->client.mutex);
 }
 static void
 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
 {
 	struct nouveau_cli *cli = nouveau_cli(fpriv);
 	nouveau_cli_destroy(cli);
 }
 static struct drm_ioctl_desc
 nouveau_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
 };
 static const struct file_operations
 nouveau_driver_fops = {
 	.owner = THIS_MODULE,
 	.open = drm_open,
 	.release = drm_release,
 	.unlocked_ioctl = drm_ioctl,
 	.mmap = nouveau_ttm_mmap,
 	.poll = drm_poll,
 	.fasync = drm_fasync,
 	.read = drm_read,
 #if defined(CONFIG_COMPAT)
 	.compat_ioctl = nouveau_compat_ioctl,
 #endif
 	.llseek = noop_llseek,
 };
 static struct drm_driver
 driver = {
 	.driver_features =
 		DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
 		DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME,
 	.load = nouveau_drm_load,
 	.unload = nouveau_drm_unload,
 	.open = nouveau_drm_open,
 	.preclose = nouveau_drm_preclose,
 	.postclose = nouveau_drm_postclose,
 	.lastclose = nouveau_vga_lastclose,
 #if defined(CONFIG_DEBUG_FS)
 	.debugfs_init = nouveau_debugfs_init,
 	.debugfs_cleanup = nouveau_debugfs_takedown,
 #endif
 	.get_vblank_counter = drm_vblank_count,
 	.enable_vblank = nouveau_drm_vblank_enable,
 	.disable_vblank = nouveau_drm_vblank_disable,
 	.ioctls = nouveau_ioctls,
 	.fops = &nouveau_driver_fops,
 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 	.gem_prime_export = drm_gem_prime_export,
 	.gem_prime_import = drm_gem_prime_import,
 	.gem_prime_pin = nouveau_gem_prime_pin,
 	.gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
 	.gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
 	.gem_prime_vmap = nouveau_gem_prime_vmap,
 	.gem_prime_vunmap = nouveau_gem_prime_vunmap,
 	.gem_init_object = nouveau_gem_object_new,
 	.gem_free_object = nouveau_gem_object_del,
 	.gem_open_object = nouveau_gem_object_open,
 	.gem_close_object = nouveau_gem_object_close,
 	.dumb_create = nouveau_display_dumb_create,
 	.dumb_map_offset = nouveau_display_dumb_map_offset,
 	.dumb_destroy = nouveau_display_dumb_destroy,
 	.name = DRIVER_NAME,
 	.desc = DRIVER_DESC,
 #ifdef GIT_REVISION
 	.date = GIT_REVISION,
 #else
 	.date = DRIVER_DATE,
 #endif
 	.major = DRIVER_MAJOR,
 	.minor = DRIVER_MINOR,
 	.patchlevel = DRIVER_PATCHLEVEL,
 };
 static struct pci_device_id
 nouveau_drm_pci_table[] = {
 	{
 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
 		.class = PCI_BASE_CLASS_DISPLAY << 16,
 		.class_mask  = 0xff << 16,
 	},
 	{
 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
 		.class = PCI_BASE_CLASS_DISPLAY << 16,
 		.class_mask  = 0xff << 16,
 	},
 	{}
 };
 static const struct dev_pm_ops nouveau_pm_ops = {
 	.suspend = nouveau_pmops_suspend,
 	.resume = nouveau_pmops_resume,
 	.freeze = nouveau_pmops_freeze,
 	.thaw = nouveau_pmops_thaw,
 	.poweroff = nouveau_pmops_freeze,
 	.restore = nouveau_pmops_resume,
 };
 static struct pci_driver
 nouveau_drm_pci_driver = {
 	.name = "nouveau",
 	.id_table = nouveau_drm_pci_table,
 	.probe = nouveau_drm_probe,
 	.remove = nouveau_drm_remove,
 	.driver.pm = &nouveau_pm_ops,
 };
 static int __init
 nouveau_drm_init(void)
 {
 	driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
 	if (nouveau_modeset == -1) {
 #ifdef CONFIG_VGA_CONSOLE
 		if (vgacon_text_force())
 			nouveau_modeset = 0;
 #endif
 	}
 	if (!nouveau_modeset)
 		return 0;
 	nouveau_register_dsm_handler();
 	return drm_pci_init(&driver, &nouveau_drm_pci_driver);
 }
 static void __exit
 nouveau_drm_exit(void)
 {
 	if (!nouveau_modeset)
 		return;
 	drm_pci_exit(&driver, &nouveau_drm_pci_driver);
 	nouveau_unregister_dsm_handler();
 }
 module_init(nouveau_drm_init);
 module_exit(nouveau_drm_exit);
 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
 MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL and additional rights");

drivers/gpu/drm/nouveau/nv50_display.c

Diff comments View file @ f468400

 	/*
  * Copyright 2011 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Ben Skeggs
  */
 #include <linux/dma-mapping.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include "nouveau_drm.h"
 #include "nouveau_dma.h"
 #include "nouveau_gem.h"
 #include "nouveau_connector.h"
 #include "nouveau_encoder.h"
 #include "nouveau_crtc.h"
 #include "nouveau_fence.h"
 #include "nv50_display.h"
 #include <core/client.h>
 #include <core/gpuobj.h>
 #include <core/class.h>
 #include <subdev/timer.h>
 #include <subdev/bar.h>
 #include <subdev/fb.h>
 #include <subdev/i2c.h>
 #define EVO_DMA_NR 9
 #define EVO_MASTER  (0x00)
 #define EVO_FLIP(c) (0x01 + (c))
 #define EVO_OVLY(c) (0x05 + (c))
 #define EVO_OIMM(c) (0x09 + (c))
 #define EVO_CURS(c) (0x0d + (c))
 /* offsets in shared sync bo of various structures */
 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
 #define EVO_CORE_HANDLE      (0xd1500000)
 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) |                               \
 			      (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
 /******************************************************************************
  * EVO channel
  *****************************************************************************/
 struct nv50_chan {
 	struct nouveau_object *user;
 	u32 handle;
 };
 static int
 nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
 		 void *data, u32 size, struct nv50_chan *chan)
 {
 	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 	const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
 	const u32 handle = EVO_CHAN_HANDLE(bclass, head);
 	int ret;
 	ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
 				 oclass, data, size, &chan->user);
 	if (ret)
 		return ret;
 	chan->handle = handle;
 	return 0;
 }
 static void
 nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
 {
 	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 	if (chan->handle)
 		nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
 }
 /******************************************************************************
  * PIO EVO channel
  *****************************************************************************/
 struct nv50_pioc {
 	struct nv50_chan base;
 };
 static void
 nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
 {
 	nv50_chan_destroy(core, &pioc->base);
 }
 static int
 nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
 		 void *data, u32 size, struct nv50_pioc *pioc)
 {
 	return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
 }
 /******************************************************************************
  * DMA EVO channel
  *****************************************************************************/
 struct nv50_dmac {
 	struct nv50_chan base;
 	dma_addr_t handle;
 	u32 *ptr;
 	/* Protects against concurrent pushbuf access to this channel, lock is
 	 * grabbed by evo_wait (if the pushbuf reservation is successful) and
 	 * dropped again by evo_kick. */
 	struct mutex lock;
 };
 static void
 nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
 {
 	if (dmac->ptr) {
 		struct pci_dev *pdev = nv_device(core)->pdev;
 		pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
 	}
 	nv50_chan_destroy(core, &dmac->base);
 }
 static int
 nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 {
 	struct nouveau_fb *pfb = nouveau_fb(core);
 	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 	struct nouveau_object *object;
 	int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 				     NV_DMA_IN_MEMORY_CLASS,
 				     &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NV50_DMA_CONF0_ENABLE |
 					         NV50_DMA_CONF0_PART_256,
 				     }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	ret = nouveau_object_new(client, parent, NvEvoFB16,
 				 NV_DMA_IN_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
 					         NV50_DMA_CONF0_PART_256,
 				 }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	ret = nouveau_object_new(client, parent, NvEvoFB32,
 				 NV_DMA_IN_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
 					         NV50_DMA_CONF0_PART_256,
 				 }, sizeof(struct nv_dma_class), &object);
 	return ret;
 }
 static int
 nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 {
 	struct nouveau_fb *pfb = nouveau_fb(core);
 	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 	struct nouveau_object *object;
 	int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 				     NV_DMA_IN_MEMORY_CLASS,
 				     &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NVC0_DMA_CONF0_ENABLE,
 				     }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	ret = nouveau_object_new(client, parent, NvEvoFB16,
 				 NV_DMA_IN_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 				 }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	ret = nouveau_object_new(client, parent, NvEvoFB32,
 				 NV_DMA_IN_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 				 }, sizeof(struct nv_dma_class), &object);
 	return ret;
 }
 static int
 nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 {
 	struct nouveau_fb *pfb = nouveau_fb(core);
 	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 	struct nouveau_object *object;
 	int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 				     NV_DMA_IN_MEMORY_CLASS,
 				     &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NVD0_DMA_CONF0_ENABLE |
 						 NVD0_DMA_CONF0_PAGE_LP,
 				     }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	ret = nouveau_object_new(client, parent, NvEvoFB32,
 				 NV_DMA_IN_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 					.conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
 						 NVD0_DMA_CONF0_PAGE_LP,
 				 }, sizeof(struct nv_dma_class), &object);
 	return ret;
 }
 static int
 nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
 		 void *data, u32 size, u64 syncbuf,
 		 struct nv50_dmac *dmac)
 {
 	struct nouveau_fb *pfb = nouveau_fb(core);
 	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 	struct nouveau_object *object;
 	u32 pushbuf = *(u32 *)data;
 	int ret;
 	mutex_init(&dmac->lock);
 	dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
 					&dmac->handle);
 	if (!dmac->ptr)
 		return -ENOMEM;
 	ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
 				 NV_DMA_FROM_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_PCI_US |
 						 NV_DMA_ACCESS_RD,
 					.start = dmac->handle + 0x0000,
 					.limit = dmac->handle + 0x0fff,
 				 }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
 	if (ret)
 		return ret;
 	ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
 				 NV_DMA_IN_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = syncbuf + 0x0000,
 					.limit = syncbuf + 0x0fff,
 				 }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
 				 NV_DMA_IN_MEMORY_CLASS,
 				 &(struct nv_dma_class) {
 					.flags = NV_DMA_TARGET_VRAM |
 						 NV_DMA_ACCESS_RDWR,
 					.start = 0,
 					.limit = pfb->ram.size - 1,
 				 }, sizeof(struct nv_dma_class), &object);
 	if (ret)
 		return ret;
 	if (nv_device(core)->card_type < NV_C0)
 		ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
 	else
 	if (nv_device(core)->card_type < NV_D0)
 		ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
 	else
 		ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
 	return ret;
 }
 struct nv50_mast {
 	struct nv50_dmac base;
 };
 struct nv50_curs {
 	struct nv50_pioc base;
 };
 struct nv50_sync {
 	struct nv50_dmac base;
 	u32 addr;
 	u32 data;
 };
 struct nv50_ovly {
 	struct nv50_dmac base;
 };
 struct nv50_oimm {
 	struct nv50_pioc base;
 };
 struct nv50_head {
 	struct nouveau_crtc base;
 	struct nv50_curs curs;
 	struct nv50_sync sync;
 	struct nv50_ovly ovly;
 	struct nv50_oimm oimm;
 };
 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 #define nv50_curs(c) (&nv50_head(c)->curs)
 #define nv50_sync(c) (&nv50_head(c)->sync)
 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 #define nv50_chan(c) (&(c)->base.base)
 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
 struct nv50_disp {
 	struct nouveau_object *core;
 	struct nv50_mast mast;
 	u32 modeset;
 	struct nouveau_bo *sync;
 };
 static struct nv50_disp *
 nv50_disp(struct drm_device *dev)
 {
 	return nouveau_display(dev)->priv;
 }
 #define nv50_mast(d) (&nv50_disp(d)->mast)
 static struct drm_crtc *
 nv50_display_crtc_get(struct drm_encoder *encoder)
 {
 	return nouveau_encoder(encoder)->crtc;
 }
 /******************************************************************************
  * EVO channel helpers
  *****************************************************************************/
 static u32 *
 evo_wait(void *evoc, int nr)
 {
 	struct nv50_dmac *dmac = evoc;
 	u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
 	mutex_lock(&dmac->lock);
 	if (put + nr >= (PAGE_SIZE / 4) - 8) {
 		dmac->ptr[put] = 0x20000000;
 		nv_wo32(dmac->base.user, 0x0000, 0x00000000);
 		if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
 			mutex_unlock(&dmac->lock);
 			NV_ERROR(dmac->base.user, "channel stalled\n");
 			return NULL;
 		}
 		put = 0;
 	}
 	return dmac->ptr + put;
 }
 static void
 evo_kick(u32 *push, void *evoc)
 {
 	struct nv50_dmac *dmac = evoc;
 	nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 	mutex_unlock(&dmac->lock);
 }
 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 #define evo_data(p,d)   *((p)++) = (d)
 static bool
 evo_sync_wait(void *data)
 {
 	if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 		return true;
 	usleep_range(1, 2);
 	return false;
 }
 static int
 evo_sync(struct drm_device *dev)
 {
 	struct nouveau_device *device = nouveau_dev(dev);
 	struct nv50_disp *disp = nv50_disp(dev);
 	struct nv50_mast *mast = nv50_mast(dev);
 	u32 *push = evo_wait(mast, 8);
 	if (push) {
 		nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 		evo_mthd(push, 0x0084, 1);
 		evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 		evo_mthd(push, 0x0080, 2);
 		evo_data(push, 0x00000000);
 		evo_data(push, 0x00000000);
 		evo_kick(push, mast);
 		if (nv_wait_cb(device, evo_sync_wait, disp->sync))
 			return 0;
 	}
 	return -EBUSY;
 }
 /******************************************************************************
  * Page flipping channel
  *****************************************************************************/
 struct nouveau_bo *
 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 {
 	return nv50_disp(dev)->sync;
 }
 struct nv50_display_flip {
 	struct nv50_disp *disp;
 	struct nv50_sync *chan;
 };
 static bool
 nv50_display_flip_wait(void *data)
 {
 	struct nv50_display_flip *flip = data;
 	if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 					      flip->chan->data);
 		return true;
 	usleep_range(1, 2);
 	return false;
 }
 void
 nv50_display_flip_stop(struct drm_crtc *crtc)
 {
 	struct nouveau_device *device = nouveau_dev(crtc->dev);
 	struct nv50_display_flip flip = {
 		.disp = nv50_disp(crtc->dev),
 		.chan = nv50_sync(crtc),
 	};
 	u32 *push;
 	push = evo_wait(flip.chan, 8);
 	if (push) {
 		evo_mthd(push, 0x0084, 1);
 		evo_data(push, 0x00000000);
 		evo_mthd(push, 0x0094, 1);
 		evo_data(push, 0x00000000);
 		evo_mthd(push, 0x00c0, 1);
 		evo_data(push, 0x00000000);
 		evo_mthd(push, 0x0080, 1);
 		evo_data(push, 0x00000000);
 		evo_kick(push, flip.chan);
 	}
 	nv_wait_cb(device, nv50_display_flip_wait, &flip);
 }
 int
 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 		       struct nouveau_channel *chan, u32 swap_interval)
 {
 	struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	struct nv50_sync *sync = nv50_sync(crtc);
 	int head = nv_crtc->index, ret;
 	u32 *push;
 	swap_interval <<= 4;
 	if (swap_interval == 0)
 		swap_interval |= 0x100;
 	if (chan == NULL)
 		evo_sync(crtc->dev);
 	push = evo_wait(sync, 128);
 	if (unlikely(push == NULL))
 		return -EBUSY;
 	if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
 		ret = RING_SPACE(chan, 8);
 		if (ret)
 			return ret;
 		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 		OUT_RING  (chan, NvEvoSema0 + head);
 		OUT_RING  (chan, sync->addr ^ 0x10);
 		BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 		OUT_RING  (chan, sync->data + 1);
 		BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 		OUT_RING  (chan, sync->addr);
 		OUT_RING  (chan, sync->data);
 	} else
 	if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
 		u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
 		ret = RING_SPACE(chan, 12);
 		if (ret)
 			return ret;
 		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 		OUT_RING  (chan, chan->vram);
 		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 		OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 		OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 		OUT_RING  (chan, sync->data + 1);
 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 		OUT_RING  (chan, upper_32_bits(addr));
 		OUT_RING  (chan, lower_32_bits(addr));
 		OUT_RING  (chan, sync->data);
 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 	} else
 	if (chan) {
 		u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
 		ret = RING_SPACE(chan, 10);
 		if (ret)
 			return ret;
 		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 		OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 		OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 		OUT_RING  (chan, sync->data + 1);
 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 				 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 		OUT_RING  (chan, upper_32_bits(addr));
 		OUT_RING  (chan, lower_32_bits(addr));
 		OUT_RING  (chan, sync->data);
 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 				 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 	}
 	if (chan) {
 		sync->addr ^= 0x10;
 		sync->data++;
 		FIRE_RING (chan);
 	}
 	/* queue the flip */
 	evo_mthd(push, 0x0100, 1);
 	evo_data(push, 0xfffe0000);
 	evo_mthd(push, 0x0084, 1);
 	evo_data(push, swap_interval);
 	if (!(swap_interval & 0x00000100)) {
 		evo_mthd(push, 0x00e0, 1);
 		evo_data(push, 0x40000000);
 	}
 	evo_mthd(push, 0x0088, 4);
 	evo_data(push, sync->addr);
 	evo_data(push, sync->data++);
 	evo_data(push, sync->data);
 	evo_data(push, NvEvoSync);
 	evo_mthd(push, 0x00a0, 2);
 	evo_data(push, 0x00000000);
 	evo_data(push, 0x00000000);
 	evo_mthd(push, 0x00c0, 1);
 	evo_data(push, nv_fb->r_dma);
 	evo_mthd(push, 0x0110, 2);
 	evo_data(push, 0x00000000);
 	evo_data(push, 0x00000000);
 	if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
 		evo_mthd(push, 0x0800, 5);
 		evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 		evo_data(push, 0);
 		evo_data(push, (fb->height << 16) | fb->width);
 		evo_data(push, nv_fb->r_pitch);
 		evo_data(push, nv_fb->r_format);
 	} else {
 		evo_mthd(push, 0x0400, 5);
 		evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 		evo_data(push, 0);
 		evo_data(push, (fb->height << 16) | fb->width);
 		evo_data(push, nv_fb->r_pitch);
 		evo_data(push, nv_fb->r_format);
 	}
 	evo_mthd(push, 0x0080, 1);
 	evo_data(push, 0x00000000);
 	evo_kick(push, sync);
 	return 0;
 }
 /******************************************************************************
  * CRTC
  *****************************************************************************/
 static int
 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 {
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 	struct nouveau_connector *nv_connector;
 	struct drm_connector *connector;
 	u32 *push, mode = 0x00;
 	nv_connector = nouveau_crtc_connector_get(nv_crtc);
 	connector = &nv_connector->base;
 	if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 		if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
 			mode = DITHERING_MODE_DYNAMIC2X2;
 	} else {
 		mode = nv_connector->dithering_mode;
 	}
 	if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 		if (connector->display_info.bpc >= 8)
 			mode |= DITHERING_DEPTH_8BPC;
 	} else {
 		mode |= nv_connector->dithering_depth;
 	}
 	push = evo_wait(mast, 4);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 			evo_data(push, mode);
 		} else
 		if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 			evo_data(push, mode);
 		} else {
 			evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 			evo_data(push, mode);
 		}
 		if (update) {
 			evo_mthd(push, 0x0080, 1);
 			evo_data(push, 0x00000000);
 		}
 		evo_kick(push, mast);
 	}
 	return 0;
 }
 static int
 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 {
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 	struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 	struct drm_crtc *crtc = &nv_crtc->base;
 	struct nouveau_connector *nv_connector;
 	int mode = DRM_MODE_SCALE_NONE;
 	u32 oX, oY, *push;
 	/* start off at the resolution we programmed the crtc for, this
 	 * effectively handles NONE/FULL scaling
 	 */
 	nv_connector = nouveau_crtc_connector_get(nv_crtc);
 	if (nv_connector && nv_connector->native_mode)
 		mode = nv_connector->scaling_mode;
 	if (mode != DRM_MODE_SCALE_NONE)
 		omode = nv_connector->native_mode;
 	else
 		omode = umode;
 	oX = omode->hdisplay;
 	oY = omode->vdisplay;
 	if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 		oY *= 2;
 	/* add overscan compensation if necessary, will keep the aspect
 	 * ratio the same as the backend mode unless overridden by the
 	 * user setting both hborder and vborder properties.
 	 */
 	if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 			     (nv_connector->underscan == UNDERSCAN_AUTO &&
 			      nv_connector->edid &&
 			      drm_detect_hdmi_monitor(nv_connector->edid)))) {
 		u32 bX = nv_connector->underscan_hborder;
 		u32 bY = nv_connector->underscan_vborder;
 		u32 aspect = (oY << 19) / oX;
 		if (bX) {
 			oX -= (bX * 2);
 			if (bY) oY -= (bY * 2);
 			else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 		} else {
 			oX -= (oX >> 4) + 32;
 			if (bY) oY -= (bY * 2);
 			else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 		}
 	}
 	/* handle CENTER/ASPECT scaling, taking into account the areas
 	 * removed already for overscan compensation
 	 */
 	switch (mode) {
 	case DRM_MODE_SCALE_CENTER:
 		oX = min((u32)umode->hdisplay, oX);
 		oY = min((u32)umode->vdisplay, oY);
 		/* fall-through */
 	case DRM_MODE_SCALE_ASPECT:
 		if (oY < oX) {
 			u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 			oX = ((oY * aspect) + (aspect / 2)) >> 19;
 		} else {
 			u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 			oY = ((oX * aspect) + (aspect / 2)) >> 19;
 		}
 		break;
 	default:
 		break;
 	}
 	push = evo_wait(mast, 8);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			/*XXX: SCALE_CTRL_ACTIVE??? */
 			evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 			evo_data(push, (oY << 16) | oX);
 			evo_data(push, (oY << 16) | oX);
 			evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x00000000);
 			evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 		} else {
 			evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 			evo_data(push, (oY << 16) | oX);
 			evo_data(push, (oY << 16) | oX);
 			evo_data(push, (oY << 16) | oX);
 			evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0x00000000);
 			evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 		}
 		evo_kick(push, mast);
 		if (update) {
 			nv50_display_flip_stop(crtc);
 			nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 		}
 	}
 	return 0;
 }
 static int
 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 {
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 	u32 *push, hue, vib;
 	int adj;
 	adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 	vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 	hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 	push = evo_wait(mast, 16);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, (hue << 20) | (vib << 8));
 		} else {
 			evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, (hue << 20) | (vib << 8));
 		}
 		if (update) {
 			evo_mthd(push, 0x0080, 1);
 			evo_data(push, 0x00000000);
 		}
 		evo_kick(push, mast);
 	}
 	return 0;
 }
 static int
 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 		    int x, int y, bool update)
 {
 	struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 	u32 *push;
 	push = evo_wait(mast, 16);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, nvfb->nvbo->bo.offset >> 8);
 			evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 			evo_data(push, (fb->height << 16) | fb->width);
 			evo_data(push, nvfb->r_pitch);
 			evo_data(push, nvfb->r_format);
 			evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, (y << 16) | x);
 			if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
 				evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 				evo_data(push, nvfb->r_dma);
 			}
 		} else {
 			evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, nvfb->nvbo->bo.offset >> 8);
 			evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 			evo_data(push, (fb->height << 16) | fb->width);
 			evo_data(push, nvfb->r_pitch);
 			evo_data(push, nvfb->r_format);
 			evo_data(push, nvfb->r_dma);
 			evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, (y << 16) | x);
 		}
 		if (update) {
 			evo_mthd(push, 0x0080, 1);
 			evo_data(push, 0x00000000);
 		}
 		evo_kick(push, mast);
 	}
 	nv_crtc->fb.tile_flags = nvfb->r_dma;
 	return 0;
 }
 static void
 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 {
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 	u32 *push = evo_wait(mast, 16);
 	if (push) {
 		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 			evo_data(push, 0x85000000);
 			evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 		} else
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 			evo_data(push, 0x85000000);
 			evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 			evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 			evo_data(push, NvEvoVRAM);
 		} else {
 			evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 			evo_data(push, 0x85000000);
 			evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 			evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 			evo_data(push, NvEvoVRAM);
 		}
 		evo_kick(push, mast);
 	}
 }
 static void
 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 {
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 	u32 *push = evo_wait(mast, 16);
 	if (push) {
 		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x05000000);
 		} else
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x05000000);
 			evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x00000000);
 		} else {
 			evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0x05000000);
 			evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0x00000000);
 		}
 		evo_kick(push, mast);
 	}
 }
 static void
 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 {
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 	if (show)
 		nv50_crtc_cursor_show(nv_crtc);
 	else
 		nv50_crtc_cursor_hide(nv_crtc);
 	if (update) {
 		u32 *push = evo_wait(mast, 2);
 		if (push) {
 			evo_mthd(push, 0x0080, 1);
 			evo_data(push, 0x00000000);
 			evo_kick(push, mast);
 		}
 	}
 }
 static void
 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
 {
 }
 static void
 nv50_crtc_prepare(struct drm_crtc *crtc)
 {
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	struct nv50_mast *mast = nv50_mast(crtc->dev);
 	u32 *push;
 	nv50_display_flip_stop(crtc);
 	push = evo_wait(mast, 2);
 	if (push) {
 		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x00000000);
 			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x40000000);
 		} else
 		if (nv50_vers(mast) <  NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x00000000);
 			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x40000000);
 			evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x00000000);
 		} else {
 			evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0x00000000);
 			evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0x03000000);
 			evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0x00000000);
 		}
 		evo_kick(push, mast);
 	}
 	nv50_crtc_cursor_show_hide(nv_crtc, false, false);
 }
 static void
 nv50_crtc_commit(struct drm_crtc *crtc)
 {
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	struct nv50_mast *mast = nv50_mast(crtc->dev);
 	u32 *push;
 	push = evo_wait(mast, 32);
 	if (push) {
 		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, NvEvoVRAM_LP);
 			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
 			evo_data(push, 0xc0000000);
 			evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 		} else
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 			evo_data(push, nv_crtc->fb.tile_flags);
 			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
 			evo_data(push, 0xc0000000);
 			evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 			evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 			evo_data(push, NvEvoVRAM);
 		} else {
 			evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, nv_crtc->fb.tile_flags);
 			evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 			evo_data(push, 0x83000000);
 			evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 			evo_data(push, 0x00000000);
 			evo_data(push, 0x00000000);
 			evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 			evo_data(push, NvEvoVRAM);
 			evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0xffffff00);
 		}
 		evo_kick(push, mast);
 	}
 	nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
 	nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 }
 static bool
 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
 		     struct drm_display_mode *adjusted_mode)
 {
 	return true;
 }
 static int
 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 {
 	struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 	int ret;
 	ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 	if (ret)
 		return ret;
 	if (old_fb) {
 		nvfb = nouveau_framebuffer(old_fb);
 		nouveau_bo_unpin(nvfb->nvbo);
 	}
 	return 0;
 }
 static int
 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 		   struct drm_display_mode *mode, int x, int y,
 		   struct drm_framebuffer *old_fb)
 {
 	struct nv50_mast *mast = nv50_mast(crtc->dev);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	struct nouveau_connector *nv_connector;
 	u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
 	u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
 	u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
 	u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
 	u32 vblan2e = 0, vblan2s = 1;
 	u32 *push;
 	int ret;
 	hactive = mode->htotal;
 	hsynce  = mode->hsync_end - mode->hsync_start - 1;
 	hbackp  = mode->htotal - mode->hsync_end;
 	hblanke = hsynce + hbackp;
 	hfrontp = mode->hsync_start - mode->hdisplay;
 	hblanks = mode->htotal - hfrontp - 1;
 	vactive = mode->vtotal * vscan / ilace;
 	vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
 	vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
 	vblanke = vsynce + vbackp;
 	vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
 	vblanks = vactive - vfrontp - 1;
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		vblan2e = vactive + vsynce + vbackp;
 		vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
 		vactive = (vactive * 2) + 1;
 	}
 	ret = nv50_crtc_swap_fbs(crtc, old_fb);
 	if (ret)
 		return ret;
 	push = evo_wait(mast, 64);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
 			evo_data(push, 0x00800000 | mode->clock);
 			evo_data(push, (ilace == 2) ? 2 : 0);
 			evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
 			evo_data(push, 0x00000000);
 			evo_data(push, (vactive << 16) | hactive);
 			evo_data(push, ( vsynce << 16) | hsynce);
 			evo_data(push, (vblanke << 16) | hblanke);
 			evo_data(push, (vblanks << 16) | hblanks);
 			evo_data(push, (vblan2e << 16) | vblan2s);
 			evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
 			evo_data(push, 0x00000000);
 			evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
 			evo_data(push, 0x00000311);
 			evo_data(push, 0x00000100);
 		} else {
 			evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
 			evo_data(push, 0x00000000);
 			evo_data(push, (vactive << 16) | hactive);
 			evo_data(push, ( vsynce << 16) | hsynce);
 			evo_data(push, (vblanke << 16) | hblanke);
 			evo_data(push, (vblanks << 16) | hblanks);
 			evo_data(push, (vblan2e << 16) | vblan2s);
 			evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 			evo_data(push, 0x00000000); /* ??? */
 			evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 			evo_data(push, mode->clock * 1000);
 			evo_data(push, 0x00200000); /* ??? */
 			evo_data(push, mode->clock * 1000);
 			evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
 			evo_data(push, 0x00000311);
 			evo_data(push, 0x00000100);
 		}
 		evo_kick(push, mast);
 	}
 	nv_connector = nouveau_crtc_connector_get(nv_crtc);
 	nv50_crtc_set_dither(nv_crtc, false);
 	nv50_crtc_set_scale(nv_crtc, false);
 	nv50_crtc_set_color_vibrance(nv_crtc, false);
 	nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 	return 0;
 }
 static int
 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 			struct drm_framebuffer *old_fb)
 {
 	struct nouveau_drm *drm = nouveau_drm(crtc->dev);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	int ret;
 	if (!crtc->fb) {
 		NV_DEBUG(drm, "No FB bound\n");
 		return 0;
 	}
 	ret = nv50_crtc_swap_fbs(crtc, old_fb);
 	if (ret)
 		return ret;
 	nv50_display_flip_stop(crtc);
 	nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 	nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 	return 0;
 }
 static int
 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 			       struct drm_framebuffer *fb, int x, int y,
 			       enum mode_set_atomic state)
 {
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	nv50_display_flip_stop(crtc);
 	nv50_crtc_set_image(nv_crtc, fb, x, y, true);
 	return 0;
 }
 static void
 nv50_crtc_lut_load(struct drm_crtc *crtc)
 {
 	struct nv50_disp *disp = nv50_disp(crtc->dev);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 	int i;
 	for (i = 0; i < 256; i++) {
 		u16 r = nv_crtc->lut.r[i] >> 2;
 		u16 g = nv_crtc->lut.g[i] >> 2;
 		u16 b = nv_crtc->lut.b[i] >> 2;
 		if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
 			writew(r + 0x0000, lut + (i * 0x08) + 0);
 			writew(g + 0x0000, lut + (i * 0x08) + 2);
 			writew(b + 0x0000, lut + (i * 0x08) + 4);
 		} else {
 			writew(r + 0x6000, lut + (i * 0x20) + 0);
 			writew(g + 0x6000, lut + (i * 0x20) + 2);
 			writew(b + 0x6000, lut + (i * 0x20) + 4);
 		}
 	}
 }
 static int
 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 		     uint32_t handle, uint32_t width, uint32_t height)
 {
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct drm_gem_object *gem;
 	struct nouveau_bo *nvbo;
 	bool visible = (handle != 0);
 	int i, ret = 0;
 	if (visible) {
 		if (width != 64 || height != 64)
 			return -EINVAL;
 		gem = drm_gem_object_lookup(dev, file_priv, handle);
 		if (unlikely(!gem))
 			return -ENOENT;
 		nvbo = nouveau_gem_object(gem);
 		ret = nouveau_bo_map(nvbo);
 		if (ret == 0) {
 			for (i = 0; i < 64 * 64; i++) {
 				u32 v = nouveau_bo_rd32(nvbo, i);
 				nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 			}
 			nouveau_bo_unmap(nvbo);
 		}
 		drm_gem_object_unreference_unlocked(gem);
 	}
 	if (visible != nv_crtc->cursor.visible) {
 		nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
 		nv_crtc->cursor.visible = visible;
 	}
 	return ret;
 }
 static int
 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 {
 	struct nv50_curs *curs = nv50_curs(crtc);
 	struct nv50_chan *chan = nv50_chan(curs);
 	nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
 	nv_wo32(chan->user, 0x0080, 0x00000000);
 	return 0;
 }
 static void
 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 		    uint32_t start, uint32_t size)
 {
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	u32 end = max(start + size, (u32)256);
 	u32 i;
 	for (i = start; i < end; i++) {
 		nv_crtc->lut.r[i] = r[i];
 		nv_crtc->lut.g[i] = g[i];
 		nv_crtc->lut.b[i] = b[i];
 	}
 	nv50_crtc_lut_load(crtc);
 }
 static void
 nv50_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	struct nv50_disp *disp = nv50_disp(crtc->dev);
 	struct nv50_head *head = nv50_head(crtc);
 	nv50_dmac_destroy(disp->core, &head->ovly.base);
 	nv50_pioc_destroy(disp->core, &head->oimm.base);
 	nv50_dmac_destroy(disp->core, &head->sync.base);
 	nv50_pioc_destroy(disp->core, &head->curs.base);
 	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 	if (nv_crtc->cursor.nvbo)
 		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
 	nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 	nouveau_bo_unmap(nv_crtc->lut.nvbo);
 	if (nv_crtc->lut.nvbo)
 		nouveau_bo_unpin(nv_crtc->lut.nvbo);
 	nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 	drm_crtc_cleanup(crtc);
 	kfree(crtc);
 }
 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
 	.dpms = nv50_crtc_dpms,
 	.prepare = nv50_crtc_prepare,
 	.commit = nv50_crtc_commit,
 	.mode_fixup = nv50_crtc_mode_fixup,
 	.mode_set = nv50_crtc_mode_set,
 	.mode_set_base = nv50_crtc_mode_set_base,
 	.mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
 	.load_lut = nv50_crtc_lut_load,
 };
 static const struct drm_crtc_funcs nv50_crtc_func = {
 	.cursor_set = nv50_crtc_cursor_set,
 	.cursor_move = nv50_crtc_cursor_move,
 	.gamma_set = nv50_crtc_gamma_set,
 	.set_config = drm_crtc_helper_set_config,
 	.destroy = nv50_crtc_destroy,
 	.page_flip = nouveau_crtc_page_flip,
 };
 static void
 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
 {
 }
 static void
 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
 {
 }
 static int
 nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
 {
 	struct nv50_disp *disp = nv50_disp(dev);
 	struct nv50_head *head;
 	struct drm_crtc *crtc;
 	int ret, i;
 	head = kzalloc(sizeof(*head), GFP_KERNEL);
 	if (!head)
 		return -ENOMEM;
 	head->base.index = index;
 	head->base.set_dither = nv50_crtc_set_dither;
 	head->base.set_scale = nv50_crtc_set_scale;
 	head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
 	head->base.color_vibrance = 50;
 	head->base.vibrant_hue = 0;
 	head->base.cursor.set_offset = nv50_cursor_set_offset;
 	head->base.cursor.set_pos = nv50_cursor_set_pos;
 	for (i = 0; i < 256; i++) {
 		head->base.lut.r[i] = i << 8;
 		head->base.lut.g[i] = i << 8;
 		head->base.lut.b[i] = i << 8;
 	}
 	crtc = &head->base.base;
 	drm_crtc_init(dev, crtc, &nv50_crtc_func);
 	drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
 	drm_mode_crtc_set_gamma_size(crtc, 256);
 	ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 			     0, 0x0000, NULL, &head->base.lut.nvbo);
 	if (!ret) {
 		ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
 		if (!ret) {
 			ret = nouveau_bo_map(head->base.lut.nvbo);
 			if (ret)
 				nouveau_bo_unpin(head->base.lut.nvbo);
 		}
 		if (ret)
 			nouveau_bo_ref(NULL, &head->base.lut.nvbo);
 	}
 	if (ret)
 		goto out;
 	nv50_crtc_lut_load(crtc);
 	/* allocate cursor resources */
 	ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
 			      &(struct nv50_display_curs_class) {
 					.head = index,
 			      }, sizeof(struct nv50_display_curs_class),
 			      &head->curs.base);
 	if (ret)
 		goto out;
 	ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 			     0, 0x0000, NULL, &head->base.cursor.nvbo);
 	if (!ret) {
 		ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
 		if (!ret) {
 			ret = nouveau_bo_map(head->base.cursor.nvbo);
 			if (ret)
 				nouveau_bo_unpin(head->base.lut.nvbo);
 		}
 		if (ret)
 			nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
 	}
 	if (ret)
 		goto out;
 	/* allocate page flip / sync resources */
 	ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
 			      &(struct nv50_display_sync_class) {
 					.pushbuf = EVO_PUSH_HANDLE(SYNC, index),
 					.head = index,
 			      }, sizeof(struct nv50_display_sync_class),
 			      disp->sync->bo.offset, &head->sync.base);
 	if (ret)
 		goto out;
 	head->sync.addr = EVO_FLIP_SEM0(index);
 	head->sync.data = 0x00000000;
 	/* allocate overlay resources */
 	ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
 			      &(struct nv50_display_oimm_class) {
 					.head = index,
 			      }, sizeof(struct nv50_display_oimm_class),
 			      &head->oimm.base);
 	if (ret)
 		goto out;
 	ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
 			      &(struct nv50_display_ovly_class) {
 					.pushbuf = EVO_PUSH_HANDLE(OVLY, index),
 					.head = index,
 			      }, sizeof(struct nv50_display_ovly_class),
 			      disp->sync->bo.offset, &head->ovly.base);
 	if (ret)
 		goto out;
 out:
 	if (ret)
 		nv50_crtc_destroy(crtc);
 	return ret;
 }
 /******************************************************************************
  * DAC
  *****************************************************************************/
 static void
 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	int or = nv_encoder->or;
 	u32 dpms_ctrl;
 	dpms_ctrl = 0x00000000;
 	if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 		dpms_ctrl |= 0x00000001;
 	if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 		dpms_ctrl |= 0x00000004;
 	nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
 }
 static bool
 nv50_dac_mode_fixup(struct drm_encoder *encoder,
 		    const struct drm_display_mode *mode,
 		    struct drm_display_mode *adjusted_mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_connector *nv_connector;
 	nv_connector = nouveau_encoder_connector_get(nv_encoder);
 	if (nv_connector && nv_connector->native_mode) {
 		if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 			int id = adjusted_mode->base.id;
 			*adjusted_mode = *nv_connector->native_mode;
 			adjusted_mode->base.id = id;
 		}
 	}
 	return true;
 }
 static void
 nv50_dac_commit(struct drm_encoder *encoder)
 {
 }
 static void
 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 		  struct drm_display_mode *adjusted_mode)
 {
 	struct nv50_mast *mast = nv50_mast(encoder->dev);
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 	u32 *push;
 	nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 	push = evo_wait(mast, 8);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			u32 syncs = 0x00000000;
 			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 				syncs |= 0x00000001;
 			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 				syncs |= 0x00000002;
 			evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
 			evo_data(push, 1 << nv_crtc->index);
 			evo_data(push, syncs);
 		} else {
 			u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
 			u32 syncs = 0x00000001;
 			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 				syncs |= 0x00000008;
 			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 				syncs |= 0x00000010;
 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 				magic |= 0x00000001;
 			evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
 			evo_data(push, syncs);
 			evo_data(push, magic);
 			evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
 			evo_data(push, 1 << nv_crtc->index);
 		}
 		evo_kick(push, mast);
 	}
 	nv_encoder->crtc = encoder->crtc;
 }
 static void
 nv50_dac_disconnect(struct drm_encoder *encoder)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nv50_mast *mast = nv50_mast(encoder->dev);
 	const int or = nv_encoder->or;
 	u32 *push;
 	if (nv_encoder->crtc) {
 		nv50_crtc_prepare(nv_encoder->crtc);
 		push = evo_wait(mast, 4);
 		if (push) {
 			if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 				evo_mthd(push, 0x0400 + (or * 0x080), 1);
 				evo_data(push, 0x00000000);
 			} else {
 				evo_mthd(push, 0x0180 + (or * 0x020), 1);
 				evo_data(push, 0x00000000);
 			}
 			evo_kick(push, mast);
 		}
 	}
 	nv_encoder->crtc = NULL;
 }
 static enum drm_connector_status
 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 {
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	int ret, or = nouveau_encoder(encoder)->or;
 	u32 load = 0;
 	ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
 	if (ret || load != 7)
 		return connector_status_disconnected;
 	return connector_status_connected;
 }
 static void
 nv50_dac_destroy(struct drm_encoder *encoder)
 {
 	drm_encoder_cleanup(encoder);
 	kfree(encoder);
 }
 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
 	.dpms = nv50_dac_dpms,
 	.mode_fixup = nv50_dac_mode_fixup,
 	.prepare = nv50_dac_disconnect,
 	.commit = nv50_dac_commit,
 	.mode_set = nv50_dac_mode_set,
 	.disable = nv50_dac_disconnect,
 	.get_crtc = nv50_display_crtc_get,
 	.detect = nv50_dac_detect
 };
 static const struct drm_encoder_funcs nv50_dac_func = {
 	.destroy = nv50_dac_destroy,
 };
 static int
 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 {
 	struct nouveau_drm *drm = nouveau_drm(connector->dev);
 	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
 	struct nouveau_encoder *nv_encoder;
 	struct drm_encoder *encoder;
 	int type = DRM_MODE_ENCODER_DAC;
 	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 	if (!nv_encoder)
 		return -ENOMEM;
 	nv_encoder->dcb = dcbe;
 	nv_encoder->or = ffs(dcbe->or) - 1;
 	nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
 	encoder = to_drm_encoder(nv_encoder);
 	encoder->possible_crtcs = dcbe->heads;
 	encoder->possible_clones = 0;
 	drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
 	drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
 	drm_mode_connector_attach_encoder(connector, encoder);
 	return 0;
 }
 /******************************************************************************
  * Audio
  *****************************************************************************/
 static void
 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_connector *nv_connector;
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	nv_connector = nouveau_encoder_connector_get(nv_encoder);
 	if (!drm_detect_monitor_audio(nv_connector->edid))
 		return;
 	drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
 	nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
 			    nv_connector->base.eld,
 			    nv_connector->base.eld[2] * 4);
 }
 static void
 nv50_audio_disconnect(struct drm_encoder *encoder)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
 }
 /******************************************************************************
  * HDMI
  *****************************************************************************/
 static void
 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 	struct nouveau_connector *nv_connector;
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
 	u32 rekey = 56; /* binary driver, and tegra constant */
 	u32 max_ac_packet;
 	nv_connector = nouveau_encoder_connector_get(nv_encoder);
 	if (!drm_detect_hdmi_monitor(nv_connector->edid))
 		return;
 	max_ac_packet  = mode->htotal - mode->hdisplay;
 	max_ac_packet -= rekey;
 	max_ac_packet -= 18; /* constant from tegra */
 	max_ac_packet /= 32;
 	nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
 			    NV84_DISP_SOR_HDMI_PWR_STATE_ON |
 			    (max_ac_packet << 16) | rekey);
 	nv50_audio_mode_set(encoder, mode);
 }
 static void
 nv50_hdmi_disconnect(struct drm_encoder *encoder)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
 	nv50_audio_disconnect(encoder);
 	nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
 }
 /******************************************************************************
  * SOR
  *****************************************************************************/
 static void
 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct drm_device *dev = encoder->dev;
 	struct nv50_disp *disp = nv50_disp(dev);
 	struct drm_encoder *partner;
 	int or = nv_encoder->or;
 	nv_encoder->last_dpms = mode;
 	list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
 		struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
 		if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
 			continue;
 		if (nv_partner != nv_encoder &&
 		    nv_partner->dcb->or == nv_encoder->dcb->or) {
 			if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
 				return;
 			break;
 		}
 	}
 	nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
 }
 static bool
 nv50_sor_mode_fixup(struct drm_encoder *encoder,
 		    const struct drm_display_mode *mode,
 		    struct drm_display_mode *adjusted_mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_connector *nv_connector;
 	nv_connector = nouveau_encoder_connector_get(nv_encoder);
 	if (nv_connector && nv_connector->native_mode) {
 		if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 			int id = adjusted_mode->base.id;
 			*adjusted_mode = *nv_connector->native_mode;
 			adjusted_mode->base.id = id;
 		}
 	}
 	return true;
 }
 static void
 nv50_sor_disconnect(struct drm_encoder *encoder)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nv50_mast *mast = nv50_mast(encoder->dev);
 	const int or = nv_encoder->or;
 	u32 *push;
 	if (nv_encoder->crtc) {
 		nv50_crtc_prepare(nv_encoder->crtc);
 		push = evo_wait(mast, 4);
 		if (push) {
 			if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 				evo_mthd(push, 0x0600 + (or * 0x40), 1);
 				evo_data(push, 0x00000000);
 			} else {
 				evo_mthd(push, 0x0200 + (or * 0x20), 1);
 				evo_data(push, 0x00000000);
 			}
 			evo_kick(push, mast);
 		}
 		nv50_hdmi_disconnect(encoder);
 	}
 	nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 	nv_encoder->crtc = NULL;
 }
 static void
 nv50_sor_commit(struct drm_encoder *encoder)
 {
 }
 static void
 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
 		  struct drm_display_mode *mode)
 {
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	struct nv50_mast *mast = nv50_mast(encoder->dev);
 	struct drm_device *dev = encoder->dev;
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 	struct nouveau_connector *nv_connector;
 	struct nvbios *bios = &drm->vbios;
 	u32 *push, lvds = 0;
 	u8 owner = 1 << nv_crtc->index;
 	u8 proto = 0xf;
 	u8 depth = 0x0;
 	nv_connector = nouveau_encoder_connector_get(nv_encoder);
 	switch (nv_encoder->dcb->type) {
 	case DCB_OUTPUT_TMDS:
 		if (nv_encoder->dcb->sorconf.link & 1) {
 			if (mode->clock < 165000)
 				proto = 0x1;
 			else
 				proto = 0x5;
 		} else {
 			proto = 0x2;
 		}
 		nv50_hdmi_mode_set(encoder, mode);
 		break;
 	case DCB_OUTPUT_LVDS:
 		proto = 0x0;
 		if (bios->fp_no_ddc) {
 			if (bios->fp.dual_link)
 				lvds |= 0x0100;
 			if (bios->fp.if_is_24bit)
 				lvds |= 0x0200;
 		} else {
 			if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 				if (((u8 *)nv_connector->edid)[121] == 2)
 					lvds |= 0x0100;
 			} else
 			if (mode->clock >= bios->fp.duallink_transition_clk) {
 				lvds |= 0x0100;
 			}
 			if (lvds & 0x0100) {
 				if (bios->fp.strapless_is_24bit & 2)
 					lvds |= 0x0200;
 			} else {
 				if (bios->fp.strapless_is_24bit & 1)
 					lvds |= 0x0200;
 			}
 			if (nv_connector->base.display_info.bpc == 8)
 				lvds |= 0x0200;
 		}
 		nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
 		break;
 	case DCB_OUTPUT_DP:
 		if (nv_connector->base.display_info.bpc == 6) {
 			nv_encoder->dp.datarate = mode->clock * 18 / 8;
 			depth = 0x2;
 		} else
 		if (nv_connector->base.display_info.bpc == 8) {
 			nv_encoder->dp.datarate = mode->clock * 24 / 8;
 			depth = 0x5;
 		} else {
 			nv_encoder->dp.datarate = mode->clock * 30 / 8;
 			depth = 0x6;
 		}
 		if (nv_encoder->dcb->sorconf.link & 1)
 			proto = 0x8;
 		else
 			proto = 0x9;
 		break;
 	default:
 		BUG_ON(1);
 		break;
 	}
 	nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
 	push = evo_wait(nv50_mast(dev), 8);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_CLASS) {
 			u32 ctrl = (depth << 16) | (proto << 8) | owner;
 			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 				ctrl |= 0x00001000;
 			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 				ctrl |= 0x00002000;
 			evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
 			evo_data(push, ctrl);
 		} else {
 			u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
 			u32 syncs = 0x00000001;
 			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 				syncs |= 0x00000008;
 			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 				syncs |= 0x00000010;
 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 				magic |= 0x00000001;
 			evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
 			evo_data(push, syncs | (depth << 6));
 			evo_data(push, magic);
 			evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
 			evo_data(push, owner | (proto << 8));
 		}
 		evo_kick(push, mast);
 	}
 	nv_encoder->crtc = encoder->crtc;
 }
 static void
 nv50_sor_destroy(struct drm_encoder *encoder)
 {
 	drm_encoder_cleanup(encoder);
 	kfree(encoder);
 }
 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
 	.dpms = nv50_sor_dpms,
 	.mode_fixup = nv50_sor_mode_fixup,
 	.prepare = nv50_sor_disconnect,
 	.commit = nv50_sor_commit,
 	.mode_set = nv50_sor_mode_set,
 	.disable = nv50_sor_disconnect,
 	.get_crtc = nv50_display_crtc_get,
 };
 static const struct drm_encoder_funcs nv50_sor_func = {
 	.destroy = nv50_sor_destroy,
 };
 static int
 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
 {
 	struct nouveau_drm *drm = nouveau_drm(connector->dev);
 	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
 	struct nouveau_encoder *nv_encoder;
 	struct drm_encoder *encoder;
 	int type;
 	switch (dcbe->type) {
 	case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
 	case DCB_OUTPUT_TMDS:
 	case DCB_OUTPUT_DP:
 	default:
 		type = DRM_MODE_ENCODER_TMDS;
 		break;
 	}
 	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 	if (!nv_encoder)
 		return -ENOMEM;
 	nv_encoder->dcb = dcbe;
 	nv_encoder->or = ffs(dcbe->or) - 1;
 	nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
 	nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 	encoder = to_drm_encoder(nv_encoder);
 	encoder->possible_crtcs = dcbe->heads;
 	encoder->possible_clones = 0;
 	drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
 	drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
 	drm_mode_connector_attach_encoder(connector, encoder);
 	return 0;
 }
 /******************************************************************************
  * PIOR
  *****************************************************************************/
 static void
 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
 	u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
 	u32 ctrl = (mode == DRM_MODE_DPMS_ON);
 	nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
 }
 static bool
 nv50_pior_mode_fixup(struct drm_encoder *encoder,
 		     const struct drm_display_mode *mode,
 		     struct drm_display_mode *adjusted_mode)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_connector *nv_connector;
 	nv_connector = nouveau_encoder_connector_get(nv_encoder);
 	if (nv_connector && nv_connector->native_mode) {
 		if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 			int id = adjusted_mode->base.id;
 			*adjusted_mode = *nv_connector->native_mode;
 			adjusted_mode->base.id = id;
 		}
 	}
 	adjusted_mode->clock *= 2;
 	return true;
 }
 static void
 nv50_pior_commit(struct drm_encoder *encoder)
 {
 }
 static void
 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 		   struct drm_display_mode *adjusted_mode)
 {
 	struct nv50_mast *mast = nv50_mast(encoder->dev);
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 	struct nouveau_connector *nv_connector;
 	u8 owner = 1 << nv_crtc->index;
 	u8 proto, depth;
 	u32 *push;
 	nv_connector = nouveau_encoder_connector_get(nv_encoder);
 	switch (nv_connector->base.display_info.bpc) {
 	case 10: depth = 0x6; break;
 	case  8: depth = 0x5; break;
 	case  6: depth = 0x2; break;
 	default: depth = 0x0; break;
 	}
 	switch (nv_encoder->dcb->type) {
 	case DCB_OUTPUT_TMDS:
 	case DCB_OUTPUT_DP:
 		proto = 0x0;
 		break;
 	default:
 		BUG_ON(1);
 		break;
 	}
 	nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
 	push = evo_wait(mast, 8);
 	if (push) {
 		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 			u32 ctrl = (depth << 16) | (proto << 8) | owner;
 			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 				ctrl |= 0x00001000;
 			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 				ctrl |= 0x00002000;
 			evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
 			evo_data(push, ctrl);
 		}
 		evo_kick(push, mast);
 	}
 	nv_encoder->crtc = encoder->crtc;
 }
 static void
 nv50_pior_disconnect(struct drm_encoder *encoder)
 {
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nv50_mast *mast = nv50_mast(encoder->dev);
 	const int or = nv_encoder->or;
 	u32 *push;
 	if (nv_encoder->crtc) {
 		nv50_crtc_prepare(nv_encoder->crtc);
 		push = evo_wait(mast, 4);
 		if (push) {
 			if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 				evo_mthd(push, 0x0700 + (or * 0x040), 1);
 				evo_data(push, 0x00000000);
 			}
 			evo_kick(push, mast);
 		}
 	}
 	nv_encoder->crtc = NULL;
 }
 static void
 nv50_pior_destroy(struct drm_encoder *encoder)
 {
 	drm_encoder_cleanup(encoder);
 	kfree(encoder);
 }
 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
 	.dpms = nv50_pior_dpms,
 	.mode_fixup = nv50_pior_mode_fixup,
 	.prepare = nv50_pior_disconnect,
 	.commit = nv50_pior_commit,
 	.mode_set = nv50_pior_mode_set,
 	.disable = nv50_pior_disconnect,
 	.get_crtc = nv50_display_crtc_get,
 };
 static const struct drm_encoder_funcs nv50_pior_func = {
 	.destroy = nv50_pior_destroy,
 };
 static int
 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
 {
 	struct nouveau_drm *drm = nouveau_drm(connector->dev);
 	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
 	struct nouveau_i2c_port *ddc = NULL;
 	struct nouveau_encoder *nv_encoder;
 	struct drm_encoder *encoder;
 	int type;
 	switch (dcbe->type) {
 	case DCB_OUTPUT_TMDS:
 		ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
 		type = DRM_MODE_ENCODER_TMDS;
 		break;
 	case DCB_OUTPUT_DP:
 		ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
 		type = DRM_MODE_ENCODER_TMDS;
 		break;
 	default:
 		return -ENODEV;
 	}
 	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 	if (!nv_encoder)
 		return -ENOMEM;
 	nv_encoder->dcb = dcbe;
 	nv_encoder->or = ffs(dcbe->or) - 1;
 	nv_encoder->i2c = ddc;
 	encoder = to_drm_encoder(nv_encoder);
 	encoder->possible_crtcs = dcbe->heads;
 	encoder->possible_clones = 0;
 	drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
 	drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
 	drm_mode_connector_attach_encoder(connector, encoder);
 	return 0;
 }
 /******************************************************************************
  * Init
  *****************************************************************************/
 void
 nv50_display_fini(struct drm_device *dev)
 {
 }
 int
 nv50_display_init(struct drm_device *dev)
 {
 	struct nv50_disp *disp = nv50_disp(dev);
 	struct drm_crtc *crtc;
 	u32 *push;
 	push = evo_wait(nv50_mast(dev), 32);
 	if (!push)
 		return -EBUSY;
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		struct nv50_sync *sync = nv50_sync(crtc);
 		nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
 	}
 	evo_mthd(push, 0x0088, 1);
 	evo_data(push, NvEvoSync);
 	evo_kick(push, nv50_mast(dev));
 	return 0;
 }
 void
 nv50_display_destroy(struct drm_device *dev)
 {
 	struct nv50_disp *disp = nv50_disp(dev);
 	nv50_dmac_destroy(disp->core, &disp->mast.base);
 	nouveau_bo_unmap(disp->sync);
 	if (disp->sync)
 		nouveau_bo_unpin(disp->sync);
 	nouveau_bo_ref(NULL, &disp->sync);
 	nouveau_display(dev)->priv = NULL;
 	kfree(disp);
 }
 int
 nv50_display_create(struct drm_device *dev)
 {
 	static const u16 oclass[] = {
+		NVF0_DISP_CLASS,
 		NVE0_DISP_CLASS,
 		NVD0_DISP_CLASS,
 		NVA3_DISP_CLASS,
 		NV94_DISP_CLASS,
 		NVA0_DISP_CLASS,
 		NV84_DISP_CLASS,
 		NV50_DISP_CLASS,
 	};
 	struct nouveau_device *device = nouveau_dev(dev);
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct dcb_table *dcb = &drm->vbios.dcb;
 	struct drm_connector *connector, *tmp;
 	struct nv50_disp *disp;
 	struct dcb_output *dcbe;
 	int crtcs, ret, i;
 	disp = kzalloc(sizeof(*disp), GFP_KERNEL);
 	if (!disp)
 		return -ENOMEM;
 	nouveau_display(dev)->priv = disp;
 	nouveau_display(dev)->dtor = nv50_display_destroy;
 	nouveau_display(dev)->init = nv50_display_init;
 	nouveau_display(dev)->fini = nv50_display_fini;
 	/* small shared memory area we use for notifiers and semaphores */
 	ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
 			     0, 0x0000, NULL, &disp->sync);
 	if (!ret) {
 		ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
 		if (!ret) {
 			ret = nouveau_bo_map(disp->sync);
 			if (ret)
 				nouveau_bo_unpin(disp->sync);
 		}
 		if (ret)
 			nouveau_bo_ref(NULL, &disp->sync);
 	}
 	if (ret)
 		goto out;
 	/* attempt to allocate a supported evo display class */
 	ret = -ENODEV;
 	for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
 		ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
 					 0xd1500000, oclass[i], NULL, 0,
 					 &disp->core);
 	}
 	if (ret)
 		goto out;
 	/* allocate master evo channel */
 	ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
 			      &(struct nv50_display_mast_class) {
 					.pushbuf = EVO_PUSH_HANDLE(MAST, 0),
 			      }, sizeof(struct nv50_display_mast_class),
 			      disp->sync->bo.offset, &disp->mast.base);
 	if (ret)
 		goto out;
 	/* create crtc objects to represent the hw heads */
 	if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
 		crtcs = nv_rd32(device, 0x022448);
 	else
 		crtcs = 2;
 	for (i = 0; i < crtcs; i++) {
 		ret = nv50_crtc_create(dev, disp->core, i);
 		if (ret)
 			goto out;
 	}
 	/* create encoder/connector objects based on VBIOS DCB table */
 	for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
 		connector = nouveau_connector_create(dev, dcbe->connector);
 		if (IS_ERR(connector))
 			continue;
 		if (dcbe->location == DCB_LOC_ON_CHIP) {
 			switch (dcbe->type) {
 			case DCB_OUTPUT_TMDS:
 			case DCB_OUTPUT_LVDS:
 			case DCB_OUTPUT_DP:
 				ret = nv50_sor_create(connector, dcbe);
 				break;
 			case DCB_OUTPUT_ANALOG:
 				ret = nv50_dac_create(connector, dcbe);
 				break;
 			default:
 				ret = -ENODEV;
 				break;
 			}
 		} else {
 			ret = nv50_pior_create(connector, dcbe);
 		}
 		if (ret) {
 			NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
 				     dcbe->location, dcbe->type,
 				     ffs(dcbe->or) - 1, ret);
 			ret = 0;
 		}
 	}
 	/* cull any connectors we created that don't have an encoder */
 	list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
 		if (connector->encoder_ids[0])
 			continue;
 		NV_WARN(drm, "%s has no encoders, removing\n",
 			drm_get_connector_name(connector));
 		connector->funcs->destroy(connector);
 	}
 out:
 	if (ret)
 		nv50_display_destroy(dev);
 	return ret;
 }