Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

Add GK110 modesetting suport. * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nve0: recognise nvf0 as a kepler board (GK110) drm/nouveau: force noaccel when no PFIFO support present drm/nvf0/disp: expose display class 2.2

Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
Add GK110 modesetting suport. * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nve0: recognise nvf0 as a kepler board (GK110) drm/nouveau: force noaccel when no PFIFO support present drm/nvf0/disp: expose display class 2.2
Dave Airlie
2 parents b11b88ef0e 7b4f638b3a
Showing 9 changed files Side-by-side Diff
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/core/engine/device/base.c
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
drivers/gpu/drm/nouveau/core/include/core/class.h
drivers/gpu/drm/nouveau/core/include/engine/disp.h
drivers/gpu/drm/nouveau/nouveau_drm.c
drivers/gpu/drm/nouveau/nv50_display.c
@@ -160,6 +160,7 @@
 nouveau-y += core/engine/disp/nva3.o
 nouveau-y += core/engine/disp/nvd0.o
 nouveau-y += core/engine/disp/nve0.o
+nouveau-y += core/engine/disp/nvf0.o
 nouveau-y += core/engine/disp/dacnv50.o
 nouveau-y += core/engine/disp/dport.o
 nouveau-y += core/engine/disp/hdanva3.o
@@ -172,7 +172,8 @@
 			case 0xa0: device->card_type = NV_50; break;
 			case 0xc0: device->card_type = NV_C0; break;
 			case 0xd0: device->card_type = NV_D0; break;
-			case 0xe0: device->card_type = NV_E0; break;
+			case 0xe0:
+			case 0xf0: device->card_type = NV_E0; break;
 			default:
 				break;
 			}
@@ -141,6 +141,40 @@
 		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 		break;
+	case 0xf0:
+		device->cname = "GK110";
+		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
+		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
+		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
+		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
+		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
+		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
+		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
+		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
+		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
+		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
+		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
+		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
+		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
+		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
+		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
+		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
+#if 0
+		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
+#endif
+		device->oclass[NVDEV_ENGINE_DISP   ] = &nvf0_disp_oclass;
+#if 0
+		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
+		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
+		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
+		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
+		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
+		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+#endif
+		break;
 	default:
 		nv_fatal(device, "unknown Kepler chipset\n");
 		return -EINVAL;
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <engine/software.h>
+#include <engine/disp.h>
+
+#include <core/class.h>
+
+#include "nv50.h"
+
+static struct nouveau_oclass
+nvf0_disp_sclass[] = {
+	{ NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
+	{ NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
+	{ NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
+	{ NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
+	{ NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
+	{}
+};
+
+static struct nouveau_oclass
+nvf0_disp_base_oclass[] = {
+	{ NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
+	{}
+};
+
+static int
+nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+	       struct nouveau_oclass *oclass, void *data, u32 size,
+	       struct nouveau_object **pobject)
+{
+	struct nv50_disp_priv *priv;
+	int heads = nv_rd32(parent, 0x022448);
+	int ret;
+
+	ret = nouveau_disp_create(parent, engine, oclass, heads,
+				  "PDISP", "display", &priv);
+	*pobject = nv_object(priv);
+	if (ret)
+		return ret;
+
+	nv_engine(priv)->sclass = nvf0_disp_base_oclass;
+	nv_engine(priv)->cclass = &nv50_disp_cclass;
+	nv_subdev(priv)->intr = nvd0_disp_intr;
+	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
+	priv->sclass = nvf0_disp_sclass;
+	priv->head.nr = heads;
+	priv->dac.nr = 3;
+	priv->sor.nr = 4;
+	priv->dac.power = nv50_dac_power;
+	priv->dac.sense = nv50_dac_sense;
+	priv->sor.power = nv50_sor_power;
+	priv->sor.hda_eld = nvd0_hda_eld;
+	priv->sor.hdmi = nvd0_hdmi_ctrl;
+	priv->sor.dp = &nvd0_sor_dp_func;
+	return 0;
+}
+
+struct nouveau_oclass
+nvf0_disp_oclass = {
+	.handle = NV_ENGINE(DISP, 0x92),
+	.ofuncs = &(struct nouveau_ofuncs) {
+		.ctor = nvf0_disp_ctor,
+		.dtor = _nouveau_disp_dtor,
+		.init = _nouveau_disp_init,
+		.fini = _nouveau_disp_fini,
+	},
+};
@@ -50,6 +50,9 @@
 		case NVE0_DISP_MAST_CLASS:
 		case NVE0_DISP_SYNC_CLASS:
 		case NVE0_DISP_OVLY_CLASS:
+		case NVF0_DISP_MAST_CLASS:
+		case NVF0_DISP_SYNC_CLASS:
+		case NVF0_DISP_OVLY_CLASS:
 			break;
 		default:
 			return -EINVAL;
@@ -169,6 +169,7 @@
  * 8570: NVA3_DISP
  * 9070: NVD0_DISP
  * 9170: NVE0_DISP
+ * 9270: NVF0_DISP
  */
  
 #define NV50_DISP_CLASS                                              0x00005070
@@ -178,6 +179,7 @@
 #define NVA3_DISP_CLASS                                              0x00008570
 #define NVD0_DISP_CLASS                                              0x00009070
 #define NVE0_DISP_CLASS                                              0x00009170
+#define NVF0_DISP_CLASS                                              0x00009270
  
 #define NV50_DISP_SOR_MTHD                                           0x00010000
 #define NV50_DISP_SOR_MTHD_TYPE                                      0x0000f000
@@ -246,6 +248,7 @@
  * 857a: NVA3_DISP_CURS
  * 907a: NVD0_DISP_CURS
  * 917a: NVE0_DISP_CURS
+ * 927a: NVF0_DISP_CURS
  */
  
 #define NV50_DISP_CURS_CLASS                                         0x0000507a
@@ -255,6 +258,7 @@
 #define NVA3_DISP_CURS_CLASS                                         0x0000857a
 #define NVD0_DISP_CURS_CLASS                                         0x0000907a
 #define NVE0_DISP_CURS_CLASS                                         0x0000917a
+#define NVF0_DISP_CURS_CLASS                                         0x0000927a
  
 struct nv50_display_curs_class {
 	u32 head;
@@ -267,6 +271,7 @@
  * 857b: NVA3_DISP_OIMM
  * 907b: NVD0_DISP_OIMM
  * 917b: NVE0_DISP_OIMM
+ * 927b: NVE0_DISP_OIMM
  */
  
 #define NV50_DISP_OIMM_CLASS                                         0x0000507b
@@ -276,6 +281,7 @@
 #define NVA3_DISP_OIMM_CLASS                                         0x0000857b
 #define NVD0_DISP_OIMM_CLASS                                         0x0000907b
 #define NVE0_DISP_OIMM_CLASS                                         0x0000917b
+#define NVF0_DISP_OIMM_CLASS                                         0x0000927b
  
 struct nv50_display_oimm_class {
 	u32 head;
@@ -288,6 +294,7 @@
  * 857c: NVA3_DISP_SYNC
  * 907c: NVD0_DISP_SYNC
  * 917c: NVE0_DISP_SYNC
+ * 927c: NVF0_DISP_SYNC
  */
  
 #define NV50_DISP_SYNC_CLASS                                         0x0000507c
@@ -297,6 +304,7 @@
 #define NVA3_DISP_SYNC_CLASS                                         0x0000857c
 #define NVD0_DISP_SYNC_CLASS                                         0x0000907c
 #define NVE0_DISP_SYNC_CLASS                                         0x0000917c
+#define NVF0_DISP_SYNC_CLASS                                         0x0000927c
  
 struct nv50_display_sync_class {
 	u32 pushbuf;
@@ -310,6 +318,7 @@
  * 857d: NVA3_DISP_MAST
  * 907d: NVD0_DISP_MAST
  * 917d: NVE0_DISP_MAST
+ * 927d: NVF0_DISP_MAST
  */
  
 #define NV50_DISP_MAST_CLASS                                         0x0000507d
@@ -319,6 +328,7 @@
 #define NVA3_DISP_MAST_CLASS                                         0x0000857d
 #define NVD0_DISP_MAST_CLASS                                         0x0000907d
 #define NVE0_DISP_MAST_CLASS                                         0x0000917d
+#define NVF0_DISP_MAST_CLASS                                         0x0000927d
  
 struct nv50_display_mast_class {
 	u32 pushbuf;
@@ -331,6 +341,7 @@
  * 857e: NVA3_DISP_OVLY
  * 907e: NVD0_DISP_OVLY
  * 917e: NVE0_DISP_OVLY
+ * 927e: NVF0_DISP_OVLY
  */
  
 #define NV50_DISP_OVLY_CLASS                                         0x0000507e
@@ -340,6 +351,7 @@
 #define NVA3_DISP_OVLY_CLASS                                         0x0000857e
 #define NVD0_DISP_OVLY_CLASS                                         0x0000907e
 #define NVE0_DISP_OVLY_CLASS                                         0x0000917e
+#define NVF0_DISP_OVLY_CLASS                                         0x0000927e
  
 struct nv50_display_ovly_class {
 	u32 pushbuf;
@@ -44,6 +44,7 @@
 extern struct nouveau_oclass nva3_disp_oclass;
 extern struct nouveau_oclass nvd0_disp_oclass;
 extern struct nouveau_oclass nve0_disp_oclass;
+extern struct nouveau_oclass nvf0_disp_oclass;
  
 #endif
@@ -33,6 +33,7 @@
  
 #include <engine/device.h>
 #include <engine/disp.h>
+#include <engine/fifo.h>
  
 #include <subdev/vm.h>
  
@@ -164,7 +165,7 @@
 	u32 arg0, arg1;
 	int ret;
  
-	if (nouveau_noaccel)
+	if (nouveau_noaccel || !nouveau_fifo(device) /*XXX*/)
 		return;
  
 	/* initialise synchronisation routines */
@@ -2174,6 +2174,7 @@
 nv50_display_create(struct drm_device *dev)
 {
 	static const u16 oclass[] = {
+		NVF0_DISP_CLASS,
 		NVE0_DISP_CLASS,
 		NVD0_DISP_CLASS,
 		NVA3_DISP_CLASS,
...	...	@@ -160,6 +160,7 @@
160	160	nouveau-y += core/engine/disp/nva3.o
161	161	nouveau-y += core/engine/disp/nvd0.o
162	162	nouveau-y += core/engine/disp/nve0.o
	163	+nouveau-y += core/engine/disp/nvf0.o
163	164	nouveau-y += core/engine/disp/dacnv50.o
164	165	nouveau-y += core/engine/disp/dport.o
165	166	nouveau-y += core/engine/disp/hdanva3.o
...	...	@@ -172,7 +172,8 @@
172	172	case 0xa0: device->card_type = NV_50; break;
173	173	case 0xc0: device->card_type = NV_C0; break;
174	174	case 0xd0: device->card_type = NV_D0; break;
175		- case 0xe0: device->card_type = NV_E0; break;
	175	+ case 0xe0:
	176	+ case 0xf0: device->card_type = NV_E0; break;
176	177	default:
177	178	break;
178	179	}
...	...	@@ -141,6 +141,40 @@
141	141	device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
142	142	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
143	143	break;
	144	+ case 0xf0:
	145	+ device->cname = "GK110";
	146	+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
	147	+ device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
	148	+ device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
	149	+ device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
	150	+ device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
	151	+ device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
	152	+ device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
	153	+ device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
	154	+ device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
	155	+ device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
	156	+ device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
	157	+ device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
	158	+ device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
	159	+ device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	160	+ device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	161	+ device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
	162	+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
	163	+#if 0
	164	+ device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
	165	+ device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	166	+ device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass;
	167	+#endif
	168	+ device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
	169	+#if 0
	170	+ device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
	171	+ device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
	172	+ device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
	173	+ device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
	174	+ device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
	175	+ device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
	176	+#endif
	177	+ break;
144	178	default:
145	179	nv_fatal(device, "unknown Kepler chipset\n");
146	180	return -EINVAL;
	1	+/*
	2	+ * Copyright 2012 Red Hat Inc.
	3	+ *
	4	+ * Permission is hereby granted, free of charge, to any person obtaining a
	5	+ * copy of this software and associated documentation files (the "Software"),
	6	+ * to deal in the Software without restriction, including without limitation
	7	+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	+ * and/or sell copies of the Software, and to permit persons to whom the
	9	+ * Software is furnished to do so, subject to the following conditions:
	10	+ *
	11	+ * The above copyright notice and this permission notice shall be included in
	12	+ * all copies or substantial portions of the Software.
	13	+ *
	14	+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	+ * OTHER DEALINGS IN THE SOFTWARE.
	21	+ *
	22	+ * Authors: Ben Skeggs
	23	+ */
	24	+
	25	+#include <engine/software.h>
	26	+#include <engine/disp.h>
	27	+
	28	+#include <core/class.h>
	29	+
	30	+#include "nv50.h"
	31	+
	32	+static struct nouveau_oclass
	33	+nvf0_disp_sclass[] = {
	34	+ { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
	35	+ { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
	36	+ { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
	37	+ { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
	38	+ { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
	39	+ {}
	40	+};
	41	+
	42	+static struct nouveau_oclass
	43	+nvf0_disp_base_oclass[] = {
	44	+ { NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
	45	+ {}
	46	+};
	47	+
	48	+static int
	49	+nvf0_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
	50	+ struct nouveau_oclass oclass, void data, u32 size,
	51	+ struct nouveau_object **pobject)
	52	+{
	53	+ struct nv50_disp_priv *priv;
	54	+ int heads = nv_rd32(parent, 0x022448);
	55	+ int ret;
	56	+
	57	+ ret = nouveau_disp_create(parent, engine, oclass, heads,
	58	+ "PDISP", "display", &priv);
	59	+ *pobject = nv_object(priv);
	60	+ if (ret)
	61	+ return ret;
	62	+
	63	+ nv_engine(priv)->sclass = nvf0_disp_base_oclass;
	64	+ nv_engine(priv)->cclass = &nv50_disp_cclass;
	65	+ nv_subdev(priv)->intr = nvd0_disp_intr;
	66	+ INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
	67	+ priv->sclass = nvf0_disp_sclass;
	68	+ priv->head.nr = heads;
	69	+ priv->dac.nr = 3;
	70	+ priv->sor.nr = 4;
	71	+ priv->dac.power = nv50_dac_power;
	72	+ priv->dac.sense = nv50_dac_sense;
	73	+ priv->sor.power = nv50_sor_power;
	74	+ priv->sor.hda_eld = nvd0_hda_eld;
	75	+ priv->sor.hdmi = nvd0_hdmi_ctrl;
	76	+ priv->sor.dp = &nvd0_sor_dp_func;
	77	+ return 0;
	78	+}
	79	+
	80	+struct nouveau_oclass
	81	+nvf0_disp_oclass = {
	82	+ .handle = NV_ENGINE(DISP, 0x92),
	83	+ .ofuncs = &(struct nouveau_ofuncs) {
	84	+ .ctor = nvf0_disp_ctor,
	85	+ .dtor = _nouveau_disp_dtor,
	86	+ .init = _nouveau_disp_init,
	87	+ .fini = _nouveau_disp_fini,
	88	+ },
	89	+};
...	...	@@ -50,6 +50,9 @@
50	50	case NVE0_DISP_MAST_CLASS:
51	51	case NVE0_DISP_SYNC_CLASS:
52	52	case NVE0_DISP_OVLY_CLASS:
	53	+ case NVF0_DISP_MAST_CLASS:
	54	+ case NVF0_DISP_SYNC_CLASS:
	55	+ case NVF0_DISP_OVLY_CLASS:
53	56	break;
54	57	default:
55	58	return -EINVAL;
...	...	@@ -169,6 +169,7 @@
169	169	* 8570: NVA3_DISP
170	170	* 9070: NVD0_DISP
171	171	* 9170: NVE0_DISP
	172	+ * 9270: NVF0_DISP
172	173	*/
173	174
174	175	#define NV50_DISP_CLASS 0x00005070
...	...	@@ -178,6 +179,7 @@
178	179	#define NVA3_DISP_CLASS 0x00008570
179	180	#define NVD0_DISP_CLASS 0x00009070
180	181	#define NVE0_DISP_CLASS 0x00009170
	182	+#define NVF0_DISP_CLASS 0x00009270
181	183
182	184	#define NV50_DISP_SOR_MTHD 0x00010000
183	185	#define NV50_DISP_SOR_MTHD_TYPE 0x0000f000
...	...	@@ -246,6 +248,7 @@
246	248	* 857a: NVA3_DISP_CURS
247	249	* 907a: NVD0_DISP_CURS
248	250	* 917a: NVE0_DISP_CURS
	251	+ * 927a: NVF0_DISP_CURS
249	252	*/
250	253
251	254	#define NV50_DISP_CURS_CLASS 0x0000507a
...	...	@@ -255,6 +258,7 @@
255	258	#define NVA3_DISP_CURS_CLASS 0x0000857a
256	259	#define NVD0_DISP_CURS_CLASS 0x0000907a
257	260	#define NVE0_DISP_CURS_CLASS 0x0000917a
	261	+#define NVF0_DISP_CURS_CLASS 0x0000927a
258	262
259	263	struct nv50_display_curs_class {
260	264	u32 head;
...	...	@@ -267,6 +271,7 @@
267	271	* 857b: NVA3_DISP_OIMM
268	272	* 907b: NVD0_DISP_OIMM
269	273	* 917b: NVE0_DISP_OIMM
	274	+ * 927b: NVE0_DISP_OIMM
270	275	*/
271	276
272	277	#define NV50_DISP_OIMM_CLASS 0x0000507b
...	...	@@ -276,6 +281,7 @@
276	281	#define NVA3_DISP_OIMM_CLASS 0x0000857b
277	282	#define NVD0_DISP_OIMM_CLASS 0x0000907b
278	283	#define NVE0_DISP_OIMM_CLASS 0x0000917b
	284	+#define NVF0_DISP_OIMM_CLASS 0x0000927b
279	285
280	286	struct nv50_display_oimm_class {
281	287	u32 head;
...	...	@@ -288,6 +294,7 @@
288	294	* 857c: NVA3_DISP_SYNC
289	295	* 907c: NVD0_DISP_SYNC
290	296	* 917c: NVE0_DISP_SYNC
	297	+ * 927c: NVF0_DISP_SYNC
291	298	*/
292	299
293	300	#define NV50_DISP_SYNC_CLASS 0x0000507c
...	...	@@ -297,6 +304,7 @@
297	304	#define NVA3_DISP_SYNC_CLASS 0x0000857c
298	305	#define NVD0_DISP_SYNC_CLASS 0x0000907c
299	306	#define NVE0_DISP_SYNC_CLASS 0x0000917c
	307	+#define NVF0_DISP_SYNC_CLASS 0x0000927c
300	308
301	309	struct nv50_display_sync_class {
302	310	u32 pushbuf;
...	...	@@ -310,6 +318,7 @@
310	318	* 857d: NVA3_DISP_MAST
311	319	* 907d: NVD0_DISP_MAST
312	320	* 917d: NVE0_DISP_MAST
	321	+ * 927d: NVF0_DISP_MAST
313	322	*/
314	323
315	324	#define NV50_DISP_MAST_CLASS 0x0000507d
...	...	@@ -319,6 +328,7 @@
319	328	#define NVA3_DISP_MAST_CLASS 0x0000857d
320	329	#define NVD0_DISP_MAST_CLASS 0x0000907d
321	330	#define NVE0_DISP_MAST_CLASS 0x0000917d
	331	+#define NVF0_DISP_MAST_CLASS 0x0000927d
322	332
323	333	struct nv50_display_mast_class {
324	334	u32 pushbuf;
...	...	@@ -331,6 +341,7 @@
331	341	* 857e: NVA3_DISP_OVLY
332	342	* 907e: NVD0_DISP_OVLY
333	343	* 917e: NVE0_DISP_OVLY
	344	+ * 927e: NVF0_DISP_OVLY
334	345	*/
335	346
336	347	#define NV50_DISP_OVLY_CLASS 0x0000507e
...	...	@@ -340,6 +351,7 @@
340	351	#define NVA3_DISP_OVLY_CLASS 0x0000857e
341	352	#define NVD0_DISP_OVLY_CLASS 0x0000907e
342	353	#define NVE0_DISP_OVLY_CLASS 0x0000917e
	354	+#define NVF0_DISP_OVLY_CLASS 0x0000927e
343	355
344	356	struct nv50_display_ovly_class {
345	357	u32 pushbuf;
...	...	@@ -44,6 +44,7 @@
44	44	extern struct nouveau_oclass nva3_disp_oclass;
45	45	extern struct nouveau_oclass nvd0_disp_oclass;
46	46	extern struct nouveau_oclass nve0_disp_oclass;
	47	+extern struct nouveau_oclass nvf0_disp_oclass;
47	48
48	49	#endif
...	...	@@ -33,6 +33,7 @@
33	33
34	34	#include <engine/device.h>
35	35	#include <engine/disp.h>
	36	+#include <engine/fifo.h>
36	37
37	38	#include <subdev/vm.h>
38	39
...	...	@@ -164,7 +165,7 @@
164	165	u32 arg0, arg1;
165	166	int ret;
166	167
167		- if (nouveau_noaccel)
	168	+ if (nouveau_noaccel \|\| !nouveau_fifo(device) /XXX/)
168	169	return;
169	170
170	171	/* initialise synchronisation routines */
...	...	@@ -2174,6 +2174,7 @@
2174	2174	nv50_display_create(struct drm_device *dev)
2175	2175	{
2176	2176	static const u16 oclass[] = {
	2177	+ NVF0_DISP_CLASS,
2177	2178	NVE0_DISP_CLASS,
2178	2179	NVD0_DISP_CLASS,
2179	2180	NVA3_DISP_CLASS,