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Commit f4f8e5635f398645d614dff5a07598651faf3ead

Authored by Viresh Kumar
Committed by Linus Walleij
1 parent 50309a9c2e
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

pinctrl: SPEAr: Add gpio ranges support 

Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio.
This patch gpio enable support for SPEAr pinctrl drivers.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 8 changed files with 447 additions and 17 deletions Inline Diff

drivers/pinctrl/spear/Kconfig
Diff comments   View file @ f4f8e56
1 # 1 #
2 # ST Microelectronics SPEAr PINCTRL drivers 2 # ST Microelectronics SPEAr PINCTRL drivers
3 # 3 #
4 4
5 if PLAT_SPEAR 5 if PLAT_SPEAR
6 6
7 config PINCTRL_SPEAR 7 config PINCTRL_SPEAR
8 bool 8 bool
9 depends on OF 9 depends on OF
10 select PINMUX 10 select PINMUX
11 help 11 help
12 This enables pin control drivers for SPEAr Platform 12 This enables pin control drivers for SPEAr Platform
13 13
14 config PINCTRL_SPEAR3XX 14 config PINCTRL_SPEAR3XX
15 bool 15 bool
16 depends on ARCH_SPEAR3XX 16 depends on ARCH_SPEAR3XX
17 select PINCTRL_SPEAR 17 select PINCTRL_SPEAR
18 18
19 config PINCTRL_SPEAR300 19 config PINCTRL_SPEAR300
20 bool "ST Microelectronics SPEAr300 SoC pin controller driver" 20 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
21 depends on MACH_SPEAR300 21 depends on MACH_SPEAR300
22 select PINCTRL_SPEAR3XX 22 select PINCTRL_SPEAR3XX
23 23
24 config PINCTRL_SPEAR310 24 config PINCTRL_SPEAR310
25 bool "ST Microelectronics SPEAr310 SoC pin controller driver" 25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
26 depends on MACH_SPEAR310 26 depends on MACH_SPEAR310
27 select PINCTRL_SPEAR3XX 27 select PINCTRL_SPEAR3XX
28 select PINCTRL_SPEAR_PLGPIO
28 29
29 config PINCTRL_SPEAR320 30 config PINCTRL_SPEAR320
30 bool "ST Microelectronics SPEAr320 SoC pin controller driver" 31 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
31 depends on MACH_SPEAR320 32 depends on MACH_SPEAR320
32 select PINCTRL_SPEAR3XX 33 select PINCTRL_SPEAR3XX
34 select PINCTRL_SPEAR_PLGPIO
33 35
34 config PINCTRL_SPEAR1310 36 config PINCTRL_SPEAR1310
35 bool "ST Microelectronics SPEAr1310 SoC pin controller driver" 37 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
36 depends on MACH_SPEAR1310 38 depends on MACH_SPEAR1310
37 select PINCTRL_SPEAR 39 select PINCTRL_SPEAR
40 select PINCTRL_SPEAR_PLGPIO
38 41
39 config PINCTRL_SPEAR1340 42 config PINCTRL_SPEAR1340
40 bool "ST Microelectronics SPEAr1340 SoC pin controller driver" 43 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
41 depends on MACH_SPEAR1340 44 depends on MACH_SPEAR1340
42 select PINCTRL_SPEAR 45 select PINCTRL_SPEAR
46 select PINCTRL_SPEAR_PLGPIO
43 47
44 config PINCTRL_SPEAR_PLGPIO 48 config PINCTRL_SPEAR_PLGPIO
45 bool "SPEAr SoC PLGPIO Controller" 49 bool "SPEAr SoC PLGPIO Controller"
46 depends on GPIOLIB && PINCTRL_SPEAR 50 depends on GPIOLIB && PINCTRL_SPEAR
47 help 51 help
48 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr 52 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
49 SoCs. 53 SoCs.
50 54
51 endif 55 endif
52 56
drivers/pinctrl/spear/pinctrl-spear.c
Diff comments   View file @ f4f8e56
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr pinmux 2 * Driver for the ST Microelectronics SPEAr pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * Inspired from: 7 * Inspired from:
8 * - U300 Pinctl drivers 8 * - U300 Pinctl drivers
9 * - Tegra Pinctl drivers 9 * - Tegra Pinctl drivers
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any 12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16 #include <linux/err.h> 16 #include <linux/err.h>
17 #include <linux/io.h> 17 #include <linux/io.h>
18 #include <linux/module.h> 18 #include <linux/module.h>
19 #include <linux/of.h> 19 #include <linux/of.h>
20 #include <linux/of_address.h> 20 #include <linux/of_address.h>
21 #include <linux/of_gpio.h>
21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinmux.h>
24 #include <linux/platform_device.h> 25 #include <linux/platform_device.h>
25 #include <linux/slab.h> 26 #include <linux/slab.h>
26 27
27 #include "pinctrl-spear.h" 28 #include "pinctrl-spear.h"
28 29
29 #define DRIVER_NAME "spear-pinmux" 30 #define DRIVER_NAME "spear-pinmux"
30 31
31 static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) 32 static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
32 { 33 {
33 return readl_relaxed(pmx->vbase + reg); 34 return readl_relaxed(pmx->vbase + reg);
34 } 35 }
35 36
36 static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) 37 static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
37 { 38 {
38 writel_relaxed(val, pmx->vbase + reg); 39 writel_relaxed(val, pmx->vbase + reg);
39 } 40 }
40 41
42 static void muxregs_endisable(struct spear_pmx *pmx,
43 struct spear_muxreg *muxregs, u8 count, bool enable)
44 {
45 struct spear_muxreg *muxreg;
46 u32 val, temp, j;
47
48 for (j = 0; j < count; j++) {
49 muxreg = &muxregs[j];
50
51 val = pmx_readl(pmx, muxreg->reg);
52 val &= ~muxreg->mask;
53
54 if (enable)
55 temp = muxreg->val;
56 else
57 temp = ~muxreg->val;
58
59 val |= muxreg->mask & temp;
60 pmx_writel(pmx, val, muxreg->reg);
61 }
62 }
63
41 static int set_mode(struct spear_pmx *pmx, int mode) 64 static int set_mode(struct spear_pmx *pmx, int mode)
42 { 65 {
43 struct spear_pmx_mode *pmx_mode = NULL; 66 struct spear_pmx_mode *pmx_mode = NULL;
44 int i; 67 int i;
45 u32 val; 68 u32 val;
46 69
47 if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes) 70 if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
48 return -EINVAL; 71 return -EINVAL;
49 72
50 for (i = 0; i < pmx->machdata->npmx_modes; i++) { 73 for (i = 0; i < pmx->machdata->npmx_modes; i++) {
51 if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) { 74 if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
52 pmx_mode = pmx->machdata->pmx_modes[i]; 75 pmx_mode = pmx->machdata->pmx_modes[i];
53 break; 76 break;
54 } 77 }
55 } 78 }
56 79
57 if (!pmx_mode) 80 if (!pmx_mode)
58 return -EINVAL; 81 return -EINVAL;
59 82
60 val = pmx_readl(pmx, pmx_mode->reg); 83 val = pmx_readl(pmx, pmx_mode->reg);
61 val &= ~pmx_mode->mask; 84 val &= ~pmx_mode->mask;
62 val |= pmx_mode->val; 85 val |= pmx_mode->val;
63 pmx_writel(pmx, val, pmx_mode->reg); 86 pmx_writel(pmx, val, pmx_mode->reg);
64 87
65 pmx->machdata->mode = pmx_mode->mode; 88 pmx->machdata->mode = pmx_mode->mode;
66 dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n", 89 dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
67 pmx_mode->name ? pmx_mode->name : "no_name", 90 pmx_mode->name ? pmx_mode->name : "no_name",
68 pmx_mode->reg); 91 pmx_mode->reg);
69 92
70 return 0; 93 return 0;
71 } 94 }
72 95
96 void __devinit
97 pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
98 unsigned count, u16 reg)
99 {
100 int i = 0, j = 0;
101
102 for (; i < count; i++)
103 for (; j < gpio_pingroup[i].nmuxregs; j++)
104 gpio_pingroup[i].muxregs[j].reg = reg;
105 }
106
73 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) 107 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
74 { 108 {
75 struct spear_pingroup *pgroup; 109 struct spear_pingroup *pgroup;
76 struct spear_modemux *modemux; 110 struct spear_modemux *modemux;
77 int i, j, group; 111 int i, j, group;
78 112
79 for (group = 0; group < machdata->ngroups; group++) { 113 for (group = 0; group < machdata->ngroups; group++) {
80 pgroup = machdata->groups[group]; 114 pgroup = machdata->groups[group];
81 115
82 for (i = 0; i < pgroup->nmodemuxs; i++) { 116 for (i = 0; i < pgroup->nmodemuxs; i++) {
83 modemux = &pgroup->modemuxs[i]; 117 modemux = &pgroup->modemuxs[i];
84 118
85 for (j = 0; j < modemux->nmuxregs; j++) 119 for (j = 0; j < modemux->nmuxregs; j++)
86 if (modemux->muxregs[j].reg == 0xFFFF) 120 if (modemux->muxregs[j].reg == 0xFFFF)
87 modemux->muxregs[j].reg = reg; 121 modemux->muxregs[j].reg = reg;
88 } 122 }
89 } 123 }
90 } 124 }
91 125
92 static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev) 126 static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
93 { 127 {
94 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 128 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
95 129
96 return pmx->machdata->ngroups; 130 return pmx->machdata->ngroups;
97 } 131 }
98 132
99 static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 133 static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
100 unsigned group) 134 unsigned group)
101 { 135 {
102 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 136 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
103 137
104 return pmx->machdata->groups[group]->name; 138 return pmx->machdata->groups[group]->name;
105 } 139 }
106 140
107 static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 141 static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
108 unsigned group, const unsigned **pins, unsigned *num_pins) 142 unsigned group, const unsigned **pins, unsigned *num_pins)
109 { 143 {
110 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 144 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
111 145
112 *pins = pmx->machdata->groups[group]->pins; 146 *pins = pmx->machdata->groups[group]->pins;
113 *num_pins = pmx->machdata->groups[group]->npins; 147 *num_pins = pmx->machdata->groups[group]->npins;
114 148
115 return 0; 149 return 0;
116 } 150 }
117 151
118 static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 152 static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
119 struct seq_file *s, unsigned offset) 153 struct seq_file *s, unsigned offset)
120 { 154 {
121 seq_printf(s, " " DRIVER_NAME); 155 seq_printf(s, " " DRIVER_NAME);
122 } 156 }
123 157
124 int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 158 int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
125 struct device_node *np_config, 159 struct device_node *np_config,
126 struct pinctrl_map **map, unsigned *num_maps) 160 struct pinctrl_map **map, unsigned *num_maps)
127 { 161 {
128 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 162 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
129 struct device_node *np; 163 struct device_node *np;
130 struct property *prop; 164 struct property *prop;
131 const char *function, *group; 165 const char *function, *group;
132 int ret, index = 0, count = 0; 166 int ret, index = 0, count = 0;
133 167
134 /* calculate number of maps required */ 168 /* calculate number of maps required */
135 for_each_child_of_node(np_config, np) { 169 for_each_child_of_node(np_config, np) {
136 ret = of_property_read_string(np, "st,function", &function); 170 ret = of_property_read_string(np, "st,function", &function);
137 if (ret < 0) 171 if (ret < 0)
138 return ret; 172 return ret;
139 173
140 ret = of_property_count_strings(np, "st,pins"); 174 ret = of_property_count_strings(np, "st,pins");
141 if (ret < 0) 175 if (ret < 0)
142 return ret; 176 return ret;
143 177
144 count += ret; 178 count += ret;
145 } 179 }
146 180
147 if (!count) { 181 if (!count) {
148 dev_err(pmx->dev, "No child nodes passed via DT\n"); 182 dev_err(pmx->dev, "No child nodes passed via DT\n");
149 return -ENODEV; 183 return -ENODEV;
150 } 184 }
151 185
152 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); 186 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
153 if (!*map) 187 if (!*map)
154 return -ENOMEM; 188 return -ENOMEM;
155 189
156 for_each_child_of_node(np_config, np) { 190 for_each_child_of_node(np_config, np) {
157 of_property_read_string(np, "st,function", &function); 191 of_property_read_string(np, "st,function", &function);
158 of_property_for_each_string(np, "st,pins", prop, group) { 192 of_property_for_each_string(np, "st,pins", prop, group) {
159 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; 193 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
160 (*map)[index].data.mux.group = group; 194 (*map)[index].data.mux.group = group;
161 (*map)[index].data.mux.function = function; 195 (*map)[index].data.mux.function = function;
162 index++; 196 index++;
163 } 197 }
164 } 198 }
165 199
166 *num_maps = count; 200 *num_maps = count;
167 201
168 return 0; 202 return 0;
169 } 203 }
170 204
171 void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, 205 void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
172 struct pinctrl_map *map, unsigned num_maps) 206 struct pinctrl_map *map, unsigned num_maps)
173 { 207 {
174 kfree(map); 208 kfree(map);
175 } 209 }
176 210
177 static struct pinctrl_ops spear_pinctrl_ops = { 211 static struct pinctrl_ops spear_pinctrl_ops = {
178 .get_groups_count = spear_pinctrl_get_groups_cnt, 212 .get_groups_count = spear_pinctrl_get_groups_cnt,
179 .get_group_name = spear_pinctrl_get_group_name, 213 .get_group_name = spear_pinctrl_get_group_name,
180 .get_group_pins = spear_pinctrl_get_group_pins, 214 .get_group_pins = spear_pinctrl_get_group_pins,
181 .pin_dbg_show = spear_pinctrl_pin_dbg_show, 215 .pin_dbg_show = spear_pinctrl_pin_dbg_show,
182 .dt_node_to_map = spear_pinctrl_dt_node_to_map, 216 .dt_node_to_map = spear_pinctrl_dt_node_to_map,
183 .dt_free_map = spear_pinctrl_dt_free_map, 217 .dt_free_map = spear_pinctrl_dt_free_map,
184 }; 218 };
185 219
186 static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 220 static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
187 { 221 {
188 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 222 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
189 223
190 return pmx->machdata->nfunctions; 224 return pmx->machdata->nfunctions;
191 } 225 }
192 226
193 static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 227 static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
194 unsigned function) 228 unsigned function)
195 { 229 {
196 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 230 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
197 231
198 return pmx->machdata->functions[function]->name; 232 return pmx->machdata->functions[function]->name;
199 } 233 }
200 234
201 static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 235 static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
202 unsigned function, const char *const **groups, 236 unsigned function, const char *const **groups,
203 unsigned * const ngroups) 237 unsigned * const ngroups)
204 { 238 {
205 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 239 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
206 240
207 *groups = pmx->machdata->functions[function]->groups; 241 *groups = pmx->machdata->functions[function]->groups;
208 *ngroups = pmx->machdata->functions[function]->ngroups; 242 *ngroups = pmx->machdata->functions[function]->ngroups;
209 243
210 return 0; 244 return 0;
211 } 245 }
212 246
213 static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, 247 static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
214 unsigned function, unsigned group, bool enable) 248 unsigned function, unsigned group, bool enable)
215 { 249 {
216 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 250 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
217 const struct spear_pingroup *pgroup; 251 const struct spear_pingroup *pgroup;
218 const struct spear_modemux *modemux; 252 const struct spear_modemux *modemux;
219 struct spear_muxreg *muxreg; 253 int i;
220 u32 val, temp;
221 int i, j;
222 bool found = false; 254 bool found = false;
223 255
224 pgroup = pmx->machdata->groups[group]; 256 pgroup = pmx->machdata->groups[group];
225 257
226 for (i = 0; i < pgroup->nmodemuxs; i++) { 258 for (i = 0; i < pgroup->nmodemuxs; i++) {
227 modemux = &pgroup->modemuxs[i]; 259 modemux = &pgroup->modemuxs[i];
228 260
229 /* SoC have any modes */ 261 /* SoC have any modes */
230 if (pmx->machdata->modes_supported) { 262 if (pmx->machdata->modes_supported) {
231 if (!(pmx->machdata->mode & modemux->modes)) 263 if (!(pmx->machdata->mode & modemux->modes))
232 continue; 264 continue;
233 } 265 }
234 266
235 found = true; 267 found = true;
236 for (j = 0; j < modemux->nmuxregs; j++) { 268 muxregs_endisable(pmx, modemux->muxregs, modemux->nmuxregs,
237 muxreg = &modemux->muxregs[j]; 269 enable);
238
239 val = pmx_readl(pmx, muxreg->reg);
240 val &= ~muxreg->mask;
241
242 if (enable)
243 temp = muxreg->val;
244 else
245 temp = ~muxreg->val;
246
247 val |= muxreg->mask & temp;
248 pmx_writel(pmx, val, muxreg->reg);
249 }
250 } 270 }
251 271
252 if (!found) { 272 if (!found) {
253 dev_err(pmx->dev, "pinmux group: %s not supported\n", 273 dev_err(pmx->dev, "pinmux group: %s not supported\n",
254 pgroup->name); 274 pgroup->name);
255 return -ENODEV; 275 return -ENODEV;
256 } 276 }
257 277
258 return 0; 278 return 0;
259 } 279 }
260 280
261 static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 281 static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
262 unsigned group) 282 unsigned group)
263 { 283 {
264 return spear_pinctrl_endisable(pctldev, function, group, true); 284 return spear_pinctrl_endisable(pctldev, function, group, true);
265 } 285 }
266 286
267 static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, 287 static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
268 unsigned function, unsigned group) 288 unsigned function, unsigned group)
269 { 289 {
270 spear_pinctrl_endisable(pctldev, function, group, false); 290 spear_pinctrl_endisable(pctldev, function, group, false);
271 } 291 }
272 292
293 /* gpio with pinmux */
294 static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
295 unsigned pin)
296 {
297 struct spear_gpio_pingroup *gpio_pingroup;
298 int i = 0, j;
299
300 if (!pmx->machdata->gpio_pingroups)
301 return NULL;
302
303 for (; i < pmx->machdata->ngpio_pingroups; i++) {
304 gpio_pingroup = &pmx->machdata->gpio_pingroups[i];
305
306 for (j = 0; j < gpio_pingroup->npins; j++) {
307 if (gpio_pingroup->pins[j] == pin)
308 return gpio_pingroup;
309 }
310 }
311
312 return ERR_PTR(-EINVAL);
313 }
314
315 static int gpio_request_endisable(struct pinctrl_dev *pctldev,
316 struct pinctrl_gpio_range *range, unsigned offset, bool enable)
317 {
318 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
319 struct spear_gpio_pingroup *gpio_pingroup;
320
321 gpio_pingroup = get_gpio_pingroup(pmx, offset);
322 if (IS_ERR(gpio_pingroup))
323 return PTR_ERR(gpio_pingroup);
324
325 if (gpio_pingroup)
326 muxregs_endisable(pmx, gpio_pingroup->muxregs,
327 gpio_pingroup->nmuxregs, enable);
328
329 return 0;
330 }
331
332 static int gpio_request_enable(struct pinctrl_dev *pctldev,
333 struct pinctrl_gpio_range *range, unsigned offset)
334 {
335 return gpio_request_endisable(pctldev, range, offset, true);
336 }
337
338 static void gpio_disable_free(struct pinctrl_dev *pctldev,
339 struct pinctrl_gpio_range *range, unsigned offset)
340 {
341 gpio_request_endisable(pctldev, range, offset, false);
342 }
343
273 static struct pinmux_ops spear_pinmux_ops = { 344 static struct pinmux_ops spear_pinmux_ops = {
274 .get_functions_count = spear_pinctrl_get_funcs_count, 345 .get_functions_count = spear_pinctrl_get_funcs_count,
275 .get_function_name = spear_pinctrl_get_func_name, 346 .get_function_name = spear_pinctrl_get_func_name,
276 .get_function_groups = spear_pinctrl_get_func_groups, 347 .get_function_groups = spear_pinctrl_get_func_groups,
277 .enable = spear_pinctrl_enable, 348 .enable = spear_pinctrl_enable,
278 .disable = spear_pinctrl_disable, 349 .disable = spear_pinctrl_disable,
350 .gpio_request_enable = gpio_request_enable,
351 .gpio_disable_free = gpio_disable_free,
279 }; 352 };
280 353
281 static struct pinctrl_desc spear_pinctrl_desc = { 354 static struct pinctrl_desc spear_pinctrl_desc = {
282 .name = DRIVER_NAME, 355 .name = DRIVER_NAME,
283 .pctlops = &spear_pinctrl_ops, 356 .pctlops = &spear_pinctrl_ops,
284 .pmxops = &spear_pinmux_ops, 357 .pmxops = &spear_pinmux_ops,
285 .owner = THIS_MODULE, 358 .owner = THIS_MODULE,
286 }; 359 };
287 360
288 int __devinit spear_pinctrl_probe(struct platform_device *pdev, 361 int __devinit spear_pinctrl_probe(struct platform_device *pdev,
289 struct spear_pinctrl_machdata *machdata) 362 struct spear_pinctrl_machdata *machdata)
290 { 363 {
291 struct device_node *np = pdev->dev.of_node; 364 struct device_node *np = pdev->dev.of_node;
292 struct resource *res; 365 struct resource *res;
293 struct spear_pmx *pmx; 366 struct spear_pmx *pmx;
294 367
295 if (!machdata) 368 if (!machdata)
296 return -ENODEV; 369 return -ENODEV;
297 370
298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299 if (!res) 372 if (!res)
300 return -EINVAL; 373 return -EINVAL;
301 374
302 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 375 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
303 if (!pmx) { 376 if (!pmx) {
304 dev_err(&pdev->dev, "Can't alloc spear_pmx\n"); 377 dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
305 return -ENOMEM; 378 return -ENOMEM;
306 } 379 }
307 380
308 pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 381 pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
309 if (!pmx->vbase) { 382 if (!pmx->vbase) {
310 dev_err(&pdev->dev, "Couldn't ioremap at index 0\n"); 383 dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
311 return -ENODEV; 384 return -ENODEV;
312 } 385 }
313 386
314 pmx->dev = &pdev->dev; 387 pmx->dev = &pdev->dev;
315 pmx->machdata = machdata; 388 pmx->machdata = machdata;
316 389
317 /* configure mode, if supported by SoC */ 390 /* configure mode, if supported by SoC */
318 if (machdata->modes_supported) { 391 if (machdata->modes_supported) {
319 int mode = 0; 392 int mode = 0;
320 393
321 if (of_property_read_u32(np, "st,pinmux-mode", &mode)) { 394 if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
322 dev_err(&pdev->dev, "OF: pinmux mode not passed\n"); 395 dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
323 return -EINVAL; 396 return -EINVAL;
324 } 397 }
325 398
326 if (set_mode(pmx, mode)) { 399 if (set_mode(pmx, mode)) {
327 dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n", 400 dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
328 mode); 401 mode);
329 return -EINVAL; 402 return -EINVAL;
330 } 403 }
331 } 404 }
332 405
333 platform_set_drvdata(pdev, pmx); 406 platform_set_drvdata(pdev, pmx);
334 407
335 spear_pinctrl_desc.pins = machdata->pins; 408 spear_pinctrl_desc.pins = machdata->pins;
336 spear_pinctrl_desc.npins = machdata->npins; 409 spear_pinctrl_desc.npins = machdata->npins;
337 410
338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); 411 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
339 if (!pmx->pctl) { 412 if (!pmx->pctl) {
340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 413 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
341 return -ENODEV; 414 return -ENODEV;
drivers/pinctrl/spear/pinctrl-spear.h
Diff comments   View file @ f4f8e56
1 /* 1 /*
2 * Driver header file for the ST Microelectronics SPEAr pinmux 2 * Driver header file for the ST Microelectronics SPEAr pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #ifndef __PINMUX_SPEAR_H__ 12 #ifndef __PINMUX_SPEAR_H__
13 #define __PINMUX_SPEAR_H__ 13 #define __PINMUX_SPEAR_H__
14 14
15 #include <linux/gpio.h>
15 #include <linux/pinctrl/pinctrl.h> 16 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/types.h> 17 #include <linux/types.h>
17 18
18 struct platform_device; 19 struct platform_device;
19 struct device; 20 struct device;
20 21
21 /** 22 /**
22 * struct spear_pmx_mode - SPEAr pmx mode 23 * struct spear_pmx_mode - SPEAr pmx mode
23 * @name: name of pmx mode 24 * @name: name of pmx mode
24 * @mode: mode id 25 * @mode: mode id
25 * @reg: register for configuring this mode 26 * @reg: register for configuring this mode
26 * @mask: mask of this mode in reg 27 * @mask: mask of this mode in reg
27 * @val: val to be configured at reg after doing (val & mask) 28 * @val: val to be configured at reg after doing (val & mask)
28 */ 29 */
29 struct spear_pmx_mode { 30 struct spear_pmx_mode {
30 const char *const name; 31 const char *const name;
31 u16 mode; 32 u16 mode;
32 u16 reg; 33 u16 reg;
33 u16 mask; 34 u16 mask;
34 u32 val; 35 u32 val;
35 }; 36 };
36 37
37 /** 38 /**
38 * struct spear_muxreg - SPEAr mux reg configuration 39 * struct spear_muxreg - SPEAr mux reg configuration
39 * @reg: register offset 40 * @reg: register offset
40 * @mask: mask bits 41 * @mask: mask bits
41 * @val: val to be written on mask bits 42 * @val: val to be written on mask bits
42 */ 43 */
43 struct spear_muxreg { 44 struct spear_muxreg {
44 u16 reg; 45 u16 reg;
45 u32 mask; 46 u32 mask;
46 u32 val; 47 u32 val;
47 }; 48 };
48 49
50 struct spear_gpio_pingroup {
51 const unsigned *pins;
52 unsigned npins;
53 struct spear_muxreg *muxregs;
54 u8 nmuxregs;
55 };
56
57 /* ste: set to enable */
58 #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \
59 static struct spear_muxreg __pins##_muxregs[] = { \
60 { \
61 .reg = __muxreg, \
62 .mask = __mask, \
63 .val = __ste ? __mask : 0, \
64 }, \
65 }
66
67 #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
68 static struct spear_muxreg __pins##_muxregs[] = { \
69 { \
70 .reg = __muxreg1, \
71 .mask = __mask, \
72 .val = __ste1 ? __mask : 0, \
73 }, { \
74 .reg = __muxreg2, \
75 .mask = __mask, \
76 .val = __ste2 ? __mask : 0, \
77 }, \
78 }
79
80 #define GPIO_PINGROUP(__pins) \
81 { \
82 .pins = __pins, \
83 .npins = ARRAY_SIZE(__pins), \
84 .muxregs = __pins##_muxregs, \
85 .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \
86 }
87
49 /** 88 /**
50 * struct spear_modemux - SPEAr mode mux configuration 89 * struct spear_modemux - SPEAr mode mux configuration
51 * @modes: mode ids supported by this group of muxregs 90 * @modes: mode ids supported by this group of muxregs
52 * @nmuxregs: number of muxreg configurations to be done for modes 91 * @nmuxregs: number of muxreg configurations to be done for modes
53 * @muxregs: array of muxreg configurations to be done for modes 92 * @muxregs: array of muxreg configurations to be done for modes
54 */ 93 */
55 struct spear_modemux { 94 struct spear_modemux {
56 u16 modes; 95 u16 modes;
57 u8 nmuxregs; 96 u8 nmuxregs;
58 struct spear_muxreg *muxregs; 97 struct spear_muxreg *muxregs;
59 }; 98 };
60 99
61 /** 100 /**
62 * struct spear_pingroup - SPEAr pin group configurations 101 * struct spear_pingroup - SPEAr pin group configurations
63 * @name: name of pin group 102 * @name: name of pin group
64 * @pins: array containing pin numbers 103 * @pins: array containing pin numbers
65 * @npins: size of pins array 104 * @npins: size of pins array
66 * @modemuxs: array of modemux configurations for this pin group 105 * @modemuxs: array of modemux configurations for this pin group
67 * @nmodemuxs: size of array modemuxs 106 * @nmodemuxs: size of array modemuxs
68 * 107 *
69 * A representation of a group of pins in the SPEAr pin controller. Each group 108 * A representation of a group of pins in the SPEAr pin controller. Each group
70 * allows some parameter or parameters to be configured. 109 * allows some parameter or parameters to be configured.
71 */ 110 */
72 struct spear_pingroup { 111 struct spear_pingroup {
73 const char *name; 112 const char *name;
74 const unsigned *pins; 113 const unsigned *pins;
75 unsigned npins; 114 unsigned npins;
76 struct spear_modemux *modemuxs; 115 struct spear_modemux *modemuxs;
77 unsigned nmodemuxs; 116 unsigned nmodemuxs;
78 }; 117 };
79 118
80 /** 119 /**
81 * struct spear_function - SPEAr pinctrl mux function 120 * struct spear_function - SPEAr pinctrl mux function
82 * @name: The name of the function, exported to pinctrl core. 121 * @name: The name of the function, exported to pinctrl core.
83 * @groups: An array of pin groups that may select this function. 122 * @groups: An array of pin groups that may select this function.
84 * @ngroups: The number of entries in @groups. 123 * @ngroups: The number of entries in @groups.
85 */ 124 */
86 struct spear_function { 125 struct spear_function {
87 const char *name; 126 const char *name;
88 const char *const *groups; 127 const char *const *groups;
89 unsigned ngroups; 128 unsigned ngroups;
90 }; 129 };
91 130
92 /** 131 /**
93 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver 132 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
94 * configuration 133 * configuration
95 * @pins: An array describing all pins the pin controller affects. 134 * @pins: An array describing all pins the pin controller affects.
96 * All pins which are also GPIOs must be listed first within the *array, 135 * All pins which are also GPIOs must be listed first within the *array,
97 * and be numbered identically to the GPIO controller's *numbering. 136 * and be numbered identically to the GPIO controller's *numbering.
98 * @npins: The numbmer of entries in @pins. 137 * @npins: The numbmer of entries in @pins.
99 * @functions: An array describing all mux functions the SoC supports. 138 * @functions: An array describing all mux functions the SoC supports.
100 * @nfunctions: The numbmer of entries in @functions. 139 * @nfunctions: The numbmer of entries in @functions.
101 * @groups: An array describing all pin groups the pin SoC supports. 140 * @groups: An array describing all pin groups the pin SoC supports.
102 * @ngroups: The numbmer of entries in @groups. 141 * @ngroups: The numbmer of entries in @groups.
142 * @gpio_pingroups: gpio pingroups
143 * @ngpio_pingroups: gpio pingroups count
103 * 144 *
104 * @modes_supported: Does SoC support modes 145 * @modes_supported: Does SoC support modes
105 * @mode: mode configured from probe 146 * @mode: mode configured from probe
106 * @pmx_modes: array of modes supported by SoC 147 * @pmx_modes: array of modes supported by SoC
107 * @npmx_modes: number of entries in pmx_modes. 148 * @npmx_modes: number of entries in pmx_modes.
108 */ 149 */
109 struct spear_pinctrl_machdata { 150 struct spear_pinctrl_machdata {
110 const struct pinctrl_pin_desc *pins; 151 const struct pinctrl_pin_desc *pins;
111 unsigned npins; 152 unsigned npins;
112 struct spear_function **functions; 153 struct spear_function **functions;
113 unsigned nfunctions; 154 unsigned nfunctions;
114 struct spear_pingroup **groups; 155 struct spear_pingroup **groups;
115 unsigned ngroups; 156 unsigned ngroups;
157 struct spear_gpio_pingroup *gpio_pingroups;
158 unsigned ngpio_pingroups;
116 159
117 bool modes_supported; 160 bool modes_supported;
118 u16 mode; 161 u16 mode;
119 struct spear_pmx_mode **pmx_modes; 162 struct spear_pmx_mode **pmx_modes;
120 unsigned npmx_modes; 163 unsigned npmx_modes;
121 }; 164 };
122 165
123 /** 166 /**
124 * struct spear_pmx - SPEAr pinctrl mux 167 * struct spear_pmx - SPEAr pinctrl mux
125 * @dev: pointer to struct dev of platform_device registered 168 * @dev: pointer to struct dev of platform_device registered
126 * @pctl: pointer to struct pinctrl_dev 169 * @pctl: pointer to struct pinctrl_dev
127 * @machdata: pointer to SoC or machine specific structure 170 * @machdata: pointer to SoC or machine specific structure
128 * @vbase: virtual base address of pinmux controller 171 * @vbase: virtual base address of pinmux controller
129 */ 172 */
130 struct spear_pmx { 173 struct spear_pmx {
131 struct device *dev; 174 struct device *dev;
132 struct pinctrl_dev *pctl; 175 struct pinctrl_dev *pctl;
133 struct spear_pinctrl_machdata *machdata; 176 struct spear_pinctrl_machdata *machdata;
134 void __iomem *vbase; 177 void __iomem *vbase;
135 }; 178 };
136 179
137 /* exported routines */ 180 /* exported routines */
138 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); 181 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
182 void __devinit
183 pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
184 unsigned count, u16 reg);
139 int __devinit spear_pinctrl_probe(struct platform_device *pdev, 185 int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 struct spear_pinctrl_machdata *machdata); 186 struct spear_pinctrl_machdata *machdata);
141 int __devexit spear_pinctrl_remove(struct platform_device *pdev); 187 int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142 188
143 #define SPEAR_PIN_0_TO_101 \ 189 #define SPEAR_PIN_0_TO_101 \
144 PINCTRL_PIN(0, "PLGPIO0"), \ 190 PINCTRL_PIN(0, "PLGPIO0"), \
145 PINCTRL_PIN(1, "PLGPIO1"), \ 191 PINCTRL_PIN(1, "PLGPIO1"), \
146 PINCTRL_PIN(2, "PLGPIO2"), \ 192 PINCTRL_PIN(2, "PLGPIO2"), \
147 PINCTRL_PIN(3, "PLGPIO3"), \ 193 PINCTRL_PIN(3, "PLGPIO3"), \
148 PINCTRL_PIN(4, "PLGPIO4"), \ 194 PINCTRL_PIN(4, "PLGPIO4"), \
149 PINCTRL_PIN(5, "PLGPIO5"), \ 195 PINCTRL_PIN(5, "PLGPIO5"), \
150 PINCTRL_PIN(6, "PLGPIO6"), \ 196 PINCTRL_PIN(6, "PLGPIO6"), \
151 PINCTRL_PIN(7, "PLGPIO7"), \ 197 PINCTRL_PIN(7, "PLGPIO7"), \
152 PINCTRL_PIN(8, "PLGPIO8"), \ 198 PINCTRL_PIN(8, "PLGPIO8"), \
153 PINCTRL_PIN(9, "PLGPIO9"), \ 199 PINCTRL_PIN(9, "PLGPIO9"), \
154 PINCTRL_PIN(10, "PLGPIO10"), \ 200 PINCTRL_PIN(10, "PLGPIO10"), \
155 PINCTRL_PIN(11, "PLGPIO11"), \ 201 PINCTRL_PIN(11, "PLGPIO11"), \
156 PINCTRL_PIN(12, "PLGPIO12"), \ 202 PINCTRL_PIN(12, "PLGPIO12"), \
157 PINCTRL_PIN(13, "PLGPIO13"), \ 203 PINCTRL_PIN(13, "PLGPIO13"), \
158 PINCTRL_PIN(14, "PLGPIO14"), \ 204 PINCTRL_PIN(14, "PLGPIO14"), \
159 PINCTRL_PIN(15, "PLGPIO15"), \ 205 PINCTRL_PIN(15, "PLGPIO15"), \
160 PINCTRL_PIN(16, "PLGPIO16"), \ 206 PINCTRL_PIN(16, "PLGPIO16"), \
161 PINCTRL_PIN(17, "PLGPIO17"), \ 207 PINCTRL_PIN(17, "PLGPIO17"), \
162 PINCTRL_PIN(18, "PLGPIO18"), \ 208 PINCTRL_PIN(18, "PLGPIO18"), \
163 PINCTRL_PIN(19, "PLGPIO19"), \ 209 PINCTRL_PIN(19, "PLGPIO19"), \
164 PINCTRL_PIN(20, "PLGPIO20"), \ 210 PINCTRL_PIN(20, "PLGPIO20"), \
165 PINCTRL_PIN(21, "PLGPIO21"), \ 211 PINCTRL_PIN(21, "PLGPIO21"), \
166 PINCTRL_PIN(22, "PLGPIO22"), \ 212 PINCTRL_PIN(22, "PLGPIO22"), \
167 PINCTRL_PIN(23, "PLGPIO23"), \ 213 PINCTRL_PIN(23, "PLGPIO23"), \
168 PINCTRL_PIN(24, "PLGPIO24"), \ 214 PINCTRL_PIN(24, "PLGPIO24"), \
169 PINCTRL_PIN(25, "PLGPIO25"), \ 215 PINCTRL_PIN(25, "PLGPIO25"), \
170 PINCTRL_PIN(26, "PLGPIO26"), \ 216 PINCTRL_PIN(26, "PLGPIO26"), \
171 PINCTRL_PIN(27, "PLGPIO27"), \ 217 PINCTRL_PIN(27, "PLGPIO27"), \
172 PINCTRL_PIN(28, "PLGPIO28"), \ 218 PINCTRL_PIN(28, "PLGPIO28"), \
173 PINCTRL_PIN(29, "PLGPIO29"), \ 219 PINCTRL_PIN(29, "PLGPIO29"), \
174 PINCTRL_PIN(30, "PLGPIO30"), \ 220 PINCTRL_PIN(30, "PLGPIO30"), \
175 PINCTRL_PIN(31, "PLGPIO31"), \ 221 PINCTRL_PIN(31, "PLGPIO31"), \
176 PINCTRL_PIN(32, "PLGPIO32"), \ 222 PINCTRL_PIN(32, "PLGPIO32"), \
177 PINCTRL_PIN(33, "PLGPIO33"), \ 223 PINCTRL_PIN(33, "PLGPIO33"), \
178 PINCTRL_PIN(34, "PLGPIO34"), \ 224 PINCTRL_PIN(34, "PLGPIO34"), \
179 PINCTRL_PIN(35, "PLGPIO35"), \ 225 PINCTRL_PIN(35, "PLGPIO35"), \
180 PINCTRL_PIN(36, "PLGPIO36"), \ 226 PINCTRL_PIN(36, "PLGPIO36"), \
181 PINCTRL_PIN(37, "PLGPIO37"), \ 227 PINCTRL_PIN(37, "PLGPIO37"), \
182 PINCTRL_PIN(38, "PLGPIO38"), \ 228 PINCTRL_PIN(38, "PLGPIO38"), \
183 PINCTRL_PIN(39, "PLGPIO39"), \ 229 PINCTRL_PIN(39, "PLGPIO39"), \
184 PINCTRL_PIN(40, "PLGPIO40"), \ 230 PINCTRL_PIN(40, "PLGPIO40"), \
185 PINCTRL_PIN(41, "PLGPIO41"), \ 231 PINCTRL_PIN(41, "PLGPIO41"), \
186 PINCTRL_PIN(42, "PLGPIO42"), \ 232 PINCTRL_PIN(42, "PLGPIO42"), \
187 PINCTRL_PIN(43, "PLGPIO43"), \ 233 PINCTRL_PIN(43, "PLGPIO43"), \
188 PINCTRL_PIN(44, "PLGPIO44"), \ 234 PINCTRL_PIN(44, "PLGPIO44"), \
189 PINCTRL_PIN(45, "PLGPIO45"), \ 235 PINCTRL_PIN(45, "PLGPIO45"), \
190 PINCTRL_PIN(46, "PLGPIO46"), \ 236 PINCTRL_PIN(46, "PLGPIO46"), \
191 PINCTRL_PIN(47, "PLGPIO47"), \ 237 PINCTRL_PIN(47, "PLGPIO47"), \
192 PINCTRL_PIN(48, "PLGPIO48"), \ 238 PINCTRL_PIN(48, "PLGPIO48"), \
193 PINCTRL_PIN(49, "PLGPIO49"), \ 239 PINCTRL_PIN(49, "PLGPIO49"), \
194 PINCTRL_PIN(50, "PLGPIO50"), \ 240 PINCTRL_PIN(50, "PLGPIO50"), \
195 PINCTRL_PIN(51, "PLGPIO51"), \ 241 PINCTRL_PIN(51, "PLGPIO51"), \
196 PINCTRL_PIN(52, "PLGPIO52"), \ 242 PINCTRL_PIN(52, "PLGPIO52"), \
197 PINCTRL_PIN(53, "PLGPIO53"), \ 243 PINCTRL_PIN(53, "PLGPIO53"), \
198 PINCTRL_PIN(54, "PLGPIO54"), \ 244 PINCTRL_PIN(54, "PLGPIO54"), \
199 PINCTRL_PIN(55, "PLGPIO55"), \ 245 PINCTRL_PIN(55, "PLGPIO55"), \
200 PINCTRL_PIN(56, "PLGPIO56"), \ 246 PINCTRL_PIN(56, "PLGPIO56"), \
201 PINCTRL_PIN(57, "PLGPIO57"), \ 247 PINCTRL_PIN(57, "PLGPIO57"), \
202 PINCTRL_PIN(58, "PLGPIO58"), \ 248 PINCTRL_PIN(58, "PLGPIO58"), \
203 PINCTRL_PIN(59, "PLGPIO59"), \ 249 PINCTRL_PIN(59, "PLGPIO59"), \
204 PINCTRL_PIN(60, "PLGPIO60"), \ 250 PINCTRL_PIN(60, "PLGPIO60"), \
205 PINCTRL_PIN(61, "PLGPIO61"), \ 251 PINCTRL_PIN(61, "PLGPIO61"), \
206 PINCTRL_PIN(62, "PLGPIO62"), \ 252 PINCTRL_PIN(62, "PLGPIO62"), \
207 PINCTRL_PIN(63, "PLGPIO63"), \ 253 PINCTRL_PIN(63, "PLGPIO63"), \
208 PINCTRL_PIN(64, "PLGPIO64"), \ 254 PINCTRL_PIN(64, "PLGPIO64"), \
209 PINCTRL_PIN(65, "PLGPIO65"), \ 255 PINCTRL_PIN(65, "PLGPIO65"), \
210 PINCTRL_PIN(66, "PLGPIO66"), \ 256 PINCTRL_PIN(66, "PLGPIO66"), \
211 PINCTRL_PIN(67, "PLGPIO67"), \ 257 PINCTRL_PIN(67, "PLGPIO67"), \
212 PINCTRL_PIN(68, "PLGPIO68"), \ 258 PINCTRL_PIN(68, "PLGPIO68"), \
213 PINCTRL_PIN(69, "PLGPIO69"), \ 259 PINCTRL_PIN(69, "PLGPIO69"), \
214 PINCTRL_PIN(70, "PLGPIO70"), \ 260 PINCTRL_PIN(70, "PLGPIO70"), \
215 PINCTRL_PIN(71, "PLGPIO71"), \ 261 PINCTRL_PIN(71, "PLGPIO71"), \
216 PINCTRL_PIN(72, "PLGPIO72"), \ 262 PINCTRL_PIN(72, "PLGPIO72"), \
217 PINCTRL_PIN(73, "PLGPIO73"), \ 263 PINCTRL_PIN(73, "PLGPIO73"), \
218 PINCTRL_PIN(74, "PLGPIO74"), \ 264 PINCTRL_PIN(74, "PLGPIO74"), \
219 PINCTRL_PIN(75, "PLGPIO75"), \ 265 PINCTRL_PIN(75, "PLGPIO75"), \
220 PINCTRL_PIN(76, "PLGPIO76"), \ 266 PINCTRL_PIN(76, "PLGPIO76"), \
221 PINCTRL_PIN(77, "PLGPIO77"), \ 267 PINCTRL_PIN(77, "PLGPIO77"), \
222 PINCTRL_PIN(78, "PLGPIO78"), \ 268 PINCTRL_PIN(78, "PLGPIO78"), \
223 PINCTRL_PIN(79, "PLGPIO79"), \ 269 PINCTRL_PIN(79, "PLGPIO79"), \
224 PINCTRL_PIN(80, "PLGPIO80"), \ 270 PINCTRL_PIN(80, "PLGPIO80"), \
225 PINCTRL_PIN(81, "PLGPIO81"), \ 271 PINCTRL_PIN(81, "PLGPIO81"), \
226 PINCTRL_PIN(82, "PLGPIO82"), \ 272 PINCTRL_PIN(82, "PLGPIO82"), \
227 PINCTRL_PIN(83, "PLGPIO83"), \ 273 PINCTRL_PIN(83, "PLGPIO83"), \
228 PINCTRL_PIN(84, "PLGPIO84"), \ 274 PINCTRL_PIN(84, "PLGPIO84"), \
229 PINCTRL_PIN(85, "PLGPIO85"), \ 275 PINCTRL_PIN(85, "PLGPIO85"), \
230 PINCTRL_PIN(86, "PLGPIO86"), \ 276 PINCTRL_PIN(86, "PLGPIO86"), \
231 PINCTRL_PIN(87, "PLGPIO87"), \ 277 PINCTRL_PIN(87, "PLGPIO87"), \
232 PINCTRL_PIN(88, "PLGPIO88"), \ 278 PINCTRL_PIN(88, "PLGPIO88"), \
233 PINCTRL_PIN(89, "PLGPIO89"), \ 279 PINCTRL_PIN(89, "PLGPIO89"), \
234 PINCTRL_PIN(90, "PLGPIO90"), \ 280 PINCTRL_PIN(90, "PLGPIO90"), \
235 PINCTRL_PIN(91, "PLGPIO91"), \ 281 PINCTRL_PIN(91, "PLGPIO91"), \
236 PINCTRL_PIN(92, "PLGPIO92"), \ 282 PINCTRL_PIN(92, "PLGPIO92"), \
237 PINCTRL_PIN(93, "PLGPIO93"), \ 283 PINCTRL_PIN(93, "PLGPIO93"), \
238 PINCTRL_PIN(94, "PLGPIO94"), \ 284 PINCTRL_PIN(94, "PLGPIO94"), \
239 PINCTRL_PIN(95, "PLGPIO95"), \ 285 PINCTRL_PIN(95, "PLGPIO95"), \
240 PINCTRL_PIN(96, "PLGPIO96"), \ 286 PINCTRL_PIN(96, "PLGPIO96"), \
241 PINCTRL_PIN(97, "PLGPIO97"), \ 287 PINCTRL_PIN(97, "PLGPIO97"), \
242 PINCTRL_PIN(98, "PLGPIO98"), \ 288 PINCTRL_PIN(98, "PLGPIO98"), \
243 PINCTRL_PIN(99, "PLGPIO99"), \ 289 PINCTRL_PIN(99, "PLGPIO99"), \
244 PINCTRL_PIN(100, "PLGPIO100"), \ 290 PINCTRL_PIN(100, "PLGPIO100"), \
245 PINCTRL_PIN(101, "PLGPIO101") 291 PINCTRL_PIN(101, "PLGPIO101")
246 292
247 #define SPEAR_PIN_102_TO_245 \ 293 #define SPEAR_PIN_102_TO_245 \
248 PINCTRL_PIN(102, "PLGPIO102"), \ 294 PINCTRL_PIN(102, "PLGPIO102"), \
249 PINCTRL_PIN(103, "PLGPIO103"), \ 295 PINCTRL_PIN(103, "PLGPIO103"), \
250 PINCTRL_PIN(104, "PLGPIO104"), \ 296 PINCTRL_PIN(104, "PLGPIO104"), \
251 PINCTRL_PIN(105, "PLGPIO105"), \ 297 PINCTRL_PIN(105, "PLGPIO105"), \
252 PINCTRL_PIN(106, "PLGPIO106"), \ 298 PINCTRL_PIN(106, "PLGPIO106"), \
253 PINCTRL_PIN(107, "PLGPIO107"), \ 299 PINCTRL_PIN(107, "PLGPIO107"), \
254 PINCTRL_PIN(108, "PLGPIO108"), \ 300 PINCTRL_PIN(108, "PLGPIO108"), \
255 PINCTRL_PIN(109, "PLGPIO109"), \ 301 PINCTRL_PIN(109, "PLGPIO109"), \
256 PINCTRL_PIN(110, "PLGPIO110"), \ 302 PINCTRL_PIN(110, "PLGPIO110"), \
257 PINCTRL_PIN(111, "PLGPIO111"), \ 303 PINCTRL_PIN(111, "PLGPIO111"), \
258 PINCTRL_PIN(112, "PLGPIO112"), \ 304 PINCTRL_PIN(112, "PLGPIO112"), \
259 PINCTRL_PIN(113, "PLGPIO113"), \ 305 PINCTRL_PIN(113, "PLGPIO113"), \
260 PINCTRL_PIN(114, "PLGPIO114"), \ 306 PINCTRL_PIN(114, "PLGPIO114"), \
261 PINCTRL_PIN(115, "PLGPIO115"), \ 307 PINCTRL_PIN(115, "PLGPIO115"), \
262 PINCTRL_PIN(116, "PLGPIO116"), \ 308 PINCTRL_PIN(116, "PLGPIO116"), \
263 PINCTRL_PIN(117, "PLGPIO117"), \ 309 PINCTRL_PIN(117, "PLGPIO117"), \
264 PINCTRL_PIN(118, "PLGPIO118"), \ 310 PINCTRL_PIN(118, "PLGPIO118"), \
265 PINCTRL_PIN(119, "PLGPIO119"), \ 311 PINCTRL_PIN(119, "PLGPIO119"), \
266 PINCTRL_PIN(120, "PLGPIO120"), \ 312 PINCTRL_PIN(120, "PLGPIO120"), \
267 PINCTRL_PIN(121, "PLGPIO121"), \ 313 PINCTRL_PIN(121, "PLGPIO121"), \
268 PINCTRL_PIN(122, "PLGPIO122"), \ 314 PINCTRL_PIN(122, "PLGPIO122"), \
269 PINCTRL_PIN(123, "PLGPIO123"), \ 315 PINCTRL_PIN(123, "PLGPIO123"), \
270 PINCTRL_PIN(124, "PLGPIO124"), \ 316 PINCTRL_PIN(124, "PLGPIO124"), \
271 PINCTRL_PIN(125, "PLGPIO125"), \ 317 PINCTRL_PIN(125, "PLGPIO125"), \
272 PINCTRL_PIN(126, "PLGPIO126"), \ 318 PINCTRL_PIN(126, "PLGPIO126"), \
273 PINCTRL_PIN(127, "PLGPIO127"), \ 319 PINCTRL_PIN(127, "PLGPIO127"), \
274 PINCTRL_PIN(128, "PLGPIO128"), \ 320 PINCTRL_PIN(128, "PLGPIO128"), \
275 PINCTRL_PIN(129, "PLGPIO129"), \ 321 PINCTRL_PIN(129, "PLGPIO129"), \
276 PINCTRL_PIN(130, "PLGPIO130"), \ 322 PINCTRL_PIN(130, "PLGPIO130"), \
277 PINCTRL_PIN(131, "PLGPIO131"), \ 323 PINCTRL_PIN(131, "PLGPIO131"), \
278 PINCTRL_PIN(132, "PLGPIO132"), \ 324 PINCTRL_PIN(132, "PLGPIO132"), \
279 PINCTRL_PIN(133, "PLGPIO133"), \ 325 PINCTRL_PIN(133, "PLGPIO133"), \
280 PINCTRL_PIN(134, "PLGPIO134"), \ 326 PINCTRL_PIN(134, "PLGPIO134"), \
281 PINCTRL_PIN(135, "PLGPIO135"), \ 327 PINCTRL_PIN(135, "PLGPIO135"), \
282 PINCTRL_PIN(136, "PLGPIO136"), \ 328 PINCTRL_PIN(136, "PLGPIO136"), \
283 PINCTRL_PIN(137, "PLGPIO137"), \ 329 PINCTRL_PIN(137, "PLGPIO137"), \
284 PINCTRL_PIN(138, "PLGPIO138"), \ 330 PINCTRL_PIN(138, "PLGPIO138"), \
285 PINCTRL_PIN(139, "PLGPIO139"), \ 331 PINCTRL_PIN(139, "PLGPIO139"), \
286 PINCTRL_PIN(140, "PLGPIO140"), \ 332 PINCTRL_PIN(140, "PLGPIO140"), \
287 PINCTRL_PIN(141, "PLGPIO141"), \ 333 PINCTRL_PIN(141, "PLGPIO141"), \
288 PINCTRL_PIN(142, "PLGPIO142"), \ 334 PINCTRL_PIN(142, "PLGPIO142"), \
289 PINCTRL_PIN(143, "PLGPIO143"), \ 335 PINCTRL_PIN(143, "PLGPIO143"), \
290 PINCTRL_PIN(144, "PLGPIO144"), \ 336 PINCTRL_PIN(144, "PLGPIO144"), \
291 PINCTRL_PIN(145, "PLGPIO145"), \ 337 PINCTRL_PIN(145, "PLGPIO145"), \
292 PINCTRL_PIN(146, "PLGPIO146"), \ 338 PINCTRL_PIN(146, "PLGPIO146"), \
293 PINCTRL_PIN(147, "PLGPIO147"), \ 339 PINCTRL_PIN(147, "PLGPIO147"), \
294 PINCTRL_PIN(148, "PLGPIO148"), \ 340 PINCTRL_PIN(148, "PLGPIO148"), \
295 PINCTRL_PIN(149, "PLGPIO149"), \ 341 PINCTRL_PIN(149, "PLGPIO149"), \
296 PINCTRL_PIN(150, "PLGPIO150"), \ 342 PINCTRL_PIN(150, "PLGPIO150"), \
297 PINCTRL_PIN(151, "PLGPIO151"), \ 343 PINCTRL_PIN(151, "PLGPIO151"), \
298 PINCTRL_PIN(152, "PLGPIO152"), \ 344 PINCTRL_PIN(152, "PLGPIO152"), \
299 PINCTRL_PIN(153, "PLGPIO153"), \ 345 PINCTRL_PIN(153, "PLGPIO153"), \
300 PINCTRL_PIN(154, "PLGPIO154"), \ 346 PINCTRL_PIN(154, "PLGPIO154"), \
301 PINCTRL_PIN(155, "PLGPIO155"), \ 347 PINCTRL_PIN(155, "PLGPIO155"), \
302 PINCTRL_PIN(156, "PLGPIO156"), \ 348 PINCTRL_PIN(156, "PLGPIO156"), \
303 PINCTRL_PIN(157, "PLGPIO157"), \ 349 PINCTRL_PIN(157, "PLGPIO157"), \
304 PINCTRL_PIN(158, "PLGPIO158"), \ 350 PINCTRL_PIN(158, "PLGPIO158"), \
305 PINCTRL_PIN(159, "PLGPIO159"), \ 351 PINCTRL_PIN(159, "PLGPIO159"), \
306 PINCTRL_PIN(160, "PLGPIO160"), \ 352 PINCTRL_PIN(160, "PLGPIO160"), \
307 PINCTRL_PIN(161, "PLGPIO161"), \ 353 PINCTRL_PIN(161, "PLGPIO161"), \
308 PINCTRL_PIN(162, "PLGPIO162"), \ 354 PINCTRL_PIN(162, "PLGPIO162"), \
309 PINCTRL_PIN(163, "PLGPIO163"), \ 355 PINCTRL_PIN(163, "PLGPIO163"), \
310 PINCTRL_PIN(164, "PLGPIO164"), \ 356 PINCTRL_PIN(164, "PLGPIO164"), \
311 PINCTRL_PIN(165, "PLGPIO165"), \ 357 PINCTRL_PIN(165, "PLGPIO165"), \
312 PINCTRL_PIN(166, "PLGPIO166"), \ 358 PINCTRL_PIN(166, "PLGPIO166"), \
313 PINCTRL_PIN(167, "PLGPIO167"), \ 359 PINCTRL_PIN(167, "PLGPIO167"), \
314 PINCTRL_PIN(168, "PLGPIO168"), \ 360 PINCTRL_PIN(168, "PLGPIO168"), \
315 PINCTRL_PIN(169, "PLGPIO169"), \ 361 PINCTRL_PIN(169, "PLGPIO169"), \
316 PINCTRL_PIN(170, "PLGPIO170"), \ 362 PINCTRL_PIN(170, "PLGPIO170"), \
317 PINCTRL_PIN(171, "PLGPIO171"), \ 363 PINCTRL_PIN(171, "PLGPIO171"), \
318 PINCTRL_PIN(172, "PLGPIO172"), \ 364 PINCTRL_PIN(172, "PLGPIO172"), \
319 PINCTRL_PIN(173, "PLGPIO173"), \ 365 PINCTRL_PIN(173, "PLGPIO173"), \
320 PINCTRL_PIN(174, "PLGPIO174"), \ 366 PINCTRL_PIN(174, "PLGPIO174"), \
321 PINCTRL_PIN(175, "PLGPIO175"), \ 367 PINCTRL_PIN(175, "PLGPIO175"), \
322 PINCTRL_PIN(176, "PLGPIO176"), \ 368 PINCTRL_PIN(176, "PLGPIO176"), \
323 PINCTRL_PIN(177, "PLGPIO177"), \ 369 PINCTRL_PIN(177, "PLGPIO177"), \
324 PINCTRL_PIN(178, "PLGPIO178"), \ 370 PINCTRL_PIN(178, "PLGPIO178"), \
325 PINCTRL_PIN(179, "PLGPIO179"), \ 371 PINCTRL_PIN(179, "PLGPIO179"), \
326 PINCTRL_PIN(180, "PLGPIO180"), \ 372 PINCTRL_PIN(180, "PLGPIO180"), \
327 PINCTRL_PIN(181, "PLGPIO181"), \ 373 PINCTRL_PIN(181, "PLGPIO181"), \
328 PINCTRL_PIN(182, "PLGPIO182"), \ 374 PINCTRL_PIN(182, "PLGPIO182"), \
329 PINCTRL_PIN(183, "PLGPIO183"), \ 375 PINCTRL_PIN(183, "PLGPIO183"), \
330 PINCTRL_PIN(184, "PLGPIO184"), \ 376 PINCTRL_PIN(184, "PLGPIO184"), \
331 PINCTRL_PIN(185, "PLGPIO185"), \ 377 PINCTRL_PIN(185, "PLGPIO185"), \
332 PINCTRL_PIN(186, "PLGPIO186"), \ 378 PINCTRL_PIN(186, "PLGPIO186"), \
333 PINCTRL_PIN(187, "PLGPIO187"), \ 379 PINCTRL_PIN(187, "PLGPIO187"), \
334 PINCTRL_PIN(188, "PLGPIO188"), \ 380 PINCTRL_PIN(188, "PLGPIO188"), \
335 PINCTRL_PIN(189, "PLGPIO189"), \ 381 PINCTRL_PIN(189, "PLGPIO189"), \
336 PINCTRL_PIN(190, "PLGPIO190"), \ 382 PINCTRL_PIN(190, "PLGPIO190"), \
337 PINCTRL_PIN(191, "PLGPIO191"), \ 383 PINCTRL_PIN(191, "PLGPIO191"), \
338 PINCTRL_PIN(192, "PLGPIO192"), \ 384 PINCTRL_PIN(192, "PLGPIO192"), \
339 PINCTRL_PIN(193, "PLGPIO193"), \ 385 PINCTRL_PIN(193, "PLGPIO193"), \
340 PINCTRL_PIN(194, "PLGPIO194"), \ 386 PINCTRL_PIN(194, "PLGPIO194"), \
341 PINCTRL_PIN(195, "PLGPIO195"), \ 387 PINCTRL_PIN(195, "PLGPIO195"), \
342 PINCTRL_PIN(196, "PLGPIO196"), \ 388 PINCTRL_PIN(196, "PLGPIO196"), \
343 PINCTRL_PIN(197, "PLGPIO197"), \ 389 PINCTRL_PIN(197, "PLGPIO197"), \
344 PINCTRL_PIN(198, "PLGPIO198"), \ 390 PINCTRL_PIN(198, "PLGPIO198"), \
345 PINCTRL_PIN(199, "PLGPIO199"), \ 391 PINCTRL_PIN(199, "PLGPIO199"), \
346 PINCTRL_PIN(200, "PLGPIO200"), \ 392 PINCTRL_PIN(200, "PLGPIO200"), \
347 PINCTRL_PIN(201, "PLGPIO201"), \ 393 PINCTRL_PIN(201, "PLGPIO201"), \
348 PINCTRL_PIN(202, "PLGPIO202"), \ 394 PINCTRL_PIN(202, "PLGPIO202"), \
349 PINCTRL_PIN(203, "PLGPIO203"), \ 395 PINCTRL_PIN(203, "PLGPIO203"), \
350 PINCTRL_PIN(204, "PLGPIO204"), \ 396 PINCTRL_PIN(204, "PLGPIO204"), \
351 PINCTRL_PIN(205, "PLGPIO205"), \ 397 PINCTRL_PIN(205, "PLGPIO205"), \
352 PINCTRL_PIN(206, "PLGPIO206"), \ 398 PINCTRL_PIN(206, "PLGPIO206"), \
353 PINCTRL_PIN(207, "PLGPIO207"), \ 399 PINCTRL_PIN(207, "PLGPIO207"), \
354 PINCTRL_PIN(208, "PLGPIO208"), \ 400 PINCTRL_PIN(208, "PLGPIO208"), \
355 PINCTRL_PIN(209, "PLGPIO209"), \ 401 PINCTRL_PIN(209, "PLGPIO209"), \
356 PINCTRL_PIN(210, "PLGPIO210"), \ 402 PINCTRL_PIN(210, "PLGPIO210"), \
357 PINCTRL_PIN(211, "PLGPIO211"), \ 403 PINCTRL_PIN(211, "PLGPIO211"), \
358 PINCTRL_PIN(212, "PLGPIO212"), \ 404 PINCTRL_PIN(212, "PLGPIO212"), \
359 PINCTRL_PIN(213, "PLGPIO213"), \ 405 PINCTRL_PIN(213, "PLGPIO213"), \
360 PINCTRL_PIN(214, "PLGPIO214"), \ 406 PINCTRL_PIN(214, "PLGPIO214"), \
361 PINCTRL_PIN(215, "PLGPIO215"), \ 407 PINCTRL_PIN(215, "PLGPIO215"), \
362 PINCTRL_PIN(216, "PLGPIO216"), \ 408 PINCTRL_PIN(216, "PLGPIO216"), \
363 PINCTRL_PIN(217, "PLGPIO217"), \ 409 PINCTRL_PIN(217, "PLGPIO217"), \
364 PINCTRL_PIN(218, "PLGPIO218"), \ 410 PINCTRL_PIN(218, "PLGPIO218"), \
365 PINCTRL_PIN(219, "PLGPIO219"), \ 411 PINCTRL_PIN(219, "PLGPIO219"), \
366 PINCTRL_PIN(220, "PLGPIO220"), \ 412 PINCTRL_PIN(220, "PLGPIO220"), \
367 PINCTRL_PIN(221, "PLGPIO221"), \ 413 PINCTRL_PIN(221, "PLGPIO221"), \
368 PINCTRL_PIN(222, "PLGPIO222"), \ 414 PINCTRL_PIN(222, "PLGPIO222"), \
369 PINCTRL_PIN(223, "PLGPIO223"), \ 415 PINCTRL_PIN(223, "PLGPIO223"), \
370 PINCTRL_PIN(224, "PLGPIO224"), \ 416 PINCTRL_PIN(224, "PLGPIO224"), \
371 PINCTRL_PIN(225, "PLGPIO225"), \ 417 PINCTRL_PIN(225, "PLGPIO225"), \
372 PINCTRL_PIN(226, "PLGPIO226"), \ 418 PINCTRL_PIN(226, "PLGPIO226"), \
373 PINCTRL_PIN(227, "PLGPIO227"), \ 419 PINCTRL_PIN(227, "PLGPIO227"), \
374 PINCTRL_PIN(228, "PLGPIO228"), \ 420 PINCTRL_PIN(228, "PLGPIO228"), \
375 PINCTRL_PIN(229, "PLGPIO229"), \ 421 PINCTRL_PIN(229, "PLGPIO229"), \
376 PINCTRL_PIN(230, "PLGPIO230"), \ 422 PINCTRL_PIN(230, "PLGPIO230"), \
377 PINCTRL_PIN(231, "PLGPIO231"), \ 423 PINCTRL_PIN(231, "PLGPIO231"), \
378 PINCTRL_PIN(232, "PLGPIO232"), \ 424 PINCTRL_PIN(232, "PLGPIO232"), \
379 PINCTRL_PIN(233, "PLGPIO233"), \ 425 PINCTRL_PIN(233, "PLGPIO233"), \
380 PINCTRL_PIN(234, "PLGPIO234"), \ 426 PINCTRL_PIN(234, "PLGPIO234"), \
381 PINCTRL_PIN(235, "PLGPIO235"), \ 427 PINCTRL_PIN(235, "PLGPIO235"), \
382 PINCTRL_PIN(236, "PLGPIO236"), \ 428 PINCTRL_PIN(236, "PLGPIO236"), \
383 PINCTRL_PIN(237, "PLGPIO237"), \ 429 PINCTRL_PIN(237, "PLGPIO237"), \
384 PINCTRL_PIN(238, "PLGPIO238"), \ 430 PINCTRL_PIN(238, "PLGPIO238"), \
385 PINCTRL_PIN(239, "PLGPIO239"), \ 431 PINCTRL_PIN(239, "PLGPIO239"), \
386 PINCTRL_PIN(240, "PLGPIO240"), \ 432 PINCTRL_PIN(240, "PLGPIO240"), \
387 PINCTRL_PIN(241, "PLGPIO241"), \ 433 PINCTRL_PIN(241, "PLGPIO241"), \
388 PINCTRL_PIN(242, "PLGPIO242"), \ 434 PINCTRL_PIN(242, "PLGPIO242"), \
389 PINCTRL_PIN(243, "PLGPIO243"), \ 435 PINCTRL_PIN(243, "PLGPIO243"), \
390 PINCTRL_PIN(244, "PLGPIO244"), \ 436 PINCTRL_PIN(244, "PLGPIO244"), \
391 PINCTRL_PIN(245, "PLGPIO245") 437 PINCTRL_PIN(245, "PLGPIO245")
392 438
393 #endif /* __PINMUX_SPEAR_H__ */ 439 #endif /* __PINMUX_SPEAR_H__ */
394 440
drivers/pinctrl/spear/pinctrl-spear1310.c
Diff comments   View file @ f4f8e56
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr1310 pinmux 2 * Driver for the ST Microelectronics SPEAr1310 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear.h" 17 #include "pinctrl-spear.h"
18 18
19 #define DRIVER_NAME "spear1310-pinmux" 19 #define DRIVER_NAME "spear1310-pinmux"
20 20
21 /* pins */ 21 /* pins */
22 static const struct pinctrl_pin_desc spear1310_pins[] = { 22 static const struct pinctrl_pin_desc spear1310_pins[] = {
23 SPEAR_PIN_0_TO_101, 23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245, 24 SPEAR_PIN_102_TO_245,
25 }; 25 };
26 26
27 /* registers */ 27 /* registers */
28 #define PERIP_CFG 0x3B0 28 #define PERIP_CFG 0x3B0
29 #define MCIF_SEL_SHIFT 5 29 #define MCIF_SEL_SHIFT 5
30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT) 30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT) 31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT) 32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT) 33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
34 34
35 #define PCIE_SATA_CFG 0x3A4 35 #define PCIE_SATA_CFG 0x3A4
36 #define PCIE_SATA2_SEL_PCIE (0 << 31) 36 #define PCIE_SATA2_SEL_PCIE (0 << 31)
37 #define PCIE_SATA1_SEL_PCIE (0 << 30) 37 #define PCIE_SATA1_SEL_PCIE (0 << 30)
38 #define PCIE_SATA0_SEL_PCIE (0 << 29) 38 #define PCIE_SATA0_SEL_PCIE (0 << 29)
39 #define PCIE_SATA2_SEL_SATA (1 << 31) 39 #define PCIE_SATA2_SEL_SATA (1 << 31)
40 #define PCIE_SATA1_SEL_SATA (1 << 30) 40 #define PCIE_SATA1_SEL_SATA (1 << 30)
41 #define PCIE_SATA0_SEL_SATA (1 << 29) 41 #define PCIE_SATA0_SEL_SATA (1 << 29)
42 #define SATA2_CFG_TX_CLK_EN (1 << 27) 42 #define SATA2_CFG_TX_CLK_EN (1 << 27)
43 #define SATA2_CFG_RX_CLK_EN (1 << 26) 43 #define SATA2_CFG_RX_CLK_EN (1 << 26)
44 #define SATA2_CFG_POWERUP_RESET (1 << 25) 44 #define SATA2_CFG_POWERUP_RESET (1 << 25)
45 #define SATA2_CFG_PM_CLK_EN (1 << 24) 45 #define SATA2_CFG_PM_CLK_EN (1 << 24)
46 #define SATA1_CFG_TX_CLK_EN (1 << 23) 46 #define SATA1_CFG_TX_CLK_EN (1 << 23)
47 #define SATA1_CFG_RX_CLK_EN (1 << 22) 47 #define SATA1_CFG_RX_CLK_EN (1 << 22)
48 #define SATA1_CFG_POWERUP_RESET (1 << 21) 48 #define SATA1_CFG_POWERUP_RESET (1 << 21)
49 #define SATA1_CFG_PM_CLK_EN (1 << 20) 49 #define SATA1_CFG_PM_CLK_EN (1 << 20)
50 #define SATA0_CFG_TX_CLK_EN (1 << 19) 50 #define SATA0_CFG_TX_CLK_EN (1 << 19)
51 #define SATA0_CFG_RX_CLK_EN (1 << 18) 51 #define SATA0_CFG_RX_CLK_EN (1 << 18)
52 #define SATA0_CFG_POWERUP_RESET (1 << 17) 52 #define SATA0_CFG_POWERUP_RESET (1 << 17)
53 #define SATA0_CFG_PM_CLK_EN (1 << 16) 53 #define SATA0_CFG_PM_CLK_EN (1 << 16)
54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11) 54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
55 #define PCIE2_CFG_POWERUP_RESET (1 << 10) 55 #define PCIE2_CFG_POWERUP_RESET (1 << 10)
56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9) 56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8) 57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7) 58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
59 #define PCIE1_CFG_POWERUP_RESET (1 << 6) 59 #define PCIE1_CFG_POWERUP_RESET (1 << 6)
60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5) 60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4) 61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3) 62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
63 #define PCIE0_CFG_POWERUP_RESET (1 << 2) 63 #define PCIE0_CFG_POWERUP_RESET (1 << 2)
64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1) 64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0) 65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
66 66
67 #define PAD_FUNCTION_EN_0 0x650 67 #define PAD_FUNCTION_EN_0 0x650
68 #define PMX_UART0_MASK (1 << 1) 68 #define PMX_UART0_MASK (1 << 1)
69 #define PMX_I2C0_MASK (1 << 2) 69 #define PMX_I2C0_MASK (1 << 2)
70 #define PMX_I2S0_MASK (1 << 3) 70 #define PMX_I2S0_MASK (1 << 3)
71 #define PMX_SSP0_MASK (1 << 4) 71 #define PMX_SSP0_MASK (1 << 4)
72 #define PMX_CLCD1_MASK (1 << 5) 72 #define PMX_CLCD1_MASK (1 << 5)
73 #define PMX_EGPIO00_MASK (1 << 6) 73 #define PMX_EGPIO00_MASK (1 << 6)
74 #define PMX_EGPIO01_MASK (1 << 7) 74 #define PMX_EGPIO01_MASK (1 << 7)
75 #define PMX_EGPIO02_MASK (1 << 8) 75 #define PMX_EGPIO02_MASK (1 << 8)
76 #define PMX_EGPIO03_MASK (1 << 9) 76 #define PMX_EGPIO03_MASK (1 << 9)
77 #define PMX_EGPIO04_MASK (1 << 10) 77 #define PMX_EGPIO04_MASK (1 << 10)
78 #define PMX_EGPIO05_MASK (1 << 11) 78 #define PMX_EGPIO05_MASK (1 << 11)
79 #define PMX_EGPIO06_MASK (1 << 12) 79 #define PMX_EGPIO06_MASK (1 << 12)
80 #define PMX_EGPIO07_MASK (1 << 13) 80 #define PMX_EGPIO07_MASK (1 << 13)
81 #define PMX_EGPIO08_MASK (1 << 14) 81 #define PMX_EGPIO08_MASK (1 << 14)
82 #define PMX_EGPIO09_MASK (1 << 15) 82 #define PMX_EGPIO09_MASK (1 << 15)
83 #define PMX_SMI_MASK (1 << 16) 83 #define PMX_SMI_MASK (1 << 16)
84 #define PMX_NAND8_MASK (1 << 17) 84 #define PMX_NAND8_MASK (1 << 17)
85 #define PMX_GMIICLK_MASK (1 << 18) 85 #define PMX_GMIICLK_MASK (1 << 18)
86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19) 86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20) 87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
88 #define PMX_GMIID47_MASK (1 << 21) 88 #define PMX_GMIID47_MASK (1 << 21)
89 #define PMX_MDC_MDIO_MASK (1 << 22) 89 #define PMX_MDC_MDIO_MASK (1 << 22)
90 #define PMX_MCI_DATA8_15_MASK (1 << 23) 90 #define PMX_MCI_DATA8_15_MASK (1 << 23)
91 #define PMX_NFAD23_MASK (1 << 24) 91 #define PMX_NFAD23_MASK (1 << 24)
92 #define PMX_NFAD24_MASK (1 << 25) 92 #define PMX_NFAD24_MASK (1 << 25)
93 #define PMX_NFAD25_MASK (1 << 26) 93 #define PMX_NFAD25_MASK (1 << 26)
94 #define PMX_NFCE3_MASK (1 << 27) 94 #define PMX_NFCE3_MASK (1 << 27)
95 #define PMX_NFWPRT3_MASK (1 << 28) 95 #define PMX_NFWPRT3_MASK (1 << 28)
96 #define PMX_NFRSTPWDWN0_MASK (1 << 29) 96 #define PMX_NFRSTPWDWN0_MASK (1 << 29)
97 #define PMX_NFRSTPWDWN1_MASK (1 << 30) 97 #define PMX_NFRSTPWDWN1_MASK (1 << 30)
98 #define PMX_NFRSTPWDWN2_MASK (1 << 31) 98 #define PMX_NFRSTPWDWN2_MASK (1 << 31)
99 99
100 #define PAD_FUNCTION_EN_1 0x654 100 #define PAD_FUNCTION_EN_1 0x654
101 #define PMX_NFRSTPWDWN3_MASK (1 << 0) 101 #define PMX_NFRSTPWDWN3_MASK (1 << 0)
102 #define PMX_SMINCS2_MASK (1 << 1) 102 #define PMX_SMINCS2_MASK (1 << 1)
103 #define PMX_SMINCS3_MASK (1 << 2) 103 #define PMX_SMINCS3_MASK (1 << 2)
104 #define PMX_CLCD2_MASK (1 << 3) 104 #define PMX_CLCD2_MASK (1 << 3)
105 #define PMX_KBD_ROWCOL68_MASK (1 << 4) 105 #define PMX_KBD_ROWCOL68_MASK (1 << 4)
106 #define PMX_EGPIO10_MASK (1 << 5) 106 #define PMX_EGPIO10_MASK (1 << 5)
107 #define PMX_EGPIO11_MASK (1 << 6) 107 #define PMX_EGPIO11_MASK (1 << 6)
108 #define PMX_EGPIO12_MASK (1 << 7) 108 #define PMX_EGPIO12_MASK (1 << 7)
109 #define PMX_EGPIO13_MASK (1 << 8) 109 #define PMX_EGPIO13_MASK (1 << 8)
110 #define PMX_EGPIO14_MASK (1 << 9) 110 #define PMX_EGPIO14_MASK (1 << 9)
111 #define PMX_EGPIO15_MASK (1 << 10) 111 #define PMX_EGPIO15_MASK (1 << 10)
112 #define PMX_UART0_MODEM_MASK (1 << 11) 112 #define PMX_UART0_MODEM_MASK (1 << 11)
113 #define PMX_GPT0_TMR0_MASK (1 << 12) 113 #define PMX_GPT0_TMR0_MASK (1 << 12)
114 #define PMX_GPT0_TMR1_MASK (1 << 13) 114 #define PMX_GPT0_TMR1_MASK (1 << 13)
115 #define PMX_GPT1_TMR0_MASK (1 << 14) 115 #define PMX_GPT1_TMR0_MASK (1 << 14)
116 #define PMX_GPT1_TMR1_MASK (1 << 15) 116 #define PMX_GPT1_TMR1_MASK (1 << 15)
117 #define PMX_I2S1_MASK (1 << 16) 117 #define PMX_I2S1_MASK (1 << 16)
118 #define PMX_KBD_ROWCOL25_MASK (1 << 17) 118 #define PMX_KBD_ROWCOL25_MASK (1 << 17)
119 #define PMX_NFIO8_15_MASK (1 << 18) 119 #define PMX_NFIO8_15_MASK (1 << 18)
120 #define PMX_KBD_COL1_MASK (1 << 19) 120 #define PMX_KBD_COL1_MASK (1 << 19)
121 #define PMX_NFCE1_MASK (1 << 20) 121 #define PMX_NFCE1_MASK (1 << 20)
122 #define PMX_KBD_COL0_MASK (1 << 21) 122 #define PMX_KBD_COL0_MASK (1 << 21)
123 #define PMX_NFCE2_MASK (1 << 22) 123 #define PMX_NFCE2_MASK (1 << 22)
124 #define PMX_KBD_ROW1_MASK (1 << 23) 124 #define PMX_KBD_ROW1_MASK (1 << 23)
125 #define PMX_NFWPRT1_MASK (1 << 24) 125 #define PMX_NFWPRT1_MASK (1 << 24)
126 #define PMX_KBD_ROW0_MASK (1 << 25) 126 #define PMX_KBD_ROW0_MASK (1 << 25)
127 #define PMX_NFWPRT2_MASK (1 << 26) 127 #define PMX_NFWPRT2_MASK (1 << 26)
128 #define PMX_MCIDATA0_MASK (1 << 27) 128 #define PMX_MCIDATA0_MASK (1 << 27)
129 #define PMX_MCIDATA1_MASK (1 << 28) 129 #define PMX_MCIDATA1_MASK (1 << 28)
130 #define PMX_MCIDATA2_MASK (1 << 29) 130 #define PMX_MCIDATA2_MASK (1 << 29)
131 #define PMX_MCIDATA3_MASK (1 << 30) 131 #define PMX_MCIDATA3_MASK (1 << 30)
132 #define PMX_MCIDATA4_MASK (1 << 31) 132 #define PMX_MCIDATA4_MASK (1 << 31)
133 133
134 #define PAD_FUNCTION_EN_2 0x658 134 #define PAD_FUNCTION_EN_2 0x658
135 #define PMX_MCIDATA5_MASK (1 << 0) 135 #define PMX_MCIDATA5_MASK (1 << 0)
136 #define PMX_MCIDATA6_MASK (1 << 1) 136 #define PMX_MCIDATA6_MASK (1 << 1)
137 #define PMX_MCIDATA7_MASK (1 << 2) 137 #define PMX_MCIDATA7_MASK (1 << 2)
138 #define PMX_MCIDATA1SD_MASK (1 << 3) 138 #define PMX_MCIDATA1SD_MASK (1 << 3)
139 #define PMX_MCIDATA2SD_MASK (1 << 4) 139 #define PMX_MCIDATA2SD_MASK (1 << 4)
140 #define PMX_MCIDATA3SD_MASK (1 << 5) 140 #define PMX_MCIDATA3SD_MASK (1 << 5)
141 #define PMX_MCIADDR0ALE_MASK (1 << 6) 141 #define PMX_MCIADDR0ALE_MASK (1 << 6)
142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7) 142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
143 #define PMX_MCIADDR2_MASK (1 << 8) 143 #define PMX_MCIADDR2_MASK (1 << 8)
144 #define PMX_MCICECF_MASK (1 << 9) 144 #define PMX_MCICECF_MASK (1 << 9)
145 #define PMX_MCICEXD_MASK (1 << 10) 145 #define PMX_MCICEXD_MASK (1 << 10)
146 #define PMX_MCICESDMMC_MASK (1 << 11) 146 #define PMX_MCICESDMMC_MASK (1 << 11)
147 #define PMX_MCICDCF1_MASK (1 << 12) 147 #define PMX_MCICDCF1_MASK (1 << 12)
148 #define PMX_MCICDCF2_MASK (1 << 13) 148 #define PMX_MCICDCF2_MASK (1 << 13)
149 #define PMX_MCICDXD_MASK (1 << 14) 149 #define PMX_MCICDXD_MASK (1 << 14)
150 #define PMX_MCICDSDMMC_MASK (1 << 15) 150 #define PMX_MCICDSDMMC_MASK (1 << 15)
151 #define PMX_MCIDATADIR_MASK (1 << 16) 151 #define PMX_MCIDATADIR_MASK (1 << 16)
152 #define PMX_MCIDMARQWP_MASK (1 << 17) 152 #define PMX_MCIDMARQWP_MASK (1 << 17)
153 #define PMX_MCIIORDRE_MASK (1 << 18) 153 #define PMX_MCIIORDRE_MASK (1 << 18)
154 #define PMX_MCIIOWRWE_MASK (1 << 19) 154 #define PMX_MCIIOWRWE_MASK (1 << 19)
155 #define PMX_MCIRESETCF_MASK (1 << 20) 155 #define PMX_MCIRESETCF_MASK (1 << 20)
156 #define PMX_MCICS0CE_MASK (1 << 21) 156 #define PMX_MCICS0CE_MASK (1 << 21)
157 #define PMX_MCICFINTR_MASK (1 << 22) 157 #define PMX_MCICFINTR_MASK (1 << 22)
158 #define PMX_MCIIORDY_MASK (1 << 23) 158 #define PMX_MCIIORDY_MASK (1 << 23)
159 #define PMX_MCICS1_MASK (1 << 24) 159 #define PMX_MCICS1_MASK (1 << 24)
160 #define PMX_MCIDMAACK_MASK (1 << 25) 160 #define PMX_MCIDMAACK_MASK (1 << 25)
161 #define PMX_MCISDCMD_MASK (1 << 26) 161 #define PMX_MCISDCMD_MASK (1 << 26)
162 #define PMX_MCILEDS_MASK (1 << 27) 162 #define PMX_MCILEDS_MASK (1 << 27)
163 #define PMX_TOUCH_XY_MASK (1 << 28) 163 #define PMX_TOUCH_XY_MASK (1 << 28)
164 #define PMX_SSP0_CS0_MASK (1 << 29) 164 #define PMX_SSP0_CS0_MASK (1 << 29)
165 #define PMX_SSP0_CS1_2_MASK (1 << 30) 165 #define PMX_SSP0_CS1_2_MASK (1 << 30)
166 166
167 #define PAD_DIRECTION_SEL_0 0x65C 167 #define PAD_DIRECTION_SEL_0 0x65C
168 #define PAD_DIRECTION_SEL_1 0x660 168 #define PAD_DIRECTION_SEL_1 0x660
169 #define PAD_DIRECTION_SEL_2 0x664 169 #define PAD_DIRECTION_SEL_2 0x664
170 170
171 /* combined macros */ 171 /* combined macros */
172 #define PMX_GMII_MASK (PMX_GMIICLK_MASK | \ 172 #define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
173 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ 173 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
174 PMX_RXCLK_RDV_TXEN_D03_MASK | \ 174 PMX_RXCLK_RDV_TXEN_D03_MASK | \
175 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK) 175 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
176 176
177 #define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \ 177 #define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
178 PMX_EGPIO02_MASK | \ 178 PMX_EGPIO02_MASK | \
179 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \ 179 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
180 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \ 180 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
181 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \ 181 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
182 PMX_EGPIO09_MASK) 182 PMX_EGPIO09_MASK)
183 #define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \ 183 #define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
184 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \ 184 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
185 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK) 185 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
186 186
187 #define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ 187 #define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
188 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \ 188 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
189 PMX_KBD_COL1_MASK) 189 PMX_KBD_COL1_MASK)
190 190
191 #define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \ 191 #define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
192 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \ 192 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
193 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \ 193 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
194 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \ 194 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
195 PMX_NFCE3_MASK) 195 PMX_NFCE3_MASK)
196 #define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK 196 #define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
197 197
198 #define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK) 198 #define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
199 #define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \ 199 #define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
200 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \ 200 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
201 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ 201 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
202 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK) 202 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
203 203
204 #define PMX_MCIFALL_1_MASK 0xF8000000 204 #define PMX_MCIFALL_1_MASK 0xF8000000
205 #define PMX_MCIFALL_2_MASK 0x0FFFFFFF 205 #define PMX_MCIFALL_2_MASK 0x0FFFFFFF
206 206
207 #define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \ 207 #define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
208 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \ 208 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
209 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \ 209 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
210 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \ 210 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
211 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \ 211 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
212 PMX_NFCE2_MASK) 212 PMX_NFCE2_MASK)
213 #define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ 213 #define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
214 PMX_SSP0_CS1_2_MASK) 214 PMX_SSP0_CS1_2_MASK)
215 215
216 #define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK) 216 #define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
217 #define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \ 217 #define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
218 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ 218 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
219 PMX_GMIID47_MASK) 219 PMX_GMIID47_MASK)
220 #define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\ 220 #define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
221 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \ 221 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
222 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK) 222 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
223 #define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ 223 #define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
224 PMX_SSP0_CS1_2_MASK) 224 PMX_SSP0_CS1_2_MASK)
225 225
226 #define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \ 226 #define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
227 PCIE##x##_CFG_AUX_CLK_EN | \ 227 PCIE##x##_CFG_AUX_CLK_EN | \
228 PCIE##x##_CFG_CORE_CLK_EN | \ 228 PCIE##x##_CFG_CORE_CLK_EN | \
229 PCIE##x##_CFG_POWERUP_RESET | \ 229 PCIE##x##_CFG_POWERUP_RESET | \
230 PCIE##x##_CFG_DEVICE_PRESENT) 230 PCIE##x##_CFG_DEVICE_PRESENT)
231 #define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \ 231 #define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
232 SATA##x##_CFG_PM_CLK_EN | \ 232 SATA##x##_CFG_PM_CLK_EN | \
233 SATA##x##_CFG_POWERUP_RESET | \ 233 SATA##x##_CFG_POWERUP_RESET | \
234 SATA##x##_CFG_RX_CLK_EN | \ 234 SATA##x##_CFG_RX_CLK_EN | \
235 SATA##x##_CFG_TX_CLK_EN) 235 SATA##x##_CFG_TX_CLK_EN)
236 236
237 /* Pad multiplexing for i2c0 device */ 237 /* Pad multiplexing for i2c0 device */
238 static const unsigned i2c0_pins[] = { 102, 103 }; 238 static const unsigned i2c0_pins[] = { 102, 103 };
239 static struct spear_muxreg i2c0_muxreg[] = { 239 static struct spear_muxreg i2c0_muxreg[] = {
240 { 240 {
241 .reg = PAD_FUNCTION_EN_0, 241 .reg = PAD_FUNCTION_EN_0,
242 .mask = PMX_I2C0_MASK, 242 .mask = PMX_I2C0_MASK,
243 .val = PMX_I2C0_MASK, 243 .val = PMX_I2C0_MASK,
244 }, { 244 }, {
245 .reg = PAD_DIRECTION_SEL_0, 245 .reg = PAD_DIRECTION_SEL_0,
246 .mask = PMX_I2C0_MASK, 246 .mask = PMX_I2C0_MASK,
247 .val = PMX_I2C0_MASK, 247 .val = PMX_I2C0_MASK,
248 }, 248 },
249 }; 249 };
250 250
251 static struct spear_modemux i2c0_modemux[] = { 251 static struct spear_modemux i2c0_modemux[] = {
252 { 252 {
253 .muxregs = i2c0_muxreg, 253 .muxregs = i2c0_muxreg,
254 .nmuxregs = ARRAY_SIZE(i2c0_muxreg), 254 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
255 }, 255 },
256 }; 256 };
257 257
258 static struct spear_pingroup i2c0_pingroup = { 258 static struct spear_pingroup i2c0_pingroup = {
259 .name = "i2c0_grp", 259 .name = "i2c0_grp",
260 .pins = i2c0_pins, 260 .pins = i2c0_pins,
261 .npins = ARRAY_SIZE(i2c0_pins), 261 .npins = ARRAY_SIZE(i2c0_pins),
262 .modemuxs = i2c0_modemux, 262 .modemuxs = i2c0_modemux,
263 .nmodemuxs = ARRAY_SIZE(i2c0_modemux), 263 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
264 }; 264 };
265 265
266 static const char *const i2c0_grps[] = { "i2c0_grp" }; 266 static const char *const i2c0_grps[] = { "i2c0_grp" };
267 static struct spear_function i2c0_function = { 267 static struct spear_function i2c0_function = {
268 .name = "i2c0", 268 .name = "i2c0",
269 .groups = i2c0_grps, 269 .groups = i2c0_grps,
270 .ngroups = ARRAY_SIZE(i2c0_grps), 270 .ngroups = ARRAY_SIZE(i2c0_grps),
271 }; 271 };
272 272
273 /* Pad multiplexing for ssp0 device */ 273 /* Pad multiplexing for ssp0 device */
274 static const unsigned ssp0_pins[] = { 109, 110, 111, 112 }; 274 static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
275 static struct spear_muxreg ssp0_muxreg[] = { 275 static struct spear_muxreg ssp0_muxreg[] = {
276 { 276 {
277 .reg = PAD_FUNCTION_EN_0, 277 .reg = PAD_FUNCTION_EN_0,
278 .mask = PMX_SSP0_MASK, 278 .mask = PMX_SSP0_MASK,
279 .val = PMX_SSP0_MASK, 279 .val = PMX_SSP0_MASK,
280 }, { 280 }, {
281 .reg = PAD_DIRECTION_SEL_0, 281 .reg = PAD_DIRECTION_SEL_0,
282 .mask = PMX_SSP0_MASK, 282 .mask = PMX_SSP0_MASK,
283 .val = PMX_SSP0_MASK, 283 .val = PMX_SSP0_MASK,
284 }, 284 },
285 }; 285 };
286 286
287 static struct spear_modemux ssp0_modemux[] = { 287 static struct spear_modemux ssp0_modemux[] = {
288 { 288 {
289 .muxregs = ssp0_muxreg, 289 .muxregs = ssp0_muxreg,
290 .nmuxregs = ARRAY_SIZE(ssp0_muxreg), 290 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
291 }, 291 },
292 }; 292 };
293 293
294 static struct spear_pingroup ssp0_pingroup = { 294 static struct spear_pingroup ssp0_pingroup = {
295 .name = "ssp0_grp", 295 .name = "ssp0_grp",
296 .pins = ssp0_pins, 296 .pins = ssp0_pins,
297 .npins = ARRAY_SIZE(ssp0_pins), 297 .npins = ARRAY_SIZE(ssp0_pins),
298 .modemuxs = ssp0_modemux, 298 .modemuxs = ssp0_modemux,
299 .nmodemuxs = ARRAY_SIZE(ssp0_modemux), 299 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
300 }; 300 };
301 301
302 /* Pad multiplexing for ssp0_cs0 device */ 302 /* Pad multiplexing for ssp0_cs0 device */
303 static const unsigned ssp0_cs0_pins[] = { 96 }; 303 static const unsigned ssp0_cs0_pins[] = { 96 };
304 static struct spear_muxreg ssp0_cs0_muxreg[] = { 304 static struct spear_muxreg ssp0_cs0_muxreg[] = {
305 { 305 {
306 .reg = PAD_FUNCTION_EN_2, 306 .reg = PAD_FUNCTION_EN_2,
307 .mask = PMX_SSP0_CS0_MASK, 307 .mask = PMX_SSP0_CS0_MASK,
308 .val = PMX_SSP0_CS0_MASK, 308 .val = PMX_SSP0_CS0_MASK,
309 }, { 309 }, {
310 .reg = PAD_DIRECTION_SEL_2, 310 .reg = PAD_DIRECTION_SEL_2,
311 .mask = PMX_SSP0_CS0_MASK, 311 .mask = PMX_SSP0_CS0_MASK,
312 .val = PMX_SSP0_CS0_MASK, 312 .val = PMX_SSP0_CS0_MASK,
313 }, 313 },
314 }; 314 };
315 315
316 static struct spear_modemux ssp0_cs0_modemux[] = { 316 static struct spear_modemux ssp0_cs0_modemux[] = {
317 { 317 {
318 .muxregs = ssp0_cs0_muxreg, 318 .muxregs = ssp0_cs0_muxreg,
319 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg), 319 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
320 }, 320 },
321 }; 321 };
322 322
323 static struct spear_pingroup ssp0_cs0_pingroup = { 323 static struct spear_pingroup ssp0_cs0_pingroup = {
324 .name = "ssp0_cs0_grp", 324 .name = "ssp0_cs0_grp",
325 .pins = ssp0_cs0_pins, 325 .pins = ssp0_cs0_pins,
326 .npins = ARRAY_SIZE(ssp0_cs0_pins), 326 .npins = ARRAY_SIZE(ssp0_cs0_pins),
327 .modemuxs = ssp0_cs0_modemux, 327 .modemuxs = ssp0_cs0_modemux,
328 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux), 328 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
329 }; 329 };
330 330
331 /* ssp0_cs1_2 device */ 331 /* ssp0_cs1_2 device */
332 static const unsigned ssp0_cs1_2_pins[] = { 94, 95 }; 332 static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
333 static struct spear_muxreg ssp0_cs1_2_muxreg[] = { 333 static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
334 { 334 {
335 .reg = PAD_FUNCTION_EN_2, 335 .reg = PAD_FUNCTION_EN_2,
336 .mask = PMX_SSP0_CS1_2_MASK, 336 .mask = PMX_SSP0_CS1_2_MASK,
337 .val = PMX_SSP0_CS1_2_MASK, 337 .val = PMX_SSP0_CS1_2_MASK,
338 }, { 338 }, {
339 .reg = PAD_DIRECTION_SEL_2, 339 .reg = PAD_DIRECTION_SEL_2,
340 .mask = PMX_SSP0_CS1_2_MASK, 340 .mask = PMX_SSP0_CS1_2_MASK,
341 .val = PMX_SSP0_CS1_2_MASK, 341 .val = PMX_SSP0_CS1_2_MASK,
342 }, 342 },
343 }; 343 };
344 344
345 static struct spear_modemux ssp0_cs1_2_modemux[] = { 345 static struct spear_modemux ssp0_cs1_2_modemux[] = {
346 { 346 {
347 .muxregs = ssp0_cs1_2_muxreg, 347 .muxregs = ssp0_cs1_2_muxreg,
348 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg), 348 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
349 }, 349 },
350 }; 350 };
351 351
352 static struct spear_pingroup ssp0_cs1_2_pingroup = { 352 static struct spear_pingroup ssp0_cs1_2_pingroup = {
353 .name = "ssp0_cs1_2_grp", 353 .name = "ssp0_cs1_2_grp",
354 .pins = ssp0_cs1_2_pins, 354 .pins = ssp0_cs1_2_pins,
355 .npins = ARRAY_SIZE(ssp0_cs1_2_pins), 355 .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
356 .modemuxs = ssp0_cs1_2_modemux, 356 .modemuxs = ssp0_cs1_2_modemux,
357 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux), 357 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
358 }; 358 };
359 359
360 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp", 360 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
361 "ssp0_cs1_2_grp" }; 361 "ssp0_cs1_2_grp" };
362 static struct spear_function ssp0_function = { 362 static struct spear_function ssp0_function = {
363 .name = "ssp0", 363 .name = "ssp0",
364 .groups = ssp0_grps, 364 .groups = ssp0_grps,
365 .ngroups = ARRAY_SIZE(ssp0_grps), 365 .ngroups = ARRAY_SIZE(ssp0_grps),
366 }; 366 };
367 367
368 /* Pad multiplexing for i2s0 device */ 368 /* Pad multiplexing for i2s0 device */
369 static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 }; 369 static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
370 static struct spear_muxreg i2s0_muxreg[] = { 370 static struct spear_muxreg i2s0_muxreg[] = {
371 { 371 {
372 .reg = PAD_FUNCTION_EN_0, 372 .reg = PAD_FUNCTION_EN_0,
373 .mask = PMX_I2S0_MASK, 373 .mask = PMX_I2S0_MASK,
374 .val = PMX_I2S0_MASK, 374 .val = PMX_I2S0_MASK,
375 }, { 375 }, {
376 .reg = PAD_DIRECTION_SEL_0, 376 .reg = PAD_DIRECTION_SEL_0,
377 .mask = PMX_I2S0_MASK, 377 .mask = PMX_I2S0_MASK,
378 .val = PMX_I2S0_MASK, 378 .val = PMX_I2S0_MASK,
379 }, 379 },
380 }; 380 };
381 381
382 static struct spear_modemux i2s0_modemux[] = { 382 static struct spear_modemux i2s0_modemux[] = {
383 { 383 {
384 .muxregs = i2s0_muxreg, 384 .muxregs = i2s0_muxreg,
385 .nmuxregs = ARRAY_SIZE(i2s0_muxreg), 385 .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
386 }, 386 },
387 }; 387 };
388 388
389 static struct spear_pingroup i2s0_pingroup = { 389 static struct spear_pingroup i2s0_pingroup = {
390 .name = "i2s0_grp", 390 .name = "i2s0_grp",
391 .pins = i2s0_pins, 391 .pins = i2s0_pins,
392 .npins = ARRAY_SIZE(i2s0_pins), 392 .npins = ARRAY_SIZE(i2s0_pins),
393 .modemuxs = i2s0_modemux, 393 .modemuxs = i2s0_modemux,
394 .nmodemuxs = ARRAY_SIZE(i2s0_modemux), 394 .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
395 }; 395 };
396 396
397 static const char *const i2s0_grps[] = { "i2s0_grp" }; 397 static const char *const i2s0_grps[] = { "i2s0_grp" };
398 static struct spear_function i2s0_function = { 398 static struct spear_function i2s0_function = {
399 .name = "i2s0", 399 .name = "i2s0",
400 .groups = i2s0_grps, 400 .groups = i2s0_grps,
401 .ngroups = ARRAY_SIZE(i2s0_grps), 401 .ngroups = ARRAY_SIZE(i2s0_grps),
402 }; 402 };
403 403
404 /* Pad multiplexing for i2s1 device */ 404 /* Pad multiplexing for i2s1 device */
405 static const unsigned i2s1_pins[] = { 0, 1, 2, 3 }; 405 static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
406 static struct spear_muxreg i2s1_muxreg[] = { 406 static struct spear_muxreg i2s1_muxreg[] = {
407 { 407 {
408 .reg = PAD_FUNCTION_EN_1, 408 .reg = PAD_FUNCTION_EN_1,
409 .mask = PMX_I2S1_MASK, 409 .mask = PMX_I2S1_MASK,
410 .val = PMX_I2S1_MASK, 410 .val = PMX_I2S1_MASK,
411 }, { 411 }, {
412 .reg = PAD_DIRECTION_SEL_1, 412 .reg = PAD_DIRECTION_SEL_1,
413 .mask = PMX_I2S1_MASK, 413 .mask = PMX_I2S1_MASK,
414 .val = PMX_I2S1_MASK, 414 .val = PMX_I2S1_MASK,
415 }, 415 },
416 }; 416 };
417 417
418 static struct spear_modemux i2s1_modemux[] = { 418 static struct spear_modemux i2s1_modemux[] = {
419 { 419 {
420 .muxregs = i2s1_muxreg, 420 .muxregs = i2s1_muxreg,
421 .nmuxregs = ARRAY_SIZE(i2s1_muxreg), 421 .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
422 }, 422 },
423 }; 423 };
424 424
425 static struct spear_pingroup i2s1_pingroup = { 425 static struct spear_pingroup i2s1_pingroup = {
426 .name = "i2s1_grp", 426 .name = "i2s1_grp",
427 .pins = i2s1_pins, 427 .pins = i2s1_pins,
428 .npins = ARRAY_SIZE(i2s1_pins), 428 .npins = ARRAY_SIZE(i2s1_pins),
429 .modemuxs = i2s1_modemux, 429 .modemuxs = i2s1_modemux,
430 .nmodemuxs = ARRAY_SIZE(i2s1_modemux), 430 .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
431 }; 431 };
432 432
433 static const char *const i2s1_grps[] = { "i2s1_grp" }; 433 static const char *const i2s1_grps[] = { "i2s1_grp" };
434 static struct spear_function i2s1_function = { 434 static struct spear_function i2s1_function = {
435 .name = "i2s1", 435 .name = "i2s1",
436 .groups = i2s1_grps, 436 .groups = i2s1_grps,
437 .ngroups = ARRAY_SIZE(i2s1_grps), 437 .ngroups = ARRAY_SIZE(i2s1_grps),
438 }; 438 };
439 439
440 /* Pad multiplexing for clcd device */ 440 /* Pad multiplexing for clcd device */
441 static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120, 441 static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
442 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 442 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
443 135, 136, 137, 138, 139, 140, 141, 142 }; 443 135, 136, 137, 138, 139, 140, 141, 142 };
444 static struct spear_muxreg clcd_muxreg[] = { 444 static struct spear_muxreg clcd_muxreg[] = {
445 { 445 {
446 .reg = PAD_FUNCTION_EN_0, 446 .reg = PAD_FUNCTION_EN_0,
447 .mask = PMX_CLCD1_MASK, 447 .mask = PMX_CLCD1_MASK,
448 .val = PMX_CLCD1_MASK, 448 .val = PMX_CLCD1_MASK,
449 }, { 449 }, {
450 .reg = PAD_DIRECTION_SEL_0, 450 .reg = PAD_DIRECTION_SEL_0,
451 .mask = PMX_CLCD1_MASK, 451 .mask = PMX_CLCD1_MASK,
452 .val = PMX_CLCD1_MASK, 452 .val = PMX_CLCD1_MASK,
453 }, 453 },
454 }; 454 };
455 455
456 static struct spear_modemux clcd_modemux[] = { 456 static struct spear_modemux clcd_modemux[] = {
457 { 457 {
458 .muxregs = clcd_muxreg, 458 .muxregs = clcd_muxreg,
459 .nmuxregs = ARRAY_SIZE(clcd_muxreg), 459 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
460 }, 460 },
461 }; 461 };
462 462
463 static struct spear_pingroup clcd_pingroup = { 463 static struct spear_pingroup clcd_pingroup = {
464 .name = "clcd_grp", 464 .name = "clcd_grp",
465 .pins = clcd_pins, 465 .pins = clcd_pins,
466 .npins = ARRAY_SIZE(clcd_pins), 466 .npins = ARRAY_SIZE(clcd_pins),
467 .modemuxs = clcd_modemux, 467 .modemuxs = clcd_modemux,
468 .nmodemuxs = ARRAY_SIZE(clcd_modemux), 468 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
469 }; 469 };
470 470
471 static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37, 471 static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
472 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 }; 472 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
473 static struct spear_muxreg clcd_high_res_muxreg[] = { 473 static struct spear_muxreg clcd_high_res_muxreg[] = {
474 { 474 {
475 .reg = PAD_FUNCTION_EN_1, 475 .reg = PAD_FUNCTION_EN_1,
476 .mask = PMX_CLCD2_MASK, 476 .mask = PMX_CLCD2_MASK,
477 .val = PMX_CLCD2_MASK, 477 .val = PMX_CLCD2_MASK,
478 }, { 478 }, {
479 .reg = PAD_DIRECTION_SEL_1, 479 .reg = PAD_DIRECTION_SEL_1,
480 .mask = PMX_CLCD2_MASK, 480 .mask = PMX_CLCD2_MASK,
481 .val = PMX_CLCD2_MASK, 481 .val = PMX_CLCD2_MASK,
482 }, 482 },
483 }; 483 };
484 484
485 static struct spear_modemux clcd_high_res_modemux[] = { 485 static struct spear_modemux clcd_high_res_modemux[] = {
486 { 486 {
487 .muxregs = clcd_high_res_muxreg, 487 .muxregs = clcd_high_res_muxreg,
488 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg), 488 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
489 }, 489 },
490 }; 490 };
491 491
492 static struct spear_pingroup clcd_high_res_pingroup = { 492 static struct spear_pingroup clcd_high_res_pingroup = {
493 .name = "clcd_high_res_grp", 493 .name = "clcd_high_res_grp",
494 .pins = clcd_high_res_pins, 494 .pins = clcd_high_res_pins,
495 .npins = ARRAY_SIZE(clcd_high_res_pins), 495 .npins = ARRAY_SIZE(clcd_high_res_pins),
496 .modemuxs = clcd_high_res_modemux, 496 .modemuxs = clcd_high_res_modemux,
497 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux), 497 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
498 }; 498 };
499 499
500 static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" }; 500 static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
501 static struct spear_function clcd_function = { 501 static struct spear_function clcd_function = {
502 .name = "clcd", 502 .name = "clcd",
503 .groups = clcd_grps, 503 .groups = clcd_grps,
504 .ngroups = ARRAY_SIZE(clcd_grps), 504 .ngroups = ARRAY_SIZE(clcd_grps),
505 }; 505 };
506 506
507 static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145, 507 static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
508 146, 147, 148, 149, 150, 151, 152 }; 508 146, 147, 148, 149, 150, 151, 152 };
509 static struct spear_muxreg arm_gpio_muxreg[] = { 509 static struct spear_muxreg arm_gpio_muxreg[] = {
510 { 510 {
511 .reg = PAD_FUNCTION_EN_0, 511 .reg = PAD_FUNCTION_EN_0,
512 .mask = PMX_EGPIO_0_GRP_MASK, 512 .mask = PMX_EGPIO_0_GRP_MASK,
513 .val = PMX_EGPIO_0_GRP_MASK, 513 .val = PMX_EGPIO_0_GRP_MASK,
514 }, { 514 }, {
515 .reg = PAD_FUNCTION_EN_1, 515 .reg = PAD_FUNCTION_EN_1,
516 .mask = PMX_EGPIO_1_GRP_MASK, 516 .mask = PMX_EGPIO_1_GRP_MASK,
517 .val = PMX_EGPIO_1_GRP_MASK, 517 .val = PMX_EGPIO_1_GRP_MASK,
518 }, { 518 }, {
519 .reg = PAD_DIRECTION_SEL_0, 519 .reg = PAD_DIRECTION_SEL_0,
520 .mask = PMX_EGPIO_0_GRP_MASK, 520 .mask = PMX_EGPIO_0_GRP_MASK,
521 .val = PMX_EGPIO_0_GRP_MASK, 521 .val = PMX_EGPIO_0_GRP_MASK,
522 }, { 522 }, {
523 .reg = PAD_DIRECTION_SEL_1, 523 .reg = PAD_DIRECTION_SEL_1,
524 .mask = PMX_EGPIO_1_GRP_MASK, 524 .mask = PMX_EGPIO_1_GRP_MASK,
525 .val = PMX_EGPIO_1_GRP_MASK, 525 .val = PMX_EGPIO_1_GRP_MASK,
526 }, 526 },
527 }; 527 };
528 528
529 static struct spear_modemux arm_gpio_modemux[] = { 529 static struct spear_modemux arm_gpio_modemux[] = {
530 { 530 {
531 .muxregs = arm_gpio_muxreg, 531 .muxregs = arm_gpio_muxreg,
532 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg), 532 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
533 }, 533 },
534 }; 534 };
535 535
536 static struct spear_pingroup arm_gpio_pingroup = { 536 static struct spear_pingroup arm_gpio_pingroup = {
537 .name = "arm_gpio_grp", 537 .name = "arm_gpio_grp",
538 .pins = arm_gpio_pins, 538 .pins = arm_gpio_pins,
539 .npins = ARRAY_SIZE(arm_gpio_pins), 539 .npins = ARRAY_SIZE(arm_gpio_pins),
540 .modemuxs = arm_gpio_modemux, 540 .modemuxs = arm_gpio_modemux,
541 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux), 541 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
542 }; 542 };
543 543
544 static const char *const arm_gpio_grps[] = { "arm_gpio_grp" }; 544 static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
545 static struct spear_function arm_gpio_function = { 545 static struct spear_function arm_gpio_function = {
546 .name = "arm_gpio", 546 .name = "arm_gpio",
547 .groups = arm_gpio_grps, 547 .groups = arm_gpio_grps,
548 .ngroups = ARRAY_SIZE(arm_gpio_grps), 548 .ngroups = ARRAY_SIZE(arm_gpio_grps),
549 }; 549 };
550 550
551 /* Pad multiplexing for smi 2 chips device */ 551 /* Pad multiplexing for smi 2 chips device */
552 static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 }; 552 static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
553 static struct spear_muxreg smi_2_chips_muxreg[] = { 553 static struct spear_muxreg smi_2_chips_muxreg[] = {
554 { 554 {
555 .reg = PAD_FUNCTION_EN_0, 555 .reg = PAD_FUNCTION_EN_0,
556 .mask = PMX_SMI_MASK, 556 .mask = PMX_SMI_MASK,
557 .val = PMX_SMI_MASK, 557 .val = PMX_SMI_MASK,
558 }, { 558 }, {
559 .reg = PAD_DIRECTION_SEL_0, 559 .reg = PAD_DIRECTION_SEL_0,
560 .mask = PMX_SMI_MASK, 560 .mask = PMX_SMI_MASK,
561 .val = PMX_SMI_MASK, 561 .val = PMX_SMI_MASK,
562 }, 562 },
563 }; 563 };
564 564
565 static struct spear_modemux smi_2_chips_modemux[] = { 565 static struct spear_modemux smi_2_chips_modemux[] = {
566 { 566 {
567 .muxregs = smi_2_chips_muxreg, 567 .muxregs = smi_2_chips_muxreg,
568 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg), 568 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
569 }, 569 },
570 }; 570 };
571 571
572 static struct spear_pingroup smi_2_chips_pingroup = { 572 static struct spear_pingroup smi_2_chips_pingroup = {
573 .name = "smi_2_chips_grp", 573 .name = "smi_2_chips_grp",
574 .pins = smi_2_chips_pins, 574 .pins = smi_2_chips_pins,
575 .npins = ARRAY_SIZE(smi_2_chips_pins), 575 .npins = ARRAY_SIZE(smi_2_chips_pins),
576 .modemuxs = smi_2_chips_modemux, 576 .modemuxs = smi_2_chips_modemux,
577 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux), 577 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
578 }; 578 };
579 579
580 static const unsigned smi_4_chips_pins[] = { 54, 55 }; 580 static const unsigned smi_4_chips_pins[] = { 54, 55 };
581 static struct spear_muxreg smi_4_chips_muxreg[] = { 581 static struct spear_muxreg smi_4_chips_muxreg[] = {
582 { 582 {
583 .reg = PAD_FUNCTION_EN_0, 583 .reg = PAD_FUNCTION_EN_0,
584 .mask = PMX_SMI_MASK, 584 .mask = PMX_SMI_MASK,
585 .val = PMX_SMI_MASK, 585 .val = PMX_SMI_MASK,
586 }, { 586 }, {
587 .reg = PAD_FUNCTION_EN_1, 587 .reg = PAD_FUNCTION_EN_1,
588 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 588 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
589 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 589 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
590 }, { 590 }, {
591 .reg = PAD_DIRECTION_SEL_0, 591 .reg = PAD_DIRECTION_SEL_0,
592 .mask = PMX_SMI_MASK, 592 .mask = PMX_SMI_MASK,
593 .val = PMX_SMI_MASK, 593 .val = PMX_SMI_MASK,
594 }, { 594 }, {
595 .reg = PAD_DIRECTION_SEL_1, 595 .reg = PAD_DIRECTION_SEL_1,
596 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 596 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
597 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 597 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
598 }, 598 },
599 }; 599 };
600 600
601 static struct spear_modemux smi_4_chips_modemux[] = { 601 static struct spear_modemux smi_4_chips_modemux[] = {
602 { 602 {
603 .muxregs = smi_4_chips_muxreg, 603 .muxregs = smi_4_chips_muxreg,
604 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg), 604 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
605 }, 605 },
606 }; 606 };
607 607
608 static struct spear_pingroup smi_4_chips_pingroup = { 608 static struct spear_pingroup smi_4_chips_pingroup = {
609 .name = "smi_4_chips_grp", 609 .name = "smi_4_chips_grp",
610 .pins = smi_4_chips_pins, 610 .pins = smi_4_chips_pins,
611 .npins = ARRAY_SIZE(smi_4_chips_pins), 611 .npins = ARRAY_SIZE(smi_4_chips_pins),
612 .modemuxs = smi_4_chips_modemux, 612 .modemuxs = smi_4_chips_modemux,
613 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux), 613 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
614 }; 614 };
615 615
616 static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" }; 616 static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
617 static struct spear_function smi_function = { 617 static struct spear_function smi_function = {
618 .name = "smi", 618 .name = "smi",
619 .groups = smi_grps, 619 .groups = smi_grps,
620 .ngroups = ARRAY_SIZE(smi_grps), 620 .ngroups = ARRAY_SIZE(smi_grps),
621 }; 621 };
622 622
623 /* Pad multiplexing for gmii device */ 623 /* Pad multiplexing for gmii device */
624 static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180, 624 static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
625 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 625 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
626 195, 196, 197, 198, 199, 200 }; 626 195, 196, 197, 198, 199, 200 };
627 static struct spear_muxreg gmii_muxreg[] = { 627 static struct spear_muxreg gmii_muxreg[] = {
628 { 628 {
629 .reg = PAD_FUNCTION_EN_0, 629 .reg = PAD_FUNCTION_EN_0,
630 .mask = PMX_GMII_MASK, 630 .mask = PMX_GMII_MASK,
631 .val = PMX_GMII_MASK, 631 .val = PMX_GMII_MASK,
632 }, { 632 }, {
633 .reg = PAD_DIRECTION_SEL_0, 633 .reg = PAD_DIRECTION_SEL_0,
634 .mask = PMX_GMII_MASK, 634 .mask = PMX_GMII_MASK,
635 .val = PMX_GMII_MASK, 635 .val = PMX_GMII_MASK,
636 }, 636 },
637 }; 637 };
638 638
639 static struct spear_modemux gmii_modemux[] = { 639 static struct spear_modemux gmii_modemux[] = {
640 { 640 {
641 .muxregs = gmii_muxreg, 641 .muxregs = gmii_muxreg,
642 .nmuxregs = ARRAY_SIZE(gmii_muxreg), 642 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
643 }, 643 },
644 }; 644 };
645 645
646 static struct spear_pingroup gmii_pingroup = { 646 static struct spear_pingroup gmii_pingroup = {
647 .name = "gmii_grp", 647 .name = "gmii_grp",
648 .pins = gmii_pins, 648 .pins = gmii_pins,
649 .npins = ARRAY_SIZE(gmii_pins), 649 .npins = ARRAY_SIZE(gmii_pins),
650 .modemuxs = gmii_modemux, 650 .modemuxs = gmii_modemux,
651 .nmodemuxs = ARRAY_SIZE(gmii_modemux), 651 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
652 }; 652 };
653 653
654 static const char *const gmii_grps[] = { "gmii_grp" }; 654 static const char *const gmii_grps[] = { "gmii_grp" };
655 static struct spear_function gmii_function = { 655 static struct spear_function gmii_function = {
656 .name = "gmii", 656 .name = "gmii",
657 .groups = gmii_grps, 657 .groups = gmii_grps,
658 .ngroups = ARRAY_SIZE(gmii_grps), 658 .ngroups = ARRAY_SIZE(gmii_grps),
659 }; 659 };
660 660
661 /* Pad multiplexing for rgmii device */ 661 /* Pad multiplexing for rgmii device */
662 static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 662 static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
663 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175, 663 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
664 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 }; 664 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
665 static struct spear_muxreg rgmii_muxreg[] = { 665 static struct spear_muxreg rgmii_muxreg[] = {
666 { 666 {
667 .reg = PAD_FUNCTION_EN_0, 667 .reg = PAD_FUNCTION_EN_0,
668 .mask = PMX_RGMII_REG0_MASK, 668 .mask = PMX_RGMII_REG0_MASK,
669 .val = 0, 669 .val = 0,
670 }, { 670 }, {
671 .reg = PAD_FUNCTION_EN_1, 671 .reg = PAD_FUNCTION_EN_1,
672 .mask = PMX_RGMII_REG1_MASK, 672 .mask = PMX_RGMII_REG1_MASK,
673 .val = 0, 673 .val = 0,
674 }, { 674 }, {
675 .reg = PAD_FUNCTION_EN_2, 675 .reg = PAD_FUNCTION_EN_2,
676 .mask = PMX_RGMII_REG2_MASK, 676 .mask = PMX_RGMII_REG2_MASK,
677 .val = 0, 677 .val = 0,
678 }, { 678 }, {
679 .reg = PAD_DIRECTION_SEL_0, 679 .reg = PAD_DIRECTION_SEL_0,
680 .mask = PMX_RGMII_REG0_MASK, 680 .mask = PMX_RGMII_REG0_MASK,
681 .val = PMX_RGMII_REG0_MASK, 681 .val = PMX_RGMII_REG0_MASK,
682 }, { 682 }, {
683 .reg = PAD_DIRECTION_SEL_1, 683 .reg = PAD_DIRECTION_SEL_1,
684 .mask = PMX_RGMII_REG1_MASK, 684 .mask = PMX_RGMII_REG1_MASK,
685 .val = PMX_RGMII_REG1_MASK, 685 .val = PMX_RGMII_REG1_MASK,
686 }, { 686 }, {
687 .reg = PAD_DIRECTION_SEL_2, 687 .reg = PAD_DIRECTION_SEL_2,
688 .mask = PMX_RGMII_REG2_MASK, 688 .mask = PMX_RGMII_REG2_MASK,
689 .val = PMX_RGMII_REG2_MASK, 689 .val = PMX_RGMII_REG2_MASK,
690 }, 690 },
691 }; 691 };
692 692
693 static struct spear_modemux rgmii_modemux[] = { 693 static struct spear_modemux rgmii_modemux[] = {
694 { 694 {
695 .muxregs = rgmii_muxreg, 695 .muxregs = rgmii_muxreg,
696 .nmuxregs = ARRAY_SIZE(rgmii_muxreg), 696 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
697 }, 697 },
698 }; 698 };
699 699
700 static struct spear_pingroup rgmii_pingroup = { 700 static struct spear_pingroup rgmii_pingroup = {
701 .name = "rgmii_grp", 701 .name = "rgmii_grp",
702 .pins = rgmii_pins, 702 .pins = rgmii_pins,
703 .npins = ARRAY_SIZE(rgmii_pins), 703 .npins = ARRAY_SIZE(rgmii_pins),
704 .modemuxs = rgmii_modemux, 704 .modemuxs = rgmii_modemux,
705 .nmodemuxs = ARRAY_SIZE(rgmii_modemux), 705 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
706 }; 706 };
707 707
708 static const char *const rgmii_grps[] = { "rgmii_grp" }; 708 static const char *const rgmii_grps[] = { "rgmii_grp" };
709 static struct spear_function rgmii_function = { 709 static struct spear_function rgmii_function = {
710 .name = "rgmii", 710 .name = "rgmii",
711 .groups = rgmii_grps, 711 .groups = rgmii_grps,
712 .ngroups = ARRAY_SIZE(rgmii_grps), 712 .ngroups = ARRAY_SIZE(rgmii_grps),
713 }; 713 };
714 714
715 /* Pad multiplexing for smii_0_1_2 device */ 715 /* Pad multiplexing for smii_0_1_2 device */
716 static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, 716 static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
717 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 717 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
718 51, 52, 53, 54, 55 }; 718 51, 52, 53, 54, 55 };
719 static struct spear_muxreg smii_0_1_2_muxreg[] = { 719 static struct spear_muxreg smii_0_1_2_muxreg[] = {
720 { 720 {
721 .reg = PAD_FUNCTION_EN_1, 721 .reg = PAD_FUNCTION_EN_1,
722 .mask = PMX_SMII_0_1_2_MASK, 722 .mask = PMX_SMII_0_1_2_MASK,
723 .val = 0, 723 .val = 0,
724 }, { 724 }, {
725 .reg = PAD_DIRECTION_SEL_1, 725 .reg = PAD_DIRECTION_SEL_1,
726 .mask = PMX_SMII_0_1_2_MASK, 726 .mask = PMX_SMII_0_1_2_MASK,
727 .val = PMX_SMII_0_1_2_MASK, 727 .val = PMX_SMII_0_1_2_MASK,
728 }, 728 },
729 }; 729 };
730 730
731 static struct spear_modemux smii_0_1_2_modemux[] = { 731 static struct spear_modemux smii_0_1_2_modemux[] = {
732 { 732 {
733 .muxregs = smii_0_1_2_muxreg, 733 .muxregs = smii_0_1_2_muxreg,
734 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg), 734 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
735 }, 735 },
736 }; 736 };
737 737
738 static struct spear_pingroup smii_0_1_2_pingroup = { 738 static struct spear_pingroup smii_0_1_2_pingroup = {
739 .name = "smii_0_1_2_grp", 739 .name = "smii_0_1_2_grp",
740 .pins = smii_0_1_2_pins, 740 .pins = smii_0_1_2_pins,
741 .npins = ARRAY_SIZE(smii_0_1_2_pins), 741 .npins = ARRAY_SIZE(smii_0_1_2_pins),
742 .modemuxs = smii_0_1_2_modemux, 742 .modemuxs = smii_0_1_2_modemux,
743 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux), 743 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
744 }; 744 };
745 745
746 static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" }; 746 static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
747 static struct spear_function smii_0_1_2_function = { 747 static struct spear_function smii_0_1_2_function = {
748 .name = "smii_0_1_2", 748 .name = "smii_0_1_2",
749 .groups = smii_0_1_2_grps, 749 .groups = smii_0_1_2_grps,
750 .ngroups = ARRAY_SIZE(smii_0_1_2_grps), 750 .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
751 }; 751 };
752 752
753 /* Pad multiplexing for ras_mii_txclk device */ 753 /* Pad multiplexing for ras_mii_txclk device */
754 static const unsigned ras_mii_txclk_pins[] = { 98, 99 }; 754 static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
755 static struct spear_muxreg ras_mii_txclk_muxreg[] = { 755 static struct spear_muxreg ras_mii_txclk_muxreg[] = {
756 { 756 {
757 .reg = PAD_FUNCTION_EN_1, 757 .reg = PAD_FUNCTION_EN_1,
758 .mask = PMX_NFCE2_MASK, 758 .mask = PMX_NFCE2_MASK,
759 .val = 0, 759 .val = 0,
760 }, { 760 }, {
761 .reg = PAD_DIRECTION_SEL_1, 761 .reg = PAD_DIRECTION_SEL_1,
762 .mask = PMX_NFCE2_MASK, 762 .mask = PMX_NFCE2_MASK,
763 .val = PMX_NFCE2_MASK, 763 .val = PMX_NFCE2_MASK,
764 }, 764 },
765 }; 765 };
766 766
767 static struct spear_modemux ras_mii_txclk_modemux[] = { 767 static struct spear_modemux ras_mii_txclk_modemux[] = {
768 { 768 {
769 .muxregs = ras_mii_txclk_muxreg, 769 .muxregs = ras_mii_txclk_muxreg,
770 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg), 770 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
771 }, 771 },
772 }; 772 };
773 773
774 static struct spear_pingroup ras_mii_txclk_pingroup = { 774 static struct spear_pingroup ras_mii_txclk_pingroup = {
775 .name = "ras_mii_txclk_grp", 775 .name = "ras_mii_txclk_grp",
776 .pins = ras_mii_txclk_pins, 776 .pins = ras_mii_txclk_pins,
777 .npins = ARRAY_SIZE(ras_mii_txclk_pins), 777 .npins = ARRAY_SIZE(ras_mii_txclk_pins),
778 .modemuxs = ras_mii_txclk_modemux, 778 .modemuxs = ras_mii_txclk_modemux,
779 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux), 779 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
780 }; 780 };
781 781
782 static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" }; 782 static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
783 static struct spear_function ras_mii_txclk_function = { 783 static struct spear_function ras_mii_txclk_function = {
784 .name = "ras_mii_txclk", 784 .name = "ras_mii_txclk",
785 .groups = ras_mii_txclk_grps, 785 .groups = ras_mii_txclk_grps,
786 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps), 786 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
787 }; 787 };
788 788
789 /* Pad multiplexing for nand 8bit device (cs0 only) */ 789 /* Pad multiplexing for nand 8bit device (cs0 only) */
790 static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64, 790 static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
791 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 791 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
792 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 792 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
793 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 793 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
794 212 }; 794 212 };
795 static struct spear_muxreg nand_8bit_muxreg[] = { 795 static struct spear_muxreg nand_8bit_muxreg[] = {
796 { 796 {
797 .reg = PAD_FUNCTION_EN_0, 797 .reg = PAD_FUNCTION_EN_0,
798 .mask = PMX_NAND8BIT_0_MASK, 798 .mask = PMX_NAND8BIT_0_MASK,
799 .val = PMX_NAND8BIT_0_MASK, 799 .val = PMX_NAND8BIT_0_MASK,
800 }, { 800 }, {
801 .reg = PAD_FUNCTION_EN_1, 801 .reg = PAD_FUNCTION_EN_1,
802 .mask = PMX_NAND8BIT_1_MASK, 802 .mask = PMX_NAND8BIT_1_MASK,
803 .val = PMX_NAND8BIT_1_MASK, 803 .val = PMX_NAND8BIT_1_MASK,
804 }, { 804 }, {
805 .reg = PAD_DIRECTION_SEL_0, 805 .reg = PAD_DIRECTION_SEL_0,
806 .mask = PMX_NAND8BIT_0_MASK, 806 .mask = PMX_NAND8BIT_0_MASK,
807 .val = PMX_NAND8BIT_0_MASK, 807 .val = PMX_NAND8BIT_0_MASK,
808 }, { 808 }, {
809 .reg = PAD_DIRECTION_SEL_1, 809 .reg = PAD_DIRECTION_SEL_1,
810 .mask = PMX_NAND8BIT_1_MASK, 810 .mask = PMX_NAND8BIT_1_MASK,
811 .val = PMX_NAND8BIT_1_MASK, 811 .val = PMX_NAND8BIT_1_MASK,
812 }, 812 },
813 }; 813 };
814 814
815 static struct spear_modemux nand_8bit_modemux[] = { 815 static struct spear_modemux nand_8bit_modemux[] = {
816 { 816 {
817 .muxregs = nand_8bit_muxreg, 817 .muxregs = nand_8bit_muxreg,
818 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg), 818 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
819 }, 819 },
820 }; 820 };
821 821
822 static struct spear_pingroup nand_8bit_pingroup = { 822 static struct spear_pingroup nand_8bit_pingroup = {
823 .name = "nand_8bit_grp", 823 .name = "nand_8bit_grp",
824 .pins = nand_8bit_pins, 824 .pins = nand_8bit_pins,
825 .npins = ARRAY_SIZE(nand_8bit_pins), 825 .npins = ARRAY_SIZE(nand_8bit_pins),
826 .modemuxs = nand_8bit_modemux, 826 .modemuxs = nand_8bit_modemux,
827 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux), 827 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
828 }; 828 };
829 829
830 /* Pad multiplexing for nand 16bit device */ 830 /* Pad multiplexing for nand 16bit device */
831 static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209, 831 static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
832 210 }; 832 210 };
833 static struct spear_muxreg nand_16bit_muxreg[] = { 833 static struct spear_muxreg nand_16bit_muxreg[] = {
834 { 834 {
835 .reg = PAD_FUNCTION_EN_1, 835 .reg = PAD_FUNCTION_EN_1,
836 .mask = PMX_NAND16BIT_1_MASK, 836 .mask = PMX_NAND16BIT_1_MASK,
837 .val = PMX_NAND16BIT_1_MASK, 837 .val = PMX_NAND16BIT_1_MASK,
838 }, { 838 }, {
839 .reg = PAD_DIRECTION_SEL_1, 839 .reg = PAD_DIRECTION_SEL_1,
840 .mask = PMX_NAND16BIT_1_MASK, 840 .mask = PMX_NAND16BIT_1_MASK,
841 .val = PMX_NAND16BIT_1_MASK, 841 .val = PMX_NAND16BIT_1_MASK,
842 }, 842 },
843 }; 843 };
844 844
845 static struct spear_modemux nand_16bit_modemux[] = { 845 static struct spear_modemux nand_16bit_modemux[] = {
846 { 846 {
847 .muxregs = nand_16bit_muxreg, 847 .muxregs = nand_16bit_muxreg,
848 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg), 848 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
849 }, 849 },
850 }; 850 };
851 851
852 static struct spear_pingroup nand_16bit_pingroup = { 852 static struct spear_pingroup nand_16bit_pingroup = {
853 .name = "nand_16bit_grp", 853 .name = "nand_16bit_grp",
854 .pins = nand_16bit_pins, 854 .pins = nand_16bit_pins,
855 .npins = ARRAY_SIZE(nand_16bit_pins), 855 .npins = ARRAY_SIZE(nand_16bit_pins),
856 .modemuxs = nand_16bit_modemux, 856 .modemuxs = nand_16bit_modemux,
857 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux), 857 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
858 }; 858 };
859 859
860 /* Pad multiplexing for nand 4 chips */ 860 /* Pad multiplexing for nand 4 chips */
861 static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 }; 861 static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
862 static struct spear_muxreg nand_4_chips_muxreg[] = { 862 static struct spear_muxreg nand_4_chips_muxreg[] = {
863 { 863 {
864 .reg = PAD_FUNCTION_EN_1, 864 .reg = PAD_FUNCTION_EN_1,
865 .mask = PMX_NAND_4CHIPS_MASK, 865 .mask = PMX_NAND_4CHIPS_MASK,
866 .val = PMX_NAND_4CHIPS_MASK, 866 .val = PMX_NAND_4CHIPS_MASK,
867 }, { 867 }, {
868 .reg = PAD_DIRECTION_SEL_1, 868 .reg = PAD_DIRECTION_SEL_1,
869 .mask = PMX_NAND_4CHIPS_MASK, 869 .mask = PMX_NAND_4CHIPS_MASK,
870 .val = PMX_NAND_4CHIPS_MASK, 870 .val = PMX_NAND_4CHIPS_MASK,
871 }, 871 },
872 }; 872 };
873 873
874 static struct spear_modemux nand_4_chips_modemux[] = { 874 static struct spear_modemux nand_4_chips_modemux[] = {
875 { 875 {
876 .muxregs = nand_4_chips_muxreg, 876 .muxregs = nand_4_chips_muxreg,
877 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg), 877 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
878 }, 878 },
879 }; 879 };
880 880
881 static struct spear_pingroup nand_4_chips_pingroup = { 881 static struct spear_pingroup nand_4_chips_pingroup = {
882 .name = "nand_4_chips_grp", 882 .name = "nand_4_chips_grp",
883 .pins = nand_4_chips_pins, 883 .pins = nand_4_chips_pins,
884 .npins = ARRAY_SIZE(nand_4_chips_pins), 884 .npins = ARRAY_SIZE(nand_4_chips_pins),
885 .modemuxs = nand_4_chips_modemux, 885 .modemuxs = nand_4_chips_modemux,
886 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux), 886 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
887 }; 887 };
888 888
889 static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp", 889 static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
890 "nand_4_chips_grp" }; 890 "nand_4_chips_grp" };
891 static struct spear_function nand_function = { 891 static struct spear_function nand_function = {
892 .name = "nand", 892 .name = "nand",
893 .groups = nand_grps, 893 .groups = nand_grps,
894 .ngroups = ARRAY_SIZE(nand_grps), 894 .ngroups = ARRAY_SIZE(nand_grps),
895 }; 895 };
896 896
897 /* Pad multiplexing for keyboard_6x6 device */ 897 /* Pad multiplexing for keyboard_6x6 device */
898 static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207, 898 static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
899 208, 209, 210, 211, 212 }; 899 208, 209, 210, 211, 212 };
900 static struct spear_muxreg keyboard_6x6_muxreg[] = { 900 static struct spear_muxreg keyboard_6x6_muxreg[] = {
901 { 901 {
902 .reg = PAD_FUNCTION_EN_1, 902 .reg = PAD_FUNCTION_EN_1,
903 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK | 903 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
904 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | 904 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
905 PMX_NFWPRT2_MASK, 905 PMX_NFWPRT2_MASK,
906 .val = PMX_KEYBOARD_6X6_MASK, 906 .val = PMX_KEYBOARD_6X6_MASK,
907 }, 907 },
908 }; 908 };
909 909
910 static struct spear_modemux keyboard_6x6_modemux[] = { 910 static struct spear_modemux keyboard_6x6_modemux[] = {
911 { 911 {
912 .muxregs = keyboard_6x6_muxreg, 912 .muxregs = keyboard_6x6_muxreg,
913 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg), 913 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
914 }, 914 },
915 }; 915 };
916 916
917 static struct spear_pingroup keyboard_6x6_pingroup = { 917 static struct spear_pingroup keyboard_6x6_pingroup = {
918 .name = "keyboard_6x6_grp", 918 .name = "keyboard_6x6_grp",
919 .pins = keyboard_6x6_pins, 919 .pins = keyboard_6x6_pins,
920 .npins = ARRAY_SIZE(keyboard_6x6_pins), 920 .npins = ARRAY_SIZE(keyboard_6x6_pins),
921 .modemuxs = keyboard_6x6_modemux, 921 .modemuxs = keyboard_6x6_modemux,
922 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux), 922 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
923 }; 923 };
924 924
925 /* Pad multiplexing for keyboard_rowcol6_8 device */ 925 /* Pad multiplexing for keyboard_rowcol6_8 device */
926 static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 }; 926 static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
927 static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = { 927 static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
928 { 928 {
929 .reg = PAD_FUNCTION_EN_1, 929 .reg = PAD_FUNCTION_EN_1,
930 .mask = PMX_KBD_ROWCOL68_MASK, 930 .mask = PMX_KBD_ROWCOL68_MASK,
931 .val = PMX_KBD_ROWCOL68_MASK, 931 .val = PMX_KBD_ROWCOL68_MASK,
932 }, { 932 }, {
933 .reg = PAD_DIRECTION_SEL_1, 933 .reg = PAD_DIRECTION_SEL_1,
934 .mask = PMX_KBD_ROWCOL68_MASK, 934 .mask = PMX_KBD_ROWCOL68_MASK,
935 .val = PMX_KBD_ROWCOL68_MASK, 935 .val = PMX_KBD_ROWCOL68_MASK,
936 }, 936 },
937 }; 937 };
938 938
939 static struct spear_modemux keyboard_rowcol6_8_modemux[] = { 939 static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
940 { 940 {
941 .muxregs = keyboard_rowcol6_8_muxreg, 941 .muxregs = keyboard_rowcol6_8_muxreg,
942 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg), 942 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
943 }, 943 },
944 }; 944 };
945 945
946 static struct spear_pingroup keyboard_rowcol6_8_pingroup = { 946 static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
947 .name = "keyboard_rowcol6_8_grp", 947 .name = "keyboard_rowcol6_8_grp",
948 .pins = keyboard_rowcol6_8_pins, 948 .pins = keyboard_rowcol6_8_pins,
949 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins), 949 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
950 .modemuxs = keyboard_rowcol6_8_modemux, 950 .modemuxs = keyboard_rowcol6_8_modemux,
951 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux), 951 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
952 }; 952 };
953 953
954 static const char *const keyboard_grps[] = { "keyboard_6x6_grp", 954 static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
955 "keyboard_rowcol6_8_grp" }; 955 "keyboard_rowcol6_8_grp" };
956 static struct spear_function keyboard_function = { 956 static struct spear_function keyboard_function = {
957 .name = "keyboard", 957 .name = "keyboard",
958 .groups = keyboard_grps, 958 .groups = keyboard_grps,
959 .ngroups = ARRAY_SIZE(keyboard_grps), 959 .ngroups = ARRAY_SIZE(keyboard_grps),
960 }; 960 };
961 961
962 /* Pad multiplexing for uart0 device */ 962 /* Pad multiplexing for uart0 device */
963 static const unsigned uart0_pins[] = { 100, 101 }; 963 static const unsigned uart0_pins[] = { 100, 101 };
964 static struct spear_muxreg uart0_muxreg[] = { 964 static struct spear_muxreg uart0_muxreg[] = {
965 { 965 {
966 .reg = PAD_FUNCTION_EN_0, 966 .reg = PAD_FUNCTION_EN_0,
967 .mask = PMX_UART0_MASK, 967 .mask = PMX_UART0_MASK,
968 .val = PMX_UART0_MASK, 968 .val = PMX_UART0_MASK,
969 }, { 969 }, {
970 .reg = PAD_DIRECTION_SEL_0, 970 .reg = PAD_DIRECTION_SEL_0,
971 .mask = PMX_UART0_MASK, 971 .mask = PMX_UART0_MASK,
972 .val = PMX_UART0_MASK, 972 .val = PMX_UART0_MASK,
973 }, 973 },
974 }; 974 };
975 975
976 static struct spear_modemux uart0_modemux[] = { 976 static struct spear_modemux uart0_modemux[] = {
977 { 977 {
978 .muxregs = uart0_muxreg, 978 .muxregs = uart0_muxreg,
979 .nmuxregs = ARRAY_SIZE(uart0_muxreg), 979 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
980 }, 980 },
981 }; 981 };
982 982
983 static struct spear_pingroup uart0_pingroup = { 983 static struct spear_pingroup uart0_pingroup = {
984 .name = "uart0_grp", 984 .name = "uart0_grp",
985 .pins = uart0_pins, 985 .pins = uart0_pins,
986 .npins = ARRAY_SIZE(uart0_pins), 986 .npins = ARRAY_SIZE(uart0_pins),
987 .modemuxs = uart0_modemux, 987 .modemuxs = uart0_modemux,
988 .nmodemuxs = ARRAY_SIZE(uart0_modemux), 988 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
989 }; 989 };
990 990
991 /* Pad multiplexing for uart0_modem device */ 991 /* Pad multiplexing for uart0_modem device */
992 static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 }; 992 static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
993 static struct spear_muxreg uart0_modem_muxreg[] = { 993 static struct spear_muxreg uart0_modem_muxreg[] = {
994 { 994 {
995 .reg = PAD_FUNCTION_EN_1, 995 .reg = PAD_FUNCTION_EN_1,
996 .mask = PMX_UART0_MODEM_MASK, 996 .mask = PMX_UART0_MODEM_MASK,
997 .val = PMX_UART0_MODEM_MASK, 997 .val = PMX_UART0_MODEM_MASK,
998 }, { 998 }, {
999 .reg = PAD_DIRECTION_SEL_1, 999 .reg = PAD_DIRECTION_SEL_1,
1000 .mask = PMX_UART0_MODEM_MASK, 1000 .mask = PMX_UART0_MODEM_MASK,
1001 .val = PMX_UART0_MODEM_MASK, 1001 .val = PMX_UART0_MODEM_MASK,
1002 }, 1002 },
1003 }; 1003 };
1004 1004
1005 static struct spear_modemux uart0_modem_modemux[] = { 1005 static struct spear_modemux uart0_modem_modemux[] = {
1006 { 1006 {
1007 .muxregs = uart0_modem_muxreg, 1007 .muxregs = uart0_modem_muxreg,
1008 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg), 1008 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
1009 }, 1009 },
1010 }; 1010 };
1011 1011
1012 static struct spear_pingroup uart0_modem_pingroup = { 1012 static struct spear_pingroup uart0_modem_pingroup = {
1013 .name = "uart0_modem_grp", 1013 .name = "uart0_modem_grp",
1014 .pins = uart0_modem_pins, 1014 .pins = uart0_modem_pins,
1015 .npins = ARRAY_SIZE(uart0_modem_pins), 1015 .npins = ARRAY_SIZE(uart0_modem_pins),
1016 .modemuxs = uart0_modem_modemux, 1016 .modemuxs = uart0_modem_modemux,
1017 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux), 1017 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
1018 }; 1018 };
1019 1019
1020 static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" }; 1020 static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
1021 static struct spear_function uart0_function = { 1021 static struct spear_function uart0_function = {
1022 .name = "uart0", 1022 .name = "uart0",
1023 .groups = uart0_grps, 1023 .groups = uart0_grps,
1024 .ngroups = ARRAY_SIZE(uart0_grps), 1024 .ngroups = ARRAY_SIZE(uart0_grps),
1025 }; 1025 };
1026 1026
1027 /* Pad multiplexing for gpt0_tmr0 device */ 1027 /* Pad multiplexing for gpt0_tmr0 device */
1028 static const unsigned gpt0_tmr0_pins[] = { 10, 11 }; 1028 static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
1029 static struct spear_muxreg gpt0_tmr0_muxreg[] = { 1029 static struct spear_muxreg gpt0_tmr0_muxreg[] = {
1030 { 1030 {
1031 .reg = PAD_FUNCTION_EN_1, 1031 .reg = PAD_FUNCTION_EN_1,
1032 .mask = PMX_GPT0_TMR0_MASK, 1032 .mask = PMX_GPT0_TMR0_MASK,
1033 .val = PMX_GPT0_TMR0_MASK, 1033 .val = PMX_GPT0_TMR0_MASK,
1034 }, { 1034 }, {
1035 .reg = PAD_DIRECTION_SEL_1, 1035 .reg = PAD_DIRECTION_SEL_1,
1036 .mask = PMX_GPT0_TMR0_MASK, 1036 .mask = PMX_GPT0_TMR0_MASK,
1037 .val = PMX_GPT0_TMR0_MASK, 1037 .val = PMX_GPT0_TMR0_MASK,
1038 }, 1038 },
1039 }; 1039 };
1040 1040
1041 static struct spear_modemux gpt0_tmr0_modemux[] = { 1041 static struct spear_modemux gpt0_tmr0_modemux[] = {
1042 { 1042 {
1043 .muxregs = gpt0_tmr0_muxreg, 1043 .muxregs = gpt0_tmr0_muxreg,
1044 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg), 1044 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
1045 }, 1045 },
1046 }; 1046 };
1047 1047
1048 static struct spear_pingroup gpt0_tmr0_pingroup = { 1048 static struct spear_pingroup gpt0_tmr0_pingroup = {
1049 .name = "gpt0_tmr0_grp", 1049 .name = "gpt0_tmr0_grp",
1050 .pins = gpt0_tmr0_pins, 1050 .pins = gpt0_tmr0_pins,
1051 .npins = ARRAY_SIZE(gpt0_tmr0_pins), 1051 .npins = ARRAY_SIZE(gpt0_tmr0_pins),
1052 .modemuxs = gpt0_tmr0_modemux, 1052 .modemuxs = gpt0_tmr0_modemux,
1053 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux), 1053 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
1054 }; 1054 };
1055 1055
1056 /* Pad multiplexing for gpt0_tmr1 device */ 1056 /* Pad multiplexing for gpt0_tmr1 device */
1057 static const unsigned gpt0_tmr1_pins[] = { 8, 9 }; 1057 static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
1058 static struct spear_muxreg gpt0_tmr1_muxreg[] = { 1058 static struct spear_muxreg gpt0_tmr1_muxreg[] = {
1059 { 1059 {
1060 .reg = PAD_FUNCTION_EN_1, 1060 .reg = PAD_FUNCTION_EN_1,
1061 .mask = PMX_GPT0_TMR1_MASK, 1061 .mask = PMX_GPT0_TMR1_MASK,
1062 .val = PMX_GPT0_TMR1_MASK, 1062 .val = PMX_GPT0_TMR1_MASK,
1063 }, { 1063 }, {
1064 .reg = PAD_DIRECTION_SEL_1, 1064 .reg = PAD_DIRECTION_SEL_1,
1065 .mask = PMX_GPT0_TMR1_MASK, 1065 .mask = PMX_GPT0_TMR1_MASK,
1066 .val = PMX_GPT0_TMR1_MASK, 1066 .val = PMX_GPT0_TMR1_MASK,
1067 }, 1067 },
1068 }; 1068 };
1069 1069
1070 static struct spear_modemux gpt0_tmr1_modemux[] = { 1070 static struct spear_modemux gpt0_tmr1_modemux[] = {
1071 { 1071 {
1072 .muxregs = gpt0_tmr1_muxreg, 1072 .muxregs = gpt0_tmr1_muxreg,
1073 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg), 1073 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
1074 }, 1074 },
1075 }; 1075 };
1076 1076
1077 static struct spear_pingroup gpt0_tmr1_pingroup = { 1077 static struct spear_pingroup gpt0_tmr1_pingroup = {
1078 .name = "gpt0_tmr1_grp", 1078 .name = "gpt0_tmr1_grp",
1079 .pins = gpt0_tmr1_pins, 1079 .pins = gpt0_tmr1_pins,
1080 .npins = ARRAY_SIZE(gpt0_tmr1_pins), 1080 .npins = ARRAY_SIZE(gpt0_tmr1_pins),
1081 .modemuxs = gpt0_tmr1_modemux, 1081 .modemuxs = gpt0_tmr1_modemux,
1082 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux), 1082 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
1083 }; 1083 };
1084 1084
1085 static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" }; 1085 static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
1086 static struct spear_function gpt0_function = { 1086 static struct spear_function gpt0_function = {
1087 .name = "gpt0", 1087 .name = "gpt0",
1088 .groups = gpt0_grps, 1088 .groups = gpt0_grps,
1089 .ngroups = ARRAY_SIZE(gpt0_grps), 1089 .ngroups = ARRAY_SIZE(gpt0_grps),
1090 }; 1090 };
1091 1091
1092 /* Pad multiplexing for gpt1_tmr0 device */ 1092 /* Pad multiplexing for gpt1_tmr0 device */
1093 static const unsigned gpt1_tmr0_pins[] = { 6, 7 }; 1093 static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
1094 static struct spear_muxreg gpt1_tmr0_muxreg[] = { 1094 static struct spear_muxreg gpt1_tmr0_muxreg[] = {
1095 { 1095 {
1096 .reg = PAD_FUNCTION_EN_1, 1096 .reg = PAD_FUNCTION_EN_1,
1097 .mask = PMX_GPT1_TMR0_MASK, 1097 .mask = PMX_GPT1_TMR0_MASK,
1098 .val = PMX_GPT1_TMR0_MASK, 1098 .val = PMX_GPT1_TMR0_MASK,
1099 }, { 1099 }, {
1100 .reg = PAD_DIRECTION_SEL_1, 1100 .reg = PAD_DIRECTION_SEL_1,
1101 .mask = PMX_GPT1_TMR0_MASK, 1101 .mask = PMX_GPT1_TMR0_MASK,
1102 .val = PMX_GPT1_TMR0_MASK, 1102 .val = PMX_GPT1_TMR0_MASK,
1103 }, 1103 },
1104 }; 1104 };
1105 1105
1106 static struct spear_modemux gpt1_tmr0_modemux[] = { 1106 static struct spear_modemux gpt1_tmr0_modemux[] = {
1107 { 1107 {
1108 .muxregs = gpt1_tmr0_muxreg, 1108 .muxregs = gpt1_tmr0_muxreg,
1109 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg), 1109 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
1110 }, 1110 },
1111 }; 1111 };
1112 1112
1113 static struct spear_pingroup gpt1_tmr0_pingroup = { 1113 static struct spear_pingroup gpt1_tmr0_pingroup = {
1114 .name = "gpt1_tmr0_grp", 1114 .name = "gpt1_tmr0_grp",
1115 .pins = gpt1_tmr0_pins, 1115 .pins = gpt1_tmr0_pins,
1116 .npins = ARRAY_SIZE(gpt1_tmr0_pins), 1116 .npins = ARRAY_SIZE(gpt1_tmr0_pins),
1117 .modemuxs = gpt1_tmr0_modemux, 1117 .modemuxs = gpt1_tmr0_modemux,
1118 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux), 1118 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
1119 }; 1119 };
1120 1120
1121 /* Pad multiplexing for gpt1_tmr1 device */ 1121 /* Pad multiplexing for gpt1_tmr1 device */
1122 static const unsigned gpt1_tmr1_pins[] = { 4, 5 }; 1122 static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
1123 static struct spear_muxreg gpt1_tmr1_muxreg[] = { 1123 static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1124 { 1124 {
1125 .reg = PAD_FUNCTION_EN_1, 1125 .reg = PAD_FUNCTION_EN_1,
1126 .mask = PMX_GPT1_TMR1_MASK, 1126 .mask = PMX_GPT1_TMR1_MASK,
1127 .val = PMX_GPT1_TMR1_MASK, 1127 .val = PMX_GPT1_TMR1_MASK,
1128 }, { 1128 }, {
1129 .reg = PAD_DIRECTION_SEL_1, 1129 .reg = PAD_DIRECTION_SEL_1,
1130 .mask = PMX_GPT1_TMR1_MASK, 1130 .mask = PMX_GPT1_TMR1_MASK,
1131 .val = PMX_GPT1_TMR1_MASK, 1131 .val = PMX_GPT1_TMR1_MASK,
1132 }, 1132 },
1133 }; 1133 };
1134 1134
1135 static struct spear_modemux gpt1_tmr1_modemux[] = { 1135 static struct spear_modemux gpt1_tmr1_modemux[] = {
1136 { 1136 {
1137 .muxregs = gpt1_tmr1_muxreg, 1137 .muxregs = gpt1_tmr1_muxreg,
1138 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg), 1138 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
1139 }, 1139 },
1140 }; 1140 };
1141 1141
1142 static struct spear_pingroup gpt1_tmr1_pingroup = { 1142 static struct spear_pingroup gpt1_tmr1_pingroup = {
1143 .name = "gpt1_tmr1_grp", 1143 .name = "gpt1_tmr1_grp",
1144 .pins = gpt1_tmr1_pins, 1144 .pins = gpt1_tmr1_pins,
1145 .npins = ARRAY_SIZE(gpt1_tmr1_pins), 1145 .npins = ARRAY_SIZE(gpt1_tmr1_pins),
1146 .modemuxs = gpt1_tmr1_modemux, 1146 .modemuxs = gpt1_tmr1_modemux,
1147 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux), 1147 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
1148 }; 1148 };
1149 1149
1150 static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" }; 1150 static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
1151 static struct spear_function gpt1_function = { 1151 static struct spear_function gpt1_function = {
1152 .name = "gpt1", 1152 .name = "gpt1",
1153 .groups = gpt1_grps, 1153 .groups = gpt1_grps,
1154 .ngroups = ARRAY_SIZE(gpt1_grps), 1154 .ngroups = ARRAY_SIZE(gpt1_grps),
1155 }; 1155 };
1156 1156
1157 /* Pad multiplexing for mcif device */ 1157 /* Pad multiplexing for mcif device */
1158 static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214, 1158 static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1159 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 1159 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1160 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 1160 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
1161 243, 244, 245 }; 1161 243, 244, 245 };
1162 #define MCIF_MUXREG \ 1162 #define MCIF_MUXREG \
1163 { \ 1163 { \
1164 .reg = PAD_FUNCTION_EN_0, \ 1164 .reg = PAD_FUNCTION_EN_0, \
1165 .mask = PMX_MCI_DATA8_15_MASK, \ 1165 .mask = PMX_MCI_DATA8_15_MASK, \
1166 .val = PMX_MCI_DATA8_15_MASK, \ 1166 .val = PMX_MCI_DATA8_15_MASK, \
1167 }, { \ 1167 }, { \
1168 .reg = PAD_FUNCTION_EN_1, \ 1168 .reg = PAD_FUNCTION_EN_1, \
1169 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ 1169 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1170 PMX_NFWPRT2_MASK, \ 1170 PMX_NFWPRT2_MASK, \
1171 .val = PMX_MCIFALL_1_MASK, \ 1171 .val = PMX_MCIFALL_1_MASK, \
1172 }, { \ 1172 }, { \
1173 .reg = PAD_FUNCTION_EN_2, \ 1173 .reg = PAD_FUNCTION_EN_2, \
1174 .mask = PMX_MCIFALL_2_MASK, \ 1174 .mask = PMX_MCIFALL_2_MASK, \
1175 .val = PMX_MCIFALL_2_MASK, \ 1175 .val = PMX_MCIFALL_2_MASK, \
1176 }, { \ 1176 }, { \
1177 .reg = PAD_DIRECTION_SEL_0, \ 1177 .reg = PAD_DIRECTION_SEL_0, \
1178 .mask = PMX_MCI_DATA8_15_MASK, \ 1178 .mask = PMX_MCI_DATA8_15_MASK, \
1179 .val = PMX_MCI_DATA8_15_MASK, \ 1179 .val = PMX_MCI_DATA8_15_MASK, \
1180 }, { \ 1180 }, { \
1181 .reg = PAD_DIRECTION_SEL_1, \ 1181 .reg = PAD_DIRECTION_SEL_1, \
1182 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ 1182 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1183 PMX_NFWPRT2_MASK, \ 1183 PMX_NFWPRT2_MASK, \
1184 .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ 1184 .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1185 PMX_NFWPRT2_MASK, \ 1185 PMX_NFWPRT2_MASK, \
1186 }, { \ 1186 }, { \
1187 .reg = PAD_DIRECTION_SEL_2, \ 1187 .reg = PAD_DIRECTION_SEL_2, \
1188 .mask = PMX_MCIFALL_2_MASK, \ 1188 .mask = PMX_MCIFALL_2_MASK, \
1189 .val = PMX_MCIFALL_2_MASK, \ 1189 .val = PMX_MCIFALL_2_MASK, \
1190 } 1190 }
1191 1191
1192 /* sdhci device */ 1192 /* sdhci device */
1193 static struct spear_muxreg sdhci_muxreg[] = { 1193 static struct spear_muxreg sdhci_muxreg[] = {
1194 MCIF_MUXREG, 1194 MCIF_MUXREG,
1195 { 1195 {
1196 .reg = PERIP_CFG, 1196 .reg = PERIP_CFG,
1197 .mask = MCIF_SEL_MASK, 1197 .mask = MCIF_SEL_MASK,
1198 .val = MCIF_SEL_SD, 1198 .val = MCIF_SEL_SD,
1199 }, 1199 },
1200 }; 1200 };
1201 1201
1202 static struct spear_modemux sdhci_modemux[] = { 1202 static struct spear_modemux sdhci_modemux[] = {
1203 { 1203 {
1204 .muxregs = sdhci_muxreg, 1204 .muxregs = sdhci_muxreg,
1205 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), 1205 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1206 }, 1206 },
1207 }; 1207 };
1208 1208
1209 static struct spear_pingroup sdhci_pingroup = { 1209 static struct spear_pingroup sdhci_pingroup = {
1210 .name = "sdhci_grp", 1210 .name = "sdhci_grp",
1211 .pins = mcif_pins, 1211 .pins = mcif_pins,
1212 .npins = ARRAY_SIZE(mcif_pins), 1212 .npins = ARRAY_SIZE(mcif_pins),
1213 .modemuxs = sdhci_modemux, 1213 .modemuxs = sdhci_modemux,
1214 .nmodemuxs = ARRAY_SIZE(sdhci_modemux), 1214 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1215 }; 1215 };
1216 1216
1217 static const char *const sdhci_grps[] = { "sdhci_grp" }; 1217 static const char *const sdhci_grps[] = { "sdhci_grp" };
1218 static struct spear_function sdhci_function = { 1218 static struct spear_function sdhci_function = {
1219 .name = "sdhci", 1219 .name = "sdhci",
1220 .groups = sdhci_grps, 1220 .groups = sdhci_grps,
1221 .ngroups = ARRAY_SIZE(sdhci_grps), 1221 .ngroups = ARRAY_SIZE(sdhci_grps),
1222 }; 1222 };
1223 1223
1224 /* cf device */ 1224 /* cf device */
1225 static struct spear_muxreg cf_muxreg[] = { 1225 static struct spear_muxreg cf_muxreg[] = {
1226 MCIF_MUXREG, 1226 MCIF_MUXREG,
1227 { 1227 {
1228 .reg = PERIP_CFG, 1228 .reg = PERIP_CFG,
1229 .mask = MCIF_SEL_MASK, 1229 .mask = MCIF_SEL_MASK,
1230 .val = MCIF_SEL_CF, 1230 .val = MCIF_SEL_CF,
1231 }, 1231 },
1232 }; 1232 };
1233 1233
1234 static struct spear_modemux cf_modemux[] = { 1234 static struct spear_modemux cf_modemux[] = {
1235 { 1235 {
1236 .muxregs = cf_muxreg, 1236 .muxregs = cf_muxreg,
1237 .nmuxregs = ARRAY_SIZE(cf_muxreg), 1237 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1238 }, 1238 },
1239 }; 1239 };
1240 1240
1241 static struct spear_pingroup cf_pingroup = { 1241 static struct spear_pingroup cf_pingroup = {
1242 .name = "cf_grp", 1242 .name = "cf_grp",
1243 .pins = mcif_pins, 1243 .pins = mcif_pins,
1244 .npins = ARRAY_SIZE(mcif_pins), 1244 .npins = ARRAY_SIZE(mcif_pins),
1245 .modemuxs = cf_modemux, 1245 .modemuxs = cf_modemux,
1246 .nmodemuxs = ARRAY_SIZE(cf_modemux), 1246 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1247 }; 1247 };
1248 1248
1249 static const char *const cf_grps[] = { "cf_grp" }; 1249 static const char *const cf_grps[] = { "cf_grp" };
1250 static struct spear_function cf_function = { 1250 static struct spear_function cf_function = {
1251 .name = "cf", 1251 .name = "cf",
1252 .groups = cf_grps, 1252 .groups = cf_grps,
1253 .ngroups = ARRAY_SIZE(cf_grps), 1253 .ngroups = ARRAY_SIZE(cf_grps),
1254 }; 1254 };
1255 1255
1256 /* xd device */ 1256 /* xd device */
1257 static struct spear_muxreg xd_muxreg[] = { 1257 static struct spear_muxreg xd_muxreg[] = {
1258 MCIF_MUXREG, 1258 MCIF_MUXREG,
1259 { 1259 {
1260 .reg = PERIP_CFG, 1260 .reg = PERIP_CFG,
1261 .mask = MCIF_SEL_MASK, 1261 .mask = MCIF_SEL_MASK,
1262 .val = MCIF_SEL_XD, 1262 .val = MCIF_SEL_XD,
1263 }, 1263 },
1264 }; 1264 };
1265 1265
1266 static struct spear_modemux xd_modemux[] = { 1266 static struct spear_modemux xd_modemux[] = {
1267 { 1267 {
1268 .muxregs = xd_muxreg, 1268 .muxregs = xd_muxreg,
1269 .nmuxregs = ARRAY_SIZE(xd_muxreg), 1269 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1270 }, 1270 },
1271 }; 1271 };
1272 1272
1273 static struct spear_pingroup xd_pingroup = { 1273 static struct spear_pingroup xd_pingroup = {
1274 .name = "xd_grp", 1274 .name = "xd_grp",
1275 .pins = mcif_pins, 1275 .pins = mcif_pins,
1276 .npins = ARRAY_SIZE(mcif_pins), 1276 .npins = ARRAY_SIZE(mcif_pins),
1277 .modemuxs = xd_modemux, 1277 .modemuxs = xd_modemux,
1278 .nmodemuxs = ARRAY_SIZE(xd_modemux), 1278 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1279 }; 1279 };
1280 1280
1281 static const char *const xd_grps[] = { "xd_grp" }; 1281 static const char *const xd_grps[] = { "xd_grp" };
1282 static struct spear_function xd_function = { 1282 static struct spear_function xd_function = {
1283 .name = "xd", 1283 .name = "xd",
1284 .groups = xd_grps, 1284 .groups = xd_grps,
1285 .ngroups = ARRAY_SIZE(xd_grps), 1285 .ngroups = ARRAY_SIZE(xd_grps),
1286 }; 1286 };
1287 1287
1288 /* Pad multiplexing for touch_xy device */ 1288 /* Pad multiplexing for touch_xy device */
1289 static const unsigned touch_xy_pins[] = { 97 }; 1289 static const unsigned touch_xy_pins[] = { 97 };
1290 static struct spear_muxreg touch_xy_muxreg[] = { 1290 static struct spear_muxreg touch_xy_muxreg[] = {
1291 { 1291 {
1292 .reg = PAD_FUNCTION_EN_2, 1292 .reg = PAD_FUNCTION_EN_2,
1293 .mask = PMX_TOUCH_XY_MASK, 1293 .mask = PMX_TOUCH_XY_MASK,
1294 .val = PMX_TOUCH_XY_MASK, 1294 .val = PMX_TOUCH_XY_MASK,
1295 }, { 1295 }, {
1296 .reg = PAD_DIRECTION_SEL_2, 1296 .reg = PAD_DIRECTION_SEL_2,
1297 .mask = PMX_TOUCH_XY_MASK, 1297 .mask = PMX_TOUCH_XY_MASK,
1298 .val = PMX_TOUCH_XY_MASK, 1298 .val = PMX_TOUCH_XY_MASK,
1299 }, 1299 },
1300 }; 1300 };
1301 1301
1302 static struct spear_modemux touch_xy_modemux[] = { 1302 static struct spear_modemux touch_xy_modemux[] = {
1303 { 1303 {
1304 .muxregs = touch_xy_muxreg, 1304 .muxregs = touch_xy_muxreg,
1305 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg), 1305 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
1306 }, 1306 },
1307 }; 1307 };
1308 1308
1309 static struct spear_pingroup touch_xy_pingroup = { 1309 static struct spear_pingroup touch_xy_pingroup = {
1310 .name = "touch_xy_grp", 1310 .name = "touch_xy_grp",
1311 .pins = touch_xy_pins, 1311 .pins = touch_xy_pins,
1312 .npins = ARRAY_SIZE(touch_xy_pins), 1312 .npins = ARRAY_SIZE(touch_xy_pins),
1313 .modemuxs = touch_xy_modemux, 1313 .modemuxs = touch_xy_modemux,
1314 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux), 1314 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
1315 }; 1315 };
1316 1316
1317 static const char *const touch_xy_grps[] = { "touch_xy_grp" }; 1317 static const char *const touch_xy_grps[] = { "touch_xy_grp" };
1318 static struct spear_function touch_xy_function = { 1318 static struct spear_function touch_xy_function = {
1319 .name = "touchscreen", 1319 .name = "touchscreen",
1320 .groups = touch_xy_grps, 1320 .groups = touch_xy_grps,
1321 .ngroups = ARRAY_SIZE(touch_xy_grps), 1321 .ngroups = ARRAY_SIZE(touch_xy_grps),
1322 }; 1322 };
1323 1323
1324 /* Pad multiplexing for uart1 device */ 1324 /* Pad multiplexing for uart1 device */
1325 /* Muxed with I2C */ 1325 /* Muxed with I2C */
1326 static const unsigned uart1_dis_i2c_pins[] = { 102, 103 }; 1326 static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
1327 static struct spear_muxreg uart1_dis_i2c_muxreg[] = { 1327 static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1328 { 1328 {
1329 .reg = PAD_FUNCTION_EN_0, 1329 .reg = PAD_FUNCTION_EN_0,
1330 .mask = PMX_I2C0_MASK, 1330 .mask = PMX_I2C0_MASK,
1331 .val = 0, 1331 .val = 0,
1332 }, { 1332 }, {
1333 .reg = PAD_DIRECTION_SEL_0, 1333 .reg = PAD_DIRECTION_SEL_0,
1334 .mask = PMX_I2C0_MASK, 1334 .mask = PMX_I2C0_MASK,
1335 .val = PMX_I2C0_MASK, 1335 .val = PMX_I2C0_MASK,
1336 }, 1336 },
1337 }; 1337 };
1338 1338
1339 static struct spear_modemux uart1_dis_i2c_modemux[] = { 1339 static struct spear_modemux uart1_dis_i2c_modemux[] = {
1340 { 1340 {
1341 .muxregs = uart1_dis_i2c_muxreg, 1341 .muxregs = uart1_dis_i2c_muxreg,
1342 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg), 1342 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
1343 }, 1343 },
1344 }; 1344 };
1345 1345
1346 static struct spear_pingroup uart_1_dis_i2c_pingroup = { 1346 static struct spear_pingroup uart_1_dis_i2c_pingroup = {
1347 .name = "uart1_disable_i2c_grp", 1347 .name = "uart1_disable_i2c_grp",
1348 .pins = uart1_dis_i2c_pins, 1348 .pins = uart1_dis_i2c_pins,
1349 .npins = ARRAY_SIZE(uart1_dis_i2c_pins), 1349 .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
1350 .modemuxs = uart1_dis_i2c_modemux, 1350 .modemuxs = uart1_dis_i2c_modemux,
1351 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux), 1351 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
1352 }; 1352 };
1353 1353
1354 /* Muxed with SD/MMC */ 1354 /* Muxed with SD/MMC */
1355 static const unsigned uart1_dis_sd_pins[] = { 214, 215 }; 1355 static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
1356 static struct spear_muxreg uart1_dis_sd_muxreg[] = { 1356 static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1357 { 1357 {
1358 .reg = PAD_FUNCTION_EN_1, 1358 .reg = PAD_FUNCTION_EN_1,
1359 .mask = PMX_MCIDATA1_MASK | 1359 .mask = PMX_MCIDATA1_MASK |
1360 PMX_MCIDATA2_MASK, 1360 PMX_MCIDATA2_MASK,
1361 .val = 0, 1361 .val = 0,
1362 }, { 1362 }, {
1363 .reg = PAD_DIRECTION_SEL_1, 1363 .reg = PAD_DIRECTION_SEL_1,
1364 .mask = PMX_MCIDATA1_MASK | 1364 .mask = PMX_MCIDATA1_MASK |
1365 PMX_MCIDATA2_MASK, 1365 PMX_MCIDATA2_MASK,
1366 .val = PMX_MCIDATA1_MASK | 1366 .val = PMX_MCIDATA1_MASK |
1367 PMX_MCIDATA2_MASK, 1367 PMX_MCIDATA2_MASK,
1368 }, 1368 },
1369 }; 1369 };
1370 1370
1371 static struct spear_modemux uart1_dis_sd_modemux[] = { 1371 static struct spear_modemux uart1_dis_sd_modemux[] = {
1372 { 1372 {
1373 .muxregs = uart1_dis_sd_muxreg, 1373 .muxregs = uart1_dis_sd_muxreg,
1374 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg), 1374 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
1375 }, 1375 },
1376 }; 1376 };
1377 1377
1378 static struct spear_pingroup uart_1_dis_sd_pingroup = { 1378 static struct spear_pingroup uart_1_dis_sd_pingroup = {
1379 .name = "uart1_disable_sd_grp", 1379 .name = "uart1_disable_sd_grp",
1380 .pins = uart1_dis_sd_pins, 1380 .pins = uart1_dis_sd_pins,
1381 .npins = ARRAY_SIZE(uart1_dis_sd_pins), 1381 .npins = ARRAY_SIZE(uart1_dis_sd_pins),
1382 .modemuxs = uart1_dis_sd_modemux, 1382 .modemuxs = uart1_dis_sd_modemux,
1383 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux), 1383 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
1384 }; 1384 };
1385 1385
1386 static const char *const uart1_grps[] = { "uart1_disable_i2c_grp", 1386 static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
1387 "uart1_disable_sd_grp" }; 1387 "uart1_disable_sd_grp" };
1388 static struct spear_function uart1_function = { 1388 static struct spear_function uart1_function = {
1389 .name = "uart1", 1389 .name = "uart1",
1390 .groups = uart1_grps, 1390 .groups = uart1_grps,
1391 .ngroups = ARRAY_SIZE(uart1_grps), 1391 .ngroups = ARRAY_SIZE(uart1_grps),
1392 }; 1392 };
1393 1393
1394 /* Pad multiplexing for uart2_3 device */ 1394 /* Pad multiplexing for uart2_3 device */
1395 static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 }; 1395 static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
1396 static struct spear_muxreg uart2_3_muxreg[] = { 1396 static struct spear_muxreg uart2_3_muxreg[] = {
1397 { 1397 {
1398 .reg = PAD_FUNCTION_EN_0, 1398 .reg = PAD_FUNCTION_EN_0,
1399 .mask = PMX_I2S0_MASK, 1399 .mask = PMX_I2S0_MASK,
1400 .val = 0, 1400 .val = 0,
1401 }, { 1401 }, {
1402 .reg = PAD_DIRECTION_SEL_0, 1402 .reg = PAD_DIRECTION_SEL_0,
1403 .mask = PMX_I2S0_MASK, 1403 .mask = PMX_I2S0_MASK,
1404 .val = PMX_I2S0_MASK, 1404 .val = PMX_I2S0_MASK,
1405 }, 1405 },
1406 }; 1406 };
1407 1407
1408 static struct spear_modemux uart2_3_modemux[] = { 1408 static struct spear_modemux uart2_3_modemux[] = {
1409 { 1409 {
1410 .muxregs = uart2_3_muxreg, 1410 .muxregs = uart2_3_muxreg,
1411 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg), 1411 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
1412 }, 1412 },
1413 }; 1413 };
1414 1414
1415 static struct spear_pingroup uart_2_3_pingroup = { 1415 static struct spear_pingroup uart_2_3_pingroup = {
1416 .name = "uart2_3_grp", 1416 .name = "uart2_3_grp",
1417 .pins = uart2_3_pins, 1417 .pins = uart2_3_pins,
1418 .npins = ARRAY_SIZE(uart2_3_pins), 1418 .npins = ARRAY_SIZE(uart2_3_pins),
1419 .modemuxs = uart2_3_modemux, 1419 .modemuxs = uart2_3_modemux,
1420 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux), 1420 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
1421 }; 1421 };
1422 1422
1423 static const char *const uart2_3_grps[] = { "uart2_3_grp" }; 1423 static const char *const uart2_3_grps[] = { "uart2_3_grp" };
1424 static struct spear_function uart2_3_function = { 1424 static struct spear_function uart2_3_function = {
1425 .name = "uart2_3", 1425 .name = "uart2_3",
1426 .groups = uart2_3_grps, 1426 .groups = uart2_3_grps,
1427 .ngroups = ARRAY_SIZE(uart2_3_grps), 1427 .ngroups = ARRAY_SIZE(uart2_3_grps),
1428 }; 1428 };
1429 1429
1430 /* Pad multiplexing for uart4 device */ 1430 /* Pad multiplexing for uart4 device */
1431 static const unsigned uart4_pins[] = { 108, 113 }; 1431 static const unsigned uart4_pins[] = { 108, 113 };
1432 static struct spear_muxreg uart4_muxreg[] = { 1432 static struct spear_muxreg uart4_muxreg[] = {
1433 { 1433 {
1434 .reg = PAD_FUNCTION_EN_0, 1434 .reg = PAD_FUNCTION_EN_0,
1435 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, 1435 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1436 .val = 0, 1436 .val = 0,
1437 }, { 1437 }, {
1438 .reg = PAD_DIRECTION_SEL_0, 1438 .reg = PAD_DIRECTION_SEL_0,
1439 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, 1439 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1440 .val = PMX_I2S0_MASK | PMX_CLCD1_MASK, 1440 .val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1441 }, 1441 },
1442 }; 1442 };
1443 1443
1444 static struct spear_modemux uart4_modemux[] = { 1444 static struct spear_modemux uart4_modemux[] = {
1445 { 1445 {
1446 .muxregs = uart4_muxreg, 1446 .muxregs = uart4_muxreg,
1447 .nmuxregs = ARRAY_SIZE(uart4_muxreg), 1447 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
1448 }, 1448 },
1449 }; 1449 };
1450 1450
1451 static struct spear_pingroup uart_4_pingroup = { 1451 static struct spear_pingroup uart_4_pingroup = {
1452 .name = "uart4_grp", 1452 .name = "uart4_grp",
1453 .pins = uart4_pins, 1453 .pins = uart4_pins,
1454 .npins = ARRAY_SIZE(uart4_pins), 1454 .npins = ARRAY_SIZE(uart4_pins),
1455 .modemuxs = uart4_modemux, 1455 .modemuxs = uart4_modemux,
1456 .nmodemuxs = ARRAY_SIZE(uart4_modemux), 1456 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
1457 }; 1457 };
1458 1458
1459 static const char *const uart4_grps[] = { "uart4_grp" }; 1459 static const char *const uart4_grps[] = { "uart4_grp" };
1460 static struct spear_function uart4_function = { 1460 static struct spear_function uart4_function = {
1461 .name = "uart4", 1461 .name = "uart4",
1462 .groups = uart4_grps, 1462 .groups = uart4_grps,
1463 .ngroups = ARRAY_SIZE(uart4_grps), 1463 .ngroups = ARRAY_SIZE(uart4_grps),
1464 }; 1464 };
1465 1465
1466 /* Pad multiplexing for uart5 device */ 1466 /* Pad multiplexing for uart5 device */
1467 static const unsigned uart5_pins[] = { 114, 115 }; 1467 static const unsigned uart5_pins[] = { 114, 115 };
1468 static struct spear_muxreg uart5_muxreg[] = { 1468 static struct spear_muxreg uart5_muxreg[] = {
1469 { 1469 {
1470 .reg = PAD_FUNCTION_EN_0, 1470 .reg = PAD_FUNCTION_EN_0,
1471 .mask = PMX_CLCD1_MASK, 1471 .mask = PMX_CLCD1_MASK,
1472 .val = 0, 1472 .val = 0,
1473 }, { 1473 }, {
1474 .reg = PAD_DIRECTION_SEL_0, 1474 .reg = PAD_DIRECTION_SEL_0,
1475 .mask = PMX_CLCD1_MASK, 1475 .mask = PMX_CLCD1_MASK,
1476 .val = PMX_CLCD1_MASK, 1476 .val = PMX_CLCD1_MASK,
1477 }, 1477 },
1478 }; 1478 };
1479 1479
1480 static struct spear_modemux uart5_modemux[] = { 1480 static struct spear_modemux uart5_modemux[] = {
1481 { 1481 {
1482 .muxregs = uart5_muxreg, 1482 .muxregs = uart5_muxreg,
1483 .nmuxregs = ARRAY_SIZE(uart5_muxreg), 1483 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
1484 }, 1484 },
1485 }; 1485 };
1486 1486
1487 static struct spear_pingroup uart_5_pingroup = { 1487 static struct spear_pingroup uart_5_pingroup = {
1488 .name = "uart5_grp", 1488 .name = "uart5_grp",
1489 .pins = uart5_pins, 1489 .pins = uart5_pins,
1490 .npins = ARRAY_SIZE(uart5_pins), 1490 .npins = ARRAY_SIZE(uart5_pins),
1491 .modemuxs = uart5_modemux, 1491 .modemuxs = uart5_modemux,
1492 .nmodemuxs = ARRAY_SIZE(uart5_modemux), 1492 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
1493 }; 1493 };
1494 1494
1495 static const char *const uart5_grps[] = { "uart5_grp" }; 1495 static const char *const uart5_grps[] = { "uart5_grp" };
1496 static struct spear_function uart5_function = { 1496 static struct spear_function uart5_function = {
1497 .name = "uart5", 1497 .name = "uart5",
1498 .groups = uart5_grps, 1498 .groups = uart5_grps,
1499 .ngroups = ARRAY_SIZE(uart5_grps), 1499 .ngroups = ARRAY_SIZE(uart5_grps),
1500 }; 1500 };
1501 1501
1502 /* Pad multiplexing for rs485_0_1_tdm_0_1 device */ 1502 /* Pad multiplexing for rs485_0_1_tdm_0_1 device */
1503 static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121, 1503 static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
1504 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 1504 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
1505 136, 137 }; 1505 136, 137 };
1506 static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = { 1506 static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1507 { 1507 {
1508 .reg = PAD_FUNCTION_EN_0, 1508 .reg = PAD_FUNCTION_EN_0,
1509 .mask = PMX_CLCD1_MASK, 1509 .mask = PMX_CLCD1_MASK,
1510 .val = 0, 1510 .val = 0,
1511 }, { 1511 }, {
1512 .reg = PAD_DIRECTION_SEL_0, 1512 .reg = PAD_DIRECTION_SEL_0,
1513 .mask = PMX_CLCD1_MASK, 1513 .mask = PMX_CLCD1_MASK,
1514 .val = PMX_CLCD1_MASK, 1514 .val = PMX_CLCD1_MASK,
1515 }, 1515 },
1516 }; 1516 };
1517 1517
1518 static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = { 1518 static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
1519 { 1519 {
1520 .muxregs = rs485_0_1_tdm_0_1_muxreg, 1520 .muxregs = rs485_0_1_tdm_0_1_muxreg,
1521 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg), 1521 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
1522 }, 1522 },
1523 }; 1523 };
1524 1524
1525 static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = { 1525 static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
1526 .name = "rs485_0_1_tdm_0_1_grp", 1526 .name = "rs485_0_1_tdm_0_1_grp",
1527 .pins = rs485_0_1_tdm_0_1_pins, 1527 .pins = rs485_0_1_tdm_0_1_pins,
1528 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins), 1528 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
1529 .modemuxs = rs485_0_1_tdm_0_1_modemux, 1529 .modemuxs = rs485_0_1_tdm_0_1_modemux,
1530 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux), 1530 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
1531 }; 1531 };
1532 1532
1533 static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" }; 1533 static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
1534 static struct spear_function rs485_0_1_tdm_0_1_function = { 1534 static struct spear_function rs485_0_1_tdm_0_1_function = {
1535 .name = "rs485_0_1_tdm_0_1", 1535 .name = "rs485_0_1_tdm_0_1",
1536 .groups = rs485_0_1_tdm_0_1_grps, 1536 .groups = rs485_0_1_tdm_0_1_grps,
1537 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps), 1537 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
1538 }; 1538 };
1539 1539
1540 /* Pad multiplexing for i2c_1_2 device */ 1540 /* Pad multiplexing for i2c_1_2 device */
1541 static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 }; 1541 static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
1542 static struct spear_muxreg i2c_1_2_muxreg[] = { 1542 static struct spear_muxreg i2c_1_2_muxreg[] = {
1543 { 1543 {
1544 .reg = PAD_FUNCTION_EN_0, 1544 .reg = PAD_FUNCTION_EN_0,
1545 .mask = PMX_CLCD1_MASK, 1545 .mask = PMX_CLCD1_MASK,
1546 .val = 0, 1546 .val = 0,
1547 }, { 1547 }, {
1548 .reg = PAD_DIRECTION_SEL_0, 1548 .reg = PAD_DIRECTION_SEL_0,
1549 .mask = PMX_CLCD1_MASK, 1549 .mask = PMX_CLCD1_MASK,
1550 .val = PMX_CLCD1_MASK, 1550 .val = PMX_CLCD1_MASK,
1551 }, 1551 },
1552 }; 1552 };
1553 1553
1554 static struct spear_modemux i2c_1_2_modemux[] = { 1554 static struct spear_modemux i2c_1_2_modemux[] = {
1555 { 1555 {
1556 .muxregs = i2c_1_2_muxreg, 1556 .muxregs = i2c_1_2_muxreg,
1557 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg), 1557 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
1558 }, 1558 },
1559 }; 1559 };
1560 1560
1561 static struct spear_pingroup i2c_1_2_pingroup = { 1561 static struct spear_pingroup i2c_1_2_pingroup = {
1562 .name = "i2c_1_2_grp", 1562 .name = "i2c_1_2_grp",
1563 .pins = i2c_1_2_pins, 1563 .pins = i2c_1_2_pins,
1564 .npins = ARRAY_SIZE(i2c_1_2_pins), 1564 .npins = ARRAY_SIZE(i2c_1_2_pins),
1565 .modemuxs = i2c_1_2_modemux, 1565 .modemuxs = i2c_1_2_modemux,
1566 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux), 1566 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
1567 }; 1567 };
1568 1568
1569 static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" }; 1569 static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
1570 static struct spear_function i2c_1_2_function = { 1570 static struct spear_function i2c_1_2_function = {
1571 .name = "i2c_1_2", 1571 .name = "i2c_1_2",
1572 .groups = i2c_1_2_grps, 1572 .groups = i2c_1_2_grps,
1573 .ngroups = ARRAY_SIZE(i2c_1_2_grps), 1573 .ngroups = ARRAY_SIZE(i2c_1_2_grps),
1574 }; 1574 };
1575 1575
1576 /* Pad multiplexing for i2c3_dis_smi_clcd device */ 1576 /* Pad multiplexing for i2c3_dis_smi_clcd device */
1577 /* Muxed with SMI & CLCD */ 1577 /* Muxed with SMI & CLCD */
1578 static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 }; 1578 static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
1579 static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = { 1579 static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1580 { 1580 {
1581 .reg = PAD_FUNCTION_EN_0, 1581 .reg = PAD_FUNCTION_EN_0,
1582 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, 1582 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1583 .val = 0, 1583 .val = 0,
1584 }, { 1584 }, {
1585 .reg = PAD_DIRECTION_SEL_0, 1585 .reg = PAD_DIRECTION_SEL_0,
1586 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, 1586 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1587 .val = PMX_CLCD1_MASK | PMX_SMI_MASK, 1587 .val = PMX_CLCD1_MASK | PMX_SMI_MASK,
1588 }, 1588 },
1589 }; 1589 };
1590 1590
1591 static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = { 1591 static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
1592 { 1592 {
1593 .muxregs = i2c3_dis_smi_clcd_muxreg, 1593 .muxregs = i2c3_dis_smi_clcd_muxreg,
1594 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg), 1594 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
1595 }, 1595 },
1596 }; 1596 };
1597 1597
1598 static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = { 1598 static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
1599 .name = "i2c3_dis_smi_clcd_grp", 1599 .name = "i2c3_dis_smi_clcd_grp",
1600 .pins = i2c3_dis_smi_clcd_pins, 1600 .pins = i2c3_dis_smi_clcd_pins,
1601 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins), 1601 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
1602 .modemuxs = i2c3_dis_smi_clcd_modemux, 1602 .modemuxs = i2c3_dis_smi_clcd_modemux,
1603 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux), 1603 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
1604 }; 1604 };
1605 1605
1606 /* Pad multiplexing for i2c3_dis_sd_i2s0 device */ 1606 /* Pad multiplexing for i2c3_dis_sd_i2s0 device */
1607 /* Muxed with SD/MMC & I2S1 */ 1607 /* Muxed with SD/MMC & I2S1 */
1608 static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 }; 1608 static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
1609 static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = { 1609 static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1610 { 1610 {
1611 .reg = PAD_FUNCTION_EN_1, 1611 .reg = PAD_FUNCTION_EN_1,
1612 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, 1612 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1613 .val = 0, 1613 .val = 0,
1614 }, { 1614 }, {
1615 .reg = PAD_DIRECTION_SEL_1, 1615 .reg = PAD_DIRECTION_SEL_1,
1616 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, 1616 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1617 .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, 1617 .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1618 }, 1618 },
1619 }; 1619 };
1620 1620
1621 static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = { 1621 static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
1622 { 1622 {
1623 .muxregs = i2c3_dis_sd_i2s0_muxreg, 1623 .muxregs = i2c3_dis_sd_i2s0_muxreg,
1624 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg), 1624 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
1625 }, 1625 },
1626 }; 1626 };
1627 1627
1628 static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = { 1628 static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
1629 .name = "i2c3_dis_sd_i2s0_grp", 1629 .name = "i2c3_dis_sd_i2s0_grp",
1630 .pins = i2c3_dis_sd_i2s0_pins, 1630 .pins = i2c3_dis_sd_i2s0_pins,
1631 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins), 1631 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
1632 .modemuxs = i2c3_dis_sd_i2s0_modemux, 1632 .modemuxs = i2c3_dis_sd_i2s0_modemux,
1633 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux), 1633 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
1634 }; 1634 };
1635 1635
1636 static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp", 1636 static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
1637 "i2c3_dis_sd_i2s0_grp" }; 1637 "i2c3_dis_sd_i2s0_grp" };
1638 static struct spear_function i2c3_unction = { 1638 static struct spear_function i2c3_unction = {
1639 .name = "i2c3_i2s1", 1639 .name = "i2c3_i2s1",
1640 .groups = i2c3_grps, 1640 .groups = i2c3_grps,
1641 .ngroups = ARRAY_SIZE(i2c3_grps), 1641 .ngroups = ARRAY_SIZE(i2c3_grps),
1642 }; 1642 };
1643 1643
1644 /* Pad multiplexing for i2c_4_5_dis_smi device */ 1644 /* Pad multiplexing for i2c_4_5_dis_smi device */
1645 /* Muxed with SMI */ 1645 /* Muxed with SMI */
1646 static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 }; 1646 static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
1647 static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = { 1647 static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1648 { 1648 {
1649 .reg = PAD_FUNCTION_EN_0, 1649 .reg = PAD_FUNCTION_EN_0,
1650 .mask = PMX_SMI_MASK, 1650 .mask = PMX_SMI_MASK,
1651 .val = 0, 1651 .val = 0,
1652 }, { 1652 }, {
1653 .reg = PAD_DIRECTION_SEL_0, 1653 .reg = PAD_DIRECTION_SEL_0,
1654 .mask = PMX_SMI_MASK, 1654 .mask = PMX_SMI_MASK,
1655 .val = PMX_SMI_MASK, 1655 .val = PMX_SMI_MASK,
1656 }, 1656 },
1657 }; 1657 };
1658 1658
1659 static struct spear_modemux i2c_4_5_dis_smi_modemux[] = { 1659 static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
1660 { 1660 {
1661 .muxregs = i2c_4_5_dis_smi_muxreg, 1661 .muxregs = i2c_4_5_dis_smi_muxreg,
1662 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg), 1662 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
1663 }, 1663 },
1664 }; 1664 };
1665 1665
1666 static struct spear_pingroup i2c_4_5_dis_smi_pingroup = { 1666 static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
1667 .name = "i2c_4_5_dis_smi_grp", 1667 .name = "i2c_4_5_dis_smi_grp",
1668 .pins = i2c_4_5_dis_smi_pins, 1668 .pins = i2c_4_5_dis_smi_pins,
1669 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins), 1669 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
1670 .modemuxs = i2c_4_5_dis_smi_modemux, 1670 .modemuxs = i2c_4_5_dis_smi_modemux,
1671 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux), 1671 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
1672 }; 1672 };
1673 1673
1674 /* Pad multiplexing for i2c4_dis_sd device */ 1674 /* Pad multiplexing for i2c4_dis_sd device */
1675 /* Muxed with SD/MMC */ 1675 /* Muxed with SD/MMC */
1676 static const unsigned i2c4_dis_sd_pins[] = { 217, 218 }; 1676 static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
1677 static struct spear_muxreg i2c4_dis_sd_muxreg[] = { 1677 static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1678 { 1678 {
1679 .reg = PAD_FUNCTION_EN_1, 1679 .reg = PAD_FUNCTION_EN_1,
1680 .mask = PMX_MCIDATA4_MASK, 1680 .mask = PMX_MCIDATA4_MASK,
1681 .val = 0, 1681 .val = 0,
1682 }, { 1682 }, {
1683 .reg = PAD_FUNCTION_EN_2, 1683 .reg = PAD_FUNCTION_EN_2,
1684 .mask = PMX_MCIDATA5_MASK, 1684 .mask = PMX_MCIDATA5_MASK,
1685 .val = 0, 1685 .val = 0,
1686 }, { 1686 }, {
1687 .reg = PAD_DIRECTION_SEL_1, 1687 .reg = PAD_DIRECTION_SEL_1,
1688 .mask = PMX_MCIDATA4_MASK, 1688 .mask = PMX_MCIDATA4_MASK,
1689 .val = PMX_MCIDATA4_MASK, 1689 .val = PMX_MCIDATA4_MASK,
1690 }, { 1690 }, {
1691 .reg = PAD_DIRECTION_SEL_2, 1691 .reg = PAD_DIRECTION_SEL_2,
1692 .mask = PMX_MCIDATA5_MASK, 1692 .mask = PMX_MCIDATA5_MASK,
1693 .val = PMX_MCIDATA5_MASK, 1693 .val = PMX_MCIDATA5_MASK,
1694 }, 1694 },
1695 }; 1695 };
1696 1696
1697 static struct spear_modemux i2c4_dis_sd_modemux[] = { 1697 static struct spear_modemux i2c4_dis_sd_modemux[] = {
1698 { 1698 {
1699 .muxregs = i2c4_dis_sd_muxreg, 1699 .muxregs = i2c4_dis_sd_muxreg,
1700 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg), 1700 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
1701 }, 1701 },
1702 }; 1702 };
1703 1703
1704 static struct spear_pingroup i2c4_dis_sd_pingroup = { 1704 static struct spear_pingroup i2c4_dis_sd_pingroup = {
1705 .name = "i2c4_dis_sd_grp", 1705 .name = "i2c4_dis_sd_grp",
1706 .pins = i2c4_dis_sd_pins, 1706 .pins = i2c4_dis_sd_pins,
1707 .npins = ARRAY_SIZE(i2c4_dis_sd_pins), 1707 .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
1708 .modemuxs = i2c4_dis_sd_modemux, 1708 .modemuxs = i2c4_dis_sd_modemux,
1709 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux), 1709 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
1710 }; 1710 };
1711 1711
1712 /* Pad multiplexing for i2c5_dis_sd device */ 1712 /* Pad multiplexing for i2c5_dis_sd device */
1713 /* Muxed with SD/MMC */ 1713 /* Muxed with SD/MMC */
1714 static const unsigned i2c5_dis_sd_pins[] = { 219, 220 }; 1714 static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
1715 static struct spear_muxreg i2c5_dis_sd_muxreg[] = { 1715 static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1716 { 1716 {
1717 .reg = PAD_FUNCTION_EN_2, 1717 .reg = PAD_FUNCTION_EN_2,
1718 .mask = PMX_MCIDATA6_MASK | 1718 .mask = PMX_MCIDATA6_MASK |
1719 PMX_MCIDATA7_MASK, 1719 PMX_MCIDATA7_MASK,
1720 .val = 0, 1720 .val = 0,
1721 }, { 1721 }, {
1722 .reg = PAD_DIRECTION_SEL_2, 1722 .reg = PAD_DIRECTION_SEL_2,
1723 .mask = PMX_MCIDATA6_MASK | 1723 .mask = PMX_MCIDATA6_MASK |
1724 PMX_MCIDATA7_MASK, 1724 PMX_MCIDATA7_MASK,
1725 .val = PMX_MCIDATA6_MASK | 1725 .val = PMX_MCIDATA6_MASK |
1726 PMX_MCIDATA7_MASK, 1726 PMX_MCIDATA7_MASK,
1727 }, 1727 },
1728 }; 1728 };
1729 1729
1730 static struct spear_modemux i2c5_dis_sd_modemux[] = { 1730 static struct spear_modemux i2c5_dis_sd_modemux[] = {
1731 { 1731 {
1732 .muxregs = i2c5_dis_sd_muxreg, 1732 .muxregs = i2c5_dis_sd_muxreg,
1733 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg), 1733 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
1734 }, 1734 },
1735 }; 1735 };
1736 1736
1737 static struct spear_pingroup i2c5_dis_sd_pingroup = { 1737 static struct spear_pingroup i2c5_dis_sd_pingroup = {
1738 .name = "i2c5_dis_sd_grp", 1738 .name = "i2c5_dis_sd_grp",
1739 .pins = i2c5_dis_sd_pins, 1739 .pins = i2c5_dis_sd_pins,
1740 .npins = ARRAY_SIZE(i2c5_dis_sd_pins), 1740 .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
1741 .modemuxs = i2c5_dis_sd_modemux, 1741 .modemuxs = i2c5_dis_sd_modemux,
1742 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux), 1742 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
1743 }; 1743 };
1744 1744
1745 static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp", 1745 static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
1746 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" }; 1746 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
1747 static struct spear_function i2c_4_5_function = { 1747 static struct spear_function i2c_4_5_function = {
1748 .name = "i2c_4_5", 1748 .name = "i2c_4_5",
1749 .groups = i2c_4_5_grps, 1749 .groups = i2c_4_5_grps,
1750 .ngroups = ARRAY_SIZE(i2c_4_5_grps), 1750 .ngroups = ARRAY_SIZE(i2c_4_5_grps),
1751 }; 1751 };
1752 1752
1753 /* Pad multiplexing for i2c_6_7_dis_kbd device */ 1753 /* Pad multiplexing for i2c_6_7_dis_kbd device */
1754 /* Muxed with KBD */ 1754 /* Muxed with KBD */
1755 static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 }; 1755 static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
1756 static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = { 1756 static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1757 { 1757 {
1758 .reg = PAD_FUNCTION_EN_1, 1758 .reg = PAD_FUNCTION_EN_1,
1759 .mask = PMX_KBD_ROWCOL25_MASK, 1759 .mask = PMX_KBD_ROWCOL25_MASK,
1760 .val = 0, 1760 .val = 0,
1761 }, { 1761 }, {
1762 .reg = PAD_DIRECTION_SEL_1, 1762 .reg = PAD_DIRECTION_SEL_1,
1763 .mask = PMX_KBD_ROWCOL25_MASK, 1763 .mask = PMX_KBD_ROWCOL25_MASK,
1764 .val = PMX_KBD_ROWCOL25_MASK, 1764 .val = PMX_KBD_ROWCOL25_MASK,
1765 }, 1765 },
1766 }; 1766 };
1767 1767
1768 static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = { 1768 static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
1769 { 1769 {
1770 .muxregs = i2c_6_7_dis_kbd_muxreg, 1770 .muxregs = i2c_6_7_dis_kbd_muxreg,
1771 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg), 1771 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
1772 }, 1772 },
1773 }; 1773 };
1774 1774
1775 static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = { 1775 static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
1776 .name = "i2c_6_7_dis_kbd_grp", 1776 .name = "i2c_6_7_dis_kbd_grp",
1777 .pins = i2c_6_7_dis_kbd_pins, 1777 .pins = i2c_6_7_dis_kbd_pins,
1778 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins), 1778 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
1779 .modemuxs = i2c_6_7_dis_kbd_modemux, 1779 .modemuxs = i2c_6_7_dis_kbd_modemux,
1780 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux), 1780 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
1781 }; 1781 };
1782 1782
1783 /* Pad multiplexing for i2c6_dis_sd device */ 1783 /* Pad multiplexing for i2c6_dis_sd device */
1784 /* Muxed with SD/MMC */ 1784 /* Muxed with SD/MMC */
1785 static const unsigned i2c6_dis_sd_pins[] = { 236, 237 }; 1785 static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
1786 static struct spear_muxreg i2c6_dis_sd_muxreg[] = { 1786 static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1787 { 1787 {
1788 .reg = PAD_FUNCTION_EN_2, 1788 .reg = PAD_FUNCTION_EN_2,
1789 .mask = PMX_MCIIORDRE_MASK | 1789 .mask = PMX_MCIIORDRE_MASK |
1790 PMX_MCIIOWRWE_MASK, 1790 PMX_MCIIOWRWE_MASK,
1791 .val = 0, 1791 .val = 0,
1792 }, { 1792 }, {
1793 .reg = PAD_DIRECTION_SEL_2, 1793 .reg = PAD_DIRECTION_SEL_2,
1794 .mask = PMX_MCIIORDRE_MASK | 1794 .mask = PMX_MCIIORDRE_MASK |
1795 PMX_MCIIOWRWE_MASK, 1795 PMX_MCIIOWRWE_MASK,
1796 .val = PMX_MCIIORDRE_MASK | 1796 .val = PMX_MCIIORDRE_MASK |
1797 PMX_MCIIOWRWE_MASK, 1797 PMX_MCIIOWRWE_MASK,
1798 }, 1798 },
1799 }; 1799 };
1800 1800
1801 static struct spear_modemux i2c6_dis_sd_modemux[] = { 1801 static struct spear_modemux i2c6_dis_sd_modemux[] = {
1802 { 1802 {
1803 .muxregs = i2c6_dis_sd_muxreg, 1803 .muxregs = i2c6_dis_sd_muxreg,
1804 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg), 1804 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
1805 }, 1805 },
1806 }; 1806 };
1807 1807
1808 static struct spear_pingroup i2c6_dis_sd_pingroup = { 1808 static struct spear_pingroup i2c6_dis_sd_pingroup = {
1809 .name = "i2c6_dis_sd_grp", 1809 .name = "i2c6_dis_sd_grp",
1810 .pins = i2c6_dis_sd_pins, 1810 .pins = i2c6_dis_sd_pins,
1811 .npins = ARRAY_SIZE(i2c6_dis_sd_pins), 1811 .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
1812 .modemuxs = i2c6_dis_sd_modemux, 1812 .modemuxs = i2c6_dis_sd_modemux,
1813 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux), 1813 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
1814 }; 1814 };
1815 1815
1816 /* Pad multiplexing for i2c7_dis_sd device */ 1816 /* Pad multiplexing for i2c7_dis_sd device */
1817 static const unsigned i2c7_dis_sd_pins[] = { 238, 239 }; 1817 static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
1818 static struct spear_muxreg i2c7_dis_sd_muxreg[] = { 1818 static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1819 { 1819 {
1820 .reg = PAD_FUNCTION_EN_2, 1820 .reg = PAD_FUNCTION_EN_2,
1821 .mask = PMX_MCIRESETCF_MASK | 1821 .mask = PMX_MCIRESETCF_MASK |
1822 PMX_MCICS0CE_MASK, 1822 PMX_MCICS0CE_MASK,
1823 .val = 0, 1823 .val = 0,
1824 }, { 1824 }, {
1825 .reg = PAD_DIRECTION_SEL_2, 1825 .reg = PAD_DIRECTION_SEL_2,
1826 .mask = PMX_MCIRESETCF_MASK | 1826 .mask = PMX_MCIRESETCF_MASK |
1827 PMX_MCICS0CE_MASK, 1827 PMX_MCICS0CE_MASK,
1828 .val = PMX_MCIRESETCF_MASK | 1828 .val = PMX_MCIRESETCF_MASK |
1829 PMX_MCICS0CE_MASK, 1829 PMX_MCICS0CE_MASK,
1830 }, 1830 },
1831 }; 1831 };
1832 1832
1833 static struct spear_modemux i2c7_dis_sd_modemux[] = { 1833 static struct spear_modemux i2c7_dis_sd_modemux[] = {
1834 { 1834 {
1835 .muxregs = i2c7_dis_sd_muxreg, 1835 .muxregs = i2c7_dis_sd_muxreg,
1836 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg), 1836 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
1837 }, 1837 },
1838 }; 1838 };
1839 1839
1840 static struct spear_pingroup i2c7_dis_sd_pingroup = { 1840 static struct spear_pingroup i2c7_dis_sd_pingroup = {
1841 .name = "i2c7_dis_sd_grp", 1841 .name = "i2c7_dis_sd_grp",
1842 .pins = i2c7_dis_sd_pins, 1842 .pins = i2c7_dis_sd_pins,
1843 .npins = ARRAY_SIZE(i2c7_dis_sd_pins), 1843 .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
1844 .modemuxs = i2c7_dis_sd_modemux, 1844 .modemuxs = i2c7_dis_sd_modemux,
1845 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux), 1845 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
1846 }; 1846 };
1847 1847
1848 static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp", 1848 static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
1849 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" }; 1849 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
1850 static struct spear_function i2c_6_7_function = { 1850 static struct spear_function i2c_6_7_function = {
1851 .name = "i2c_6_7", 1851 .name = "i2c_6_7",
1852 .groups = i2c_6_7_grps, 1852 .groups = i2c_6_7_grps,
1853 .ngroups = ARRAY_SIZE(i2c_6_7_grps), 1853 .ngroups = ARRAY_SIZE(i2c_6_7_grps),
1854 }; 1854 };
1855 1855
1856 /* Pad multiplexing for can0_dis_nor device */ 1856 /* Pad multiplexing for can0_dis_nor device */
1857 /* Muxed with NOR */ 1857 /* Muxed with NOR */
1858 static const unsigned can0_dis_nor_pins[] = { 56, 57 }; 1858 static const unsigned can0_dis_nor_pins[] = { 56, 57 };
1859 static struct spear_muxreg can0_dis_nor_muxreg[] = { 1859 static struct spear_muxreg can0_dis_nor_muxreg[] = {
1860 { 1860 {
1861 .reg = PAD_FUNCTION_EN_0, 1861 .reg = PAD_FUNCTION_EN_0,
1862 .mask = PMX_NFRSTPWDWN2_MASK, 1862 .mask = PMX_NFRSTPWDWN2_MASK,
1863 .val = 0, 1863 .val = 0,
1864 }, { 1864 }, {
1865 .reg = PAD_FUNCTION_EN_1, 1865 .reg = PAD_FUNCTION_EN_1,
1866 .mask = PMX_NFRSTPWDWN3_MASK, 1866 .mask = PMX_NFRSTPWDWN3_MASK,
1867 .val = 0, 1867 .val = 0,
1868 }, { 1868 }, {
1869 .reg = PAD_DIRECTION_SEL_0, 1869 .reg = PAD_DIRECTION_SEL_0,
1870 .mask = PMX_NFRSTPWDWN2_MASK, 1870 .mask = PMX_NFRSTPWDWN2_MASK,
1871 .val = PMX_NFRSTPWDWN2_MASK, 1871 .val = PMX_NFRSTPWDWN2_MASK,
1872 }, { 1872 }, {
1873 .reg = PAD_DIRECTION_SEL_1, 1873 .reg = PAD_DIRECTION_SEL_1,
1874 .mask = PMX_NFRSTPWDWN3_MASK, 1874 .mask = PMX_NFRSTPWDWN3_MASK,
1875 .val = PMX_NFRSTPWDWN3_MASK, 1875 .val = PMX_NFRSTPWDWN3_MASK,
1876 }, 1876 },
1877 }; 1877 };
1878 1878
1879 static struct spear_modemux can0_dis_nor_modemux[] = { 1879 static struct spear_modemux can0_dis_nor_modemux[] = {
1880 { 1880 {
1881 .muxregs = can0_dis_nor_muxreg, 1881 .muxregs = can0_dis_nor_muxreg,
1882 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg), 1882 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
1883 }, 1883 },
1884 }; 1884 };
1885 1885
1886 static struct spear_pingroup can0_dis_nor_pingroup = { 1886 static struct spear_pingroup can0_dis_nor_pingroup = {
1887 .name = "can0_dis_nor_grp", 1887 .name = "can0_dis_nor_grp",
1888 .pins = can0_dis_nor_pins, 1888 .pins = can0_dis_nor_pins,
1889 .npins = ARRAY_SIZE(can0_dis_nor_pins), 1889 .npins = ARRAY_SIZE(can0_dis_nor_pins),
1890 .modemuxs = can0_dis_nor_modemux, 1890 .modemuxs = can0_dis_nor_modemux,
1891 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux), 1891 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
1892 }; 1892 };
1893 1893
1894 /* Pad multiplexing for can0_dis_sd device */ 1894 /* Pad multiplexing for can0_dis_sd device */
1895 /* Muxed with SD/MMC */ 1895 /* Muxed with SD/MMC */
1896 static const unsigned can0_dis_sd_pins[] = { 240, 241 }; 1896 static const unsigned can0_dis_sd_pins[] = { 240, 241 };
1897 static struct spear_muxreg can0_dis_sd_muxreg[] = { 1897 static struct spear_muxreg can0_dis_sd_muxreg[] = {
1898 { 1898 {
1899 .reg = PAD_FUNCTION_EN_2, 1899 .reg = PAD_FUNCTION_EN_2,
1900 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, 1900 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1901 .val = 0, 1901 .val = 0,
1902 }, { 1902 }, {
1903 .reg = PAD_DIRECTION_SEL_2, 1903 .reg = PAD_DIRECTION_SEL_2,
1904 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, 1904 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1905 .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, 1905 .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1906 }, 1906 },
1907 }; 1907 };
1908 1908
1909 static struct spear_modemux can0_dis_sd_modemux[] = { 1909 static struct spear_modemux can0_dis_sd_modemux[] = {
1910 { 1910 {
1911 .muxregs = can0_dis_sd_muxreg, 1911 .muxregs = can0_dis_sd_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg), 1912 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
1913 }, 1913 },
1914 }; 1914 };
1915 1915
1916 static struct spear_pingroup can0_dis_sd_pingroup = { 1916 static struct spear_pingroup can0_dis_sd_pingroup = {
1917 .name = "can0_dis_sd_grp", 1917 .name = "can0_dis_sd_grp",
1918 .pins = can0_dis_sd_pins, 1918 .pins = can0_dis_sd_pins,
1919 .npins = ARRAY_SIZE(can0_dis_sd_pins), 1919 .npins = ARRAY_SIZE(can0_dis_sd_pins),
1920 .modemuxs = can0_dis_sd_modemux, 1920 .modemuxs = can0_dis_sd_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux), 1921 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
1922 }; 1922 };
1923 1923
1924 static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp" 1924 static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
1925 }; 1925 };
1926 static struct spear_function can0_function = { 1926 static struct spear_function can0_function = {
1927 .name = "can0", 1927 .name = "can0",
1928 .groups = can0_grps, 1928 .groups = can0_grps,
1929 .ngroups = ARRAY_SIZE(can0_grps), 1929 .ngroups = ARRAY_SIZE(can0_grps),
1930 }; 1930 };
1931 1931
1932 /* Pad multiplexing for can1_dis_sd device */ 1932 /* Pad multiplexing for can1_dis_sd device */
1933 /* Muxed with SD/MMC */ 1933 /* Muxed with SD/MMC */
1934 static const unsigned can1_dis_sd_pins[] = { 242, 243 }; 1934 static const unsigned can1_dis_sd_pins[] = { 242, 243 };
1935 static struct spear_muxreg can1_dis_sd_muxreg[] = { 1935 static struct spear_muxreg can1_dis_sd_muxreg[] = {
1936 { 1936 {
1937 .reg = PAD_FUNCTION_EN_2, 1937 .reg = PAD_FUNCTION_EN_2,
1938 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, 1938 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1939 .val = 0, 1939 .val = 0,
1940 }, { 1940 }, {
1941 .reg = PAD_DIRECTION_SEL_2, 1941 .reg = PAD_DIRECTION_SEL_2,
1942 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, 1942 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1943 .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, 1943 .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1944 }, 1944 },
1945 }; 1945 };
1946 1946
1947 static struct spear_modemux can1_dis_sd_modemux[] = { 1947 static struct spear_modemux can1_dis_sd_modemux[] = {
1948 { 1948 {
1949 .muxregs = can1_dis_sd_muxreg, 1949 .muxregs = can1_dis_sd_muxreg,
1950 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg), 1950 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
1951 }, 1951 },
1952 }; 1952 };
1953 1953
1954 static struct spear_pingroup can1_dis_sd_pingroup = { 1954 static struct spear_pingroup can1_dis_sd_pingroup = {
1955 .name = "can1_dis_sd_grp", 1955 .name = "can1_dis_sd_grp",
1956 .pins = can1_dis_sd_pins, 1956 .pins = can1_dis_sd_pins,
1957 .npins = ARRAY_SIZE(can1_dis_sd_pins), 1957 .npins = ARRAY_SIZE(can1_dis_sd_pins),
1958 .modemuxs = can1_dis_sd_modemux, 1958 .modemuxs = can1_dis_sd_modemux,
1959 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux), 1959 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
1960 }; 1960 };
1961 1961
1962 /* Pad multiplexing for can1_dis_kbd device */ 1962 /* Pad multiplexing for can1_dis_kbd device */
1963 /* Muxed with KBD */ 1963 /* Muxed with KBD */
1964 static const unsigned can1_dis_kbd_pins[] = { 201, 202 }; 1964 static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
1965 static struct spear_muxreg can1_dis_kbd_muxreg[] = { 1965 static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1966 { 1966 {
1967 .reg = PAD_FUNCTION_EN_1, 1967 .reg = PAD_FUNCTION_EN_1,
1968 .mask = PMX_KBD_ROWCOL25_MASK, 1968 .mask = PMX_KBD_ROWCOL25_MASK,
1969 .val = 0, 1969 .val = 0,
1970 }, { 1970 }, {
1971 .reg = PAD_DIRECTION_SEL_1, 1971 .reg = PAD_DIRECTION_SEL_1,
1972 .mask = PMX_KBD_ROWCOL25_MASK, 1972 .mask = PMX_KBD_ROWCOL25_MASK,
1973 .val = PMX_KBD_ROWCOL25_MASK, 1973 .val = PMX_KBD_ROWCOL25_MASK,
1974 }, 1974 },
1975 }; 1975 };
1976 1976
1977 static struct spear_modemux can1_dis_kbd_modemux[] = { 1977 static struct spear_modemux can1_dis_kbd_modemux[] = {
1978 { 1978 {
1979 .muxregs = can1_dis_kbd_muxreg, 1979 .muxregs = can1_dis_kbd_muxreg,
1980 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg), 1980 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
1981 }, 1981 },
1982 }; 1982 };
1983 1983
1984 static struct spear_pingroup can1_dis_kbd_pingroup = { 1984 static struct spear_pingroup can1_dis_kbd_pingroup = {
1985 .name = "can1_dis_kbd_grp", 1985 .name = "can1_dis_kbd_grp",
1986 .pins = can1_dis_kbd_pins, 1986 .pins = can1_dis_kbd_pins,
1987 .npins = ARRAY_SIZE(can1_dis_kbd_pins), 1987 .npins = ARRAY_SIZE(can1_dis_kbd_pins),
1988 .modemuxs = can1_dis_kbd_modemux, 1988 .modemuxs = can1_dis_kbd_modemux,
1989 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux), 1989 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
1990 }; 1990 };
1991 1991
1992 static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp" 1992 static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
1993 }; 1993 };
1994 static struct spear_function can1_function = { 1994 static struct spear_function can1_function = {
1995 .name = "can1", 1995 .name = "can1",
1996 .groups = can1_grps, 1996 .groups = can1_grps,
1997 .ngroups = ARRAY_SIZE(can1_grps), 1997 .ngroups = ARRAY_SIZE(can1_grps),
1998 }; 1998 };
1999 1999
2000 /* Pad multiplexing for (ras-ip) pci device */ 2000 /* Pad multiplexing for (ras-ip) pci device */
2001 static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18, 2001 static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
2002 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2002 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
2003 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 2003 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
2004 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 }; 2004 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
2005 2005
2006 static struct spear_muxreg pci_muxreg[] = { 2006 static struct spear_muxreg pci_muxreg[] = {
2007 { 2007 {
2008 .reg = PAD_FUNCTION_EN_0, 2008 .reg = PAD_FUNCTION_EN_0,
2009 .mask = PMX_MCI_DATA8_15_MASK, 2009 .mask = PMX_MCI_DATA8_15_MASK,
2010 .val = 0, 2010 .val = 0,
2011 }, { 2011 }, {
2012 .reg = PAD_FUNCTION_EN_1, 2012 .reg = PAD_FUNCTION_EN_1,
2013 .mask = PMX_PCI_REG1_MASK, 2013 .mask = PMX_PCI_REG1_MASK,
2014 .val = 0, 2014 .val = 0,
2015 }, { 2015 }, {
2016 .reg = PAD_FUNCTION_EN_2, 2016 .reg = PAD_FUNCTION_EN_2,
2017 .mask = PMX_PCI_REG2_MASK, 2017 .mask = PMX_PCI_REG2_MASK,
2018 .val = 0, 2018 .val = 0,
2019 }, { 2019 }, {
2020 .reg = PAD_DIRECTION_SEL_0, 2020 .reg = PAD_DIRECTION_SEL_0,
2021 .mask = PMX_MCI_DATA8_15_MASK, 2021 .mask = PMX_MCI_DATA8_15_MASK,
2022 .val = PMX_MCI_DATA8_15_MASK, 2022 .val = PMX_MCI_DATA8_15_MASK,
2023 }, { 2023 }, {
2024 .reg = PAD_DIRECTION_SEL_1, 2024 .reg = PAD_DIRECTION_SEL_1,
2025 .mask = PMX_PCI_REG1_MASK, 2025 .mask = PMX_PCI_REG1_MASK,
2026 .val = PMX_PCI_REG1_MASK, 2026 .val = PMX_PCI_REG1_MASK,
2027 }, { 2027 }, {
2028 .reg = PAD_DIRECTION_SEL_2, 2028 .reg = PAD_DIRECTION_SEL_2,
2029 .mask = PMX_PCI_REG2_MASK, 2029 .mask = PMX_PCI_REG2_MASK,
2030 .val = PMX_PCI_REG2_MASK, 2030 .val = PMX_PCI_REG2_MASK,
2031 }, 2031 },
2032 }; 2032 };
2033 2033
2034 static struct spear_modemux pci_modemux[] = { 2034 static struct spear_modemux pci_modemux[] = {
2035 { 2035 {
2036 .muxregs = pci_muxreg, 2036 .muxregs = pci_muxreg,
2037 .nmuxregs = ARRAY_SIZE(pci_muxreg), 2037 .nmuxregs = ARRAY_SIZE(pci_muxreg),
2038 }, 2038 },
2039 }; 2039 };
2040 2040
2041 static struct spear_pingroup pci_pingroup = { 2041 static struct spear_pingroup pci_pingroup = {
2042 .name = "pci_grp", 2042 .name = "pci_grp",
2043 .pins = pci_pins, 2043 .pins = pci_pins,
2044 .npins = ARRAY_SIZE(pci_pins), 2044 .npins = ARRAY_SIZE(pci_pins),
2045 .modemuxs = pci_modemux, 2045 .modemuxs = pci_modemux,
2046 .nmodemuxs = ARRAY_SIZE(pci_modemux), 2046 .nmodemuxs = ARRAY_SIZE(pci_modemux),
2047 }; 2047 };
2048 2048
2049 static const char *const pci_grps[] = { "pci_grp" }; 2049 static const char *const pci_grps[] = { "pci_grp" };
2050 static struct spear_function pci_function = { 2050 static struct spear_function pci_function = {
2051 .name = "pci", 2051 .name = "pci",
2052 .groups = pci_grps, 2052 .groups = pci_grps,
2053 .ngroups = ARRAY_SIZE(pci_grps), 2053 .ngroups = ARRAY_SIZE(pci_grps),
2054 }; 2054 };
2055 2055
2056 /* pad multiplexing for (fix-part) pcie0 device */ 2056 /* pad multiplexing for (fix-part) pcie0 device */
2057 static struct spear_muxreg pcie0_muxreg[] = { 2057 static struct spear_muxreg pcie0_muxreg[] = {
2058 { 2058 {
2059 .reg = PCIE_SATA_CFG, 2059 .reg = PCIE_SATA_CFG,
2060 .mask = PCIE_CFG_VAL(0), 2060 .mask = PCIE_CFG_VAL(0),
2061 .val = PCIE_CFG_VAL(0), 2061 .val = PCIE_CFG_VAL(0),
2062 }, 2062 },
2063 }; 2063 };
2064 2064
2065 static struct spear_modemux pcie0_modemux[] = { 2065 static struct spear_modemux pcie0_modemux[] = {
2066 { 2066 {
2067 .muxregs = pcie0_muxreg, 2067 .muxregs = pcie0_muxreg,
2068 .nmuxregs = ARRAY_SIZE(pcie0_muxreg), 2068 .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
2069 }, 2069 },
2070 }; 2070 };
2071 2071
2072 static struct spear_pingroup pcie0_pingroup = { 2072 static struct spear_pingroup pcie0_pingroup = {
2073 .name = "pcie0_grp", 2073 .name = "pcie0_grp",
2074 .modemuxs = pcie0_modemux, 2074 .modemuxs = pcie0_modemux,
2075 .nmodemuxs = ARRAY_SIZE(pcie0_modemux), 2075 .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
2076 }; 2076 };
2077 2077
2078 /* pad multiplexing for (fix-part) pcie1 device */ 2078 /* pad multiplexing for (fix-part) pcie1 device */
2079 static struct spear_muxreg pcie1_muxreg[] = { 2079 static struct spear_muxreg pcie1_muxreg[] = {
2080 { 2080 {
2081 .reg = PCIE_SATA_CFG, 2081 .reg = PCIE_SATA_CFG,
2082 .mask = PCIE_CFG_VAL(1), 2082 .mask = PCIE_CFG_VAL(1),
2083 .val = PCIE_CFG_VAL(1), 2083 .val = PCIE_CFG_VAL(1),
2084 }, 2084 },
2085 }; 2085 };
2086 2086
2087 static struct spear_modemux pcie1_modemux[] = { 2087 static struct spear_modemux pcie1_modemux[] = {
2088 { 2088 {
2089 .muxregs = pcie1_muxreg, 2089 .muxregs = pcie1_muxreg,
2090 .nmuxregs = ARRAY_SIZE(pcie1_muxreg), 2090 .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
2091 }, 2091 },
2092 }; 2092 };
2093 2093
2094 static struct spear_pingroup pcie1_pingroup = { 2094 static struct spear_pingroup pcie1_pingroup = {
2095 .name = "pcie1_grp", 2095 .name = "pcie1_grp",
2096 .modemuxs = pcie1_modemux, 2096 .modemuxs = pcie1_modemux,
2097 .nmodemuxs = ARRAY_SIZE(pcie1_modemux), 2097 .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
2098 }; 2098 };
2099 2099
2100 /* pad multiplexing for (fix-part) pcie2 device */ 2100 /* pad multiplexing for (fix-part) pcie2 device */
2101 static struct spear_muxreg pcie2_muxreg[] = { 2101 static struct spear_muxreg pcie2_muxreg[] = {
2102 { 2102 {
2103 .reg = PCIE_SATA_CFG, 2103 .reg = PCIE_SATA_CFG,
2104 .mask = PCIE_CFG_VAL(2), 2104 .mask = PCIE_CFG_VAL(2),
2105 .val = PCIE_CFG_VAL(2), 2105 .val = PCIE_CFG_VAL(2),
2106 }, 2106 },
2107 }; 2107 };
2108 2108
2109 static struct spear_modemux pcie2_modemux[] = { 2109 static struct spear_modemux pcie2_modemux[] = {
2110 { 2110 {
2111 .muxregs = pcie2_muxreg, 2111 .muxregs = pcie2_muxreg,
2112 .nmuxregs = ARRAY_SIZE(pcie2_muxreg), 2112 .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
2113 }, 2113 },
2114 }; 2114 };
2115 2115
2116 static struct spear_pingroup pcie2_pingroup = { 2116 static struct spear_pingroup pcie2_pingroup = {
2117 .name = "pcie2_grp", 2117 .name = "pcie2_grp",
2118 .modemuxs = pcie2_modemux, 2118 .modemuxs = pcie2_modemux,
2119 .nmodemuxs = ARRAY_SIZE(pcie2_modemux), 2119 .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
2120 }; 2120 };
2121 2121
2122 static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" 2122 static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
2123 }; 2123 };
2124 static struct spear_function pcie_function = { 2124 static struct spear_function pcie_function = {
2125 .name = "pci_express", 2125 .name = "pci_express",
2126 .groups = pcie_grps, 2126 .groups = pcie_grps,
2127 .ngroups = ARRAY_SIZE(pcie_grps), 2127 .ngroups = ARRAY_SIZE(pcie_grps),
2128 }; 2128 };
2129 2129
2130 /* pad multiplexing for sata0 device */ 2130 /* pad multiplexing for sata0 device */
2131 static struct spear_muxreg sata0_muxreg[] = { 2131 static struct spear_muxreg sata0_muxreg[] = {
2132 { 2132 {
2133 .reg = PCIE_SATA_CFG, 2133 .reg = PCIE_SATA_CFG,
2134 .mask = SATA_CFG_VAL(0), 2134 .mask = SATA_CFG_VAL(0),
2135 .val = SATA_CFG_VAL(0), 2135 .val = SATA_CFG_VAL(0),
2136 }, 2136 },
2137 }; 2137 };
2138 2138
2139 static struct spear_modemux sata0_modemux[] = { 2139 static struct spear_modemux sata0_modemux[] = {
2140 { 2140 {
2141 .muxregs = sata0_muxreg, 2141 .muxregs = sata0_muxreg,
2142 .nmuxregs = ARRAY_SIZE(sata0_muxreg), 2142 .nmuxregs = ARRAY_SIZE(sata0_muxreg),
2143 }, 2143 },
2144 }; 2144 };
2145 2145
2146 static struct spear_pingroup sata0_pingroup = { 2146 static struct spear_pingroup sata0_pingroup = {
2147 .name = "sata0_grp", 2147 .name = "sata0_grp",
2148 .modemuxs = sata0_modemux, 2148 .modemuxs = sata0_modemux,
2149 .nmodemuxs = ARRAY_SIZE(sata0_modemux), 2149 .nmodemuxs = ARRAY_SIZE(sata0_modemux),
2150 }; 2150 };
2151 2151
2152 /* pad multiplexing for sata1 device */ 2152 /* pad multiplexing for sata1 device */
2153 static struct spear_muxreg sata1_muxreg[] = { 2153 static struct spear_muxreg sata1_muxreg[] = {
2154 { 2154 {
2155 .reg = PCIE_SATA_CFG, 2155 .reg = PCIE_SATA_CFG,
2156 .mask = SATA_CFG_VAL(1), 2156 .mask = SATA_CFG_VAL(1),
2157 .val = SATA_CFG_VAL(1), 2157 .val = SATA_CFG_VAL(1),
2158 }, 2158 },
2159 }; 2159 };
2160 2160
2161 static struct spear_modemux sata1_modemux[] = { 2161 static struct spear_modemux sata1_modemux[] = {
2162 { 2162 {
2163 .muxregs = sata1_muxreg, 2163 .muxregs = sata1_muxreg,
2164 .nmuxregs = ARRAY_SIZE(sata1_muxreg), 2164 .nmuxregs = ARRAY_SIZE(sata1_muxreg),
2165 }, 2165 },
2166 }; 2166 };
2167 2167
2168 static struct spear_pingroup sata1_pingroup = { 2168 static struct spear_pingroup sata1_pingroup = {
2169 .name = "sata1_grp", 2169 .name = "sata1_grp",
2170 .modemuxs = sata1_modemux, 2170 .modemuxs = sata1_modemux,
2171 .nmodemuxs = ARRAY_SIZE(sata1_modemux), 2171 .nmodemuxs = ARRAY_SIZE(sata1_modemux),
2172 }; 2172 };
2173 2173
2174 /* pad multiplexing for sata2 device */ 2174 /* pad multiplexing for sata2 device */
2175 static struct spear_muxreg sata2_muxreg[] = { 2175 static struct spear_muxreg sata2_muxreg[] = {
2176 { 2176 {
2177 .reg = PCIE_SATA_CFG, 2177 .reg = PCIE_SATA_CFG,
2178 .mask = SATA_CFG_VAL(2), 2178 .mask = SATA_CFG_VAL(2),
2179 .val = SATA_CFG_VAL(2), 2179 .val = SATA_CFG_VAL(2),
2180 }, 2180 },
2181 }; 2181 };
2182 2182
2183 static struct spear_modemux sata2_modemux[] = { 2183 static struct spear_modemux sata2_modemux[] = {
2184 { 2184 {
2185 .muxregs = sata2_muxreg, 2185 .muxregs = sata2_muxreg,
2186 .nmuxregs = ARRAY_SIZE(sata2_muxreg), 2186 .nmuxregs = ARRAY_SIZE(sata2_muxreg),
2187 }, 2187 },
2188 }; 2188 };
2189 2189
2190 static struct spear_pingroup sata2_pingroup = { 2190 static struct spear_pingroup sata2_pingroup = {
2191 .name = "sata2_grp", 2191 .name = "sata2_grp",
2192 .modemuxs = sata2_modemux, 2192 .modemuxs = sata2_modemux,
2193 .nmodemuxs = ARRAY_SIZE(sata2_modemux), 2193 .nmodemuxs = ARRAY_SIZE(sata2_modemux),
2194 }; 2194 };
2195 2195
2196 static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp" 2196 static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
2197 }; 2197 };
2198 static struct spear_function sata_function = { 2198 static struct spear_function sata_function = {
2199 .name = "sata", 2199 .name = "sata",
2200 .groups = sata_grps, 2200 .groups = sata_grps,
2201 .ngroups = ARRAY_SIZE(sata_grps), 2201 .ngroups = ARRAY_SIZE(sata_grps),
2202 }; 2202 };
2203 2203
2204 /* Pad multiplexing for ssp1_dis_kbd device */ 2204 /* Pad multiplexing for ssp1_dis_kbd device */
2205 static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 }; 2205 static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
2206 static struct spear_muxreg ssp1_dis_kbd_muxreg[] = { 2206 static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
2207 { 2207 {
2208 .reg = PAD_FUNCTION_EN_1, 2208 .reg = PAD_FUNCTION_EN_1,
2209 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | 2209 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2210 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | 2210 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2211 PMX_NFCE2_MASK, 2211 PMX_NFCE2_MASK,
2212 .val = 0, 2212 .val = 0,
2213 }, { 2213 }, {
2214 .reg = PAD_DIRECTION_SEL_1, 2214 .reg = PAD_DIRECTION_SEL_1,
2215 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | 2215 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2216 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | 2216 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2217 PMX_NFCE2_MASK, 2217 PMX_NFCE2_MASK,
2218 .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | 2218 .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2219 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | 2219 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2220 PMX_NFCE2_MASK, 2220 PMX_NFCE2_MASK,
2221 }, 2221 },
2222 }; 2222 };
2223 2223
2224 static struct spear_modemux ssp1_dis_kbd_modemux[] = { 2224 static struct spear_modemux ssp1_dis_kbd_modemux[] = {
2225 { 2225 {
2226 .muxregs = ssp1_dis_kbd_muxreg, 2226 .muxregs = ssp1_dis_kbd_muxreg,
2227 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg), 2227 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
2228 }, 2228 },
2229 }; 2229 };
2230 2230
2231 static struct spear_pingroup ssp1_dis_kbd_pingroup = { 2231 static struct spear_pingroup ssp1_dis_kbd_pingroup = {
2232 .name = "ssp1_dis_kbd_grp", 2232 .name = "ssp1_dis_kbd_grp",
2233 .pins = ssp1_dis_kbd_pins, 2233 .pins = ssp1_dis_kbd_pins,
2234 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins), 2234 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
2235 .modemuxs = ssp1_dis_kbd_modemux, 2235 .modemuxs = ssp1_dis_kbd_modemux,
2236 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux), 2236 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
2237 }; 2237 };
2238 2238
2239 /* Pad multiplexing for ssp1_dis_sd device */ 2239 /* Pad multiplexing for ssp1_dis_sd device */
2240 static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 }; 2240 static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
2241 static struct spear_muxreg ssp1_dis_sd_muxreg[] = { 2241 static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
2242 { 2242 {
2243 .reg = PAD_FUNCTION_EN_2, 2243 .reg = PAD_FUNCTION_EN_2,
2244 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | 2244 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2245 PMX_MCICECF_MASK | PMX_MCICEXD_MASK, 2245 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2246 .val = 0, 2246 .val = 0,
2247 }, { 2247 }, {
2248 .reg = PAD_DIRECTION_SEL_2, 2248 .reg = PAD_DIRECTION_SEL_2,
2249 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | 2249 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2250 PMX_MCICECF_MASK | PMX_MCICEXD_MASK, 2250 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2251 .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | 2251 .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2252 PMX_MCICECF_MASK | PMX_MCICEXD_MASK, 2252 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2253 }, 2253 },
2254 }; 2254 };
2255 2255
2256 static struct spear_modemux ssp1_dis_sd_modemux[] = { 2256 static struct spear_modemux ssp1_dis_sd_modemux[] = {
2257 { 2257 {
2258 .muxregs = ssp1_dis_sd_muxreg, 2258 .muxregs = ssp1_dis_sd_muxreg,
2259 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg), 2259 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
2260 }, 2260 },
2261 }; 2261 };
2262 2262
2263 static struct spear_pingroup ssp1_dis_sd_pingroup = { 2263 static struct spear_pingroup ssp1_dis_sd_pingroup = {
2264 .name = "ssp1_dis_sd_grp", 2264 .name = "ssp1_dis_sd_grp",
2265 .pins = ssp1_dis_sd_pins, 2265 .pins = ssp1_dis_sd_pins,
2266 .npins = ARRAY_SIZE(ssp1_dis_sd_pins), 2266 .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
2267 .modemuxs = ssp1_dis_sd_modemux, 2267 .modemuxs = ssp1_dis_sd_modemux,
2268 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux), 2268 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
2269 }; 2269 };
2270 2270
2271 static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp", 2271 static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
2272 "ssp1_dis_sd_grp" }; 2272 "ssp1_dis_sd_grp" };
2273 static struct spear_function ssp1_function = { 2273 static struct spear_function ssp1_function = {
2274 .name = "ssp1", 2274 .name = "ssp1",
2275 .groups = ssp1_grps, 2275 .groups = ssp1_grps,
2276 .ngroups = ARRAY_SIZE(ssp1_grps), 2276 .ngroups = ARRAY_SIZE(ssp1_grps),
2277 }; 2277 };
2278 2278
2279 /* Pad multiplexing for gpt64 device */ 2279 /* Pad multiplexing for gpt64 device */
2280 static const unsigned gpt64_pins[] = { 230, 231, 232, 245 }; 2280 static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
2281 static struct spear_muxreg gpt64_muxreg[] = { 2281 static struct spear_muxreg gpt64_muxreg[] = {
2282 { 2282 {
2283 .reg = PAD_FUNCTION_EN_2, 2283 .reg = PAD_FUNCTION_EN_2,
2284 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK 2284 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2285 | PMX_MCILEDS_MASK, 2285 | PMX_MCILEDS_MASK,
2286 .val = 0, 2286 .val = 0,
2287 }, { 2287 }, {
2288 .reg = PAD_DIRECTION_SEL_2, 2288 .reg = PAD_DIRECTION_SEL_2,
2289 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK 2289 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2290 | PMX_MCILEDS_MASK, 2290 | PMX_MCILEDS_MASK,
2291 .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK 2291 .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2292 | PMX_MCILEDS_MASK, 2292 | PMX_MCILEDS_MASK,
2293 }, 2293 },
2294 }; 2294 };
2295 2295
2296 static struct spear_modemux gpt64_modemux[] = { 2296 static struct spear_modemux gpt64_modemux[] = {
2297 { 2297 {
2298 .muxregs = gpt64_muxreg, 2298 .muxregs = gpt64_muxreg,
2299 .nmuxregs = ARRAY_SIZE(gpt64_muxreg), 2299 .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
2300 }, 2300 },
2301 }; 2301 };
2302 2302
2303 static struct spear_pingroup gpt64_pingroup = { 2303 static struct spear_pingroup gpt64_pingroup = {
2304 .name = "gpt64_grp", 2304 .name = "gpt64_grp",
2305 .pins = gpt64_pins, 2305 .pins = gpt64_pins,
2306 .npins = ARRAY_SIZE(gpt64_pins), 2306 .npins = ARRAY_SIZE(gpt64_pins),
2307 .modemuxs = gpt64_modemux, 2307 .modemuxs = gpt64_modemux,
2308 .nmodemuxs = ARRAY_SIZE(gpt64_modemux), 2308 .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
2309 }; 2309 };
2310 2310
2311 static const char *const gpt64_grps[] = { "gpt64_grp" }; 2311 static const char *const gpt64_grps[] = { "gpt64_grp" };
2312 static struct spear_function gpt64_function = { 2312 static struct spear_function gpt64_function = {
2313 .name = "gpt64", 2313 .name = "gpt64",
2314 .groups = gpt64_grps, 2314 .groups = gpt64_grps,
2315 .ngroups = ARRAY_SIZE(gpt64_grps), 2315 .ngroups = ARRAY_SIZE(gpt64_grps),
2316 }; 2316 };
2317 2317
2318 /* pingroups */ 2318 /* pingroups */
2319 static struct spear_pingroup *spear1310_pingroups[] = { 2319 static struct spear_pingroup *spear1310_pingroups[] = {
2320 &i2c0_pingroup, 2320 &i2c0_pingroup,
2321 &ssp0_pingroup, 2321 &ssp0_pingroup,
2322 &i2s0_pingroup, 2322 &i2s0_pingroup,
2323 &i2s1_pingroup, 2323 &i2s1_pingroup,
2324 &clcd_pingroup, 2324 &clcd_pingroup,
2325 &clcd_high_res_pingroup, 2325 &clcd_high_res_pingroup,
2326 &arm_gpio_pingroup, 2326 &arm_gpio_pingroup,
2327 &smi_2_chips_pingroup, 2327 &smi_2_chips_pingroup,
2328 &smi_4_chips_pingroup, 2328 &smi_4_chips_pingroup,
2329 &gmii_pingroup, 2329 &gmii_pingroup,
2330 &rgmii_pingroup, 2330 &rgmii_pingroup,
2331 &smii_0_1_2_pingroup, 2331 &smii_0_1_2_pingroup,
2332 &ras_mii_txclk_pingroup, 2332 &ras_mii_txclk_pingroup,
2333 &nand_8bit_pingroup, 2333 &nand_8bit_pingroup,
2334 &nand_16bit_pingroup, 2334 &nand_16bit_pingroup,
2335 &nand_4_chips_pingroup, 2335 &nand_4_chips_pingroup,
2336 &keyboard_6x6_pingroup, 2336 &keyboard_6x6_pingroup,
2337 &keyboard_rowcol6_8_pingroup, 2337 &keyboard_rowcol6_8_pingroup,
2338 &uart0_pingroup, 2338 &uart0_pingroup,
2339 &uart0_modem_pingroup, 2339 &uart0_modem_pingroup,
2340 &gpt0_tmr0_pingroup, 2340 &gpt0_tmr0_pingroup,
2341 &gpt0_tmr1_pingroup, 2341 &gpt0_tmr1_pingroup,
2342 &gpt1_tmr0_pingroup, 2342 &gpt1_tmr0_pingroup,
2343 &gpt1_tmr1_pingroup, 2343 &gpt1_tmr1_pingroup,
2344 &sdhci_pingroup, 2344 &sdhci_pingroup,
2345 &cf_pingroup, 2345 &cf_pingroup,
2346 &xd_pingroup, 2346 &xd_pingroup,
2347 &touch_xy_pingroup, 2347 &touch_xy_pingroup,
2348 &ssp0_cs0_pingroup, 2348 &ssp0_cs0_pingroup,
2349 &ssp0_cs1_2_pingroup, 2349 &ssp0_cs1_2_pingroup,
2350 &uart_1_dis_i2c_pingroup, 2350 &uart_1_dis_i2c_pingroup,
2351 &uart_1_dis_sd_pingroup, 2351 &uart_1_dis_sd_pingroup,
2352 &uart_2_3_pingroup, 2352 &uart_2_3_pingroup,
2353 &uart_4_pingroup, 2353 &uart_4_pingroup,
2354 &uart_5_pingroup, 2354 &uart_5_pingroup,
2355 &rs485_0_1_tdm_0_1_pingroup, 2355 &rs485_0_1_tdm_0_1_pingroup,
2356 &i2c_1_2_pingroup, 2356 &i2c_1_2_pingroup,
2357 &i2c3_dis_smi_clcd_pingroup, 2357 &i2c3_dis_smi_clcd_pingroup,
2358 &i2c3_dis_sd_i2s0_pingroup, 2358 &i2c3_dis_sd_i2s0_pingroup,
2359 &i2c_4_5_dis_smi_pingroup, 2359 &i2c_4_5_dis_smi_pingroup,
2360 &i2c4_dis_sd_pingroup, 2360 &i2c4_dis_sd_pingroup,
2361 &i2c5_dis_sd_pingroup, 2361 &i2c5_dis_sd_pingroup,
2362 &i2c_6_7_dis_kbd_pingroup, 2362 &i2c_6_7_dis_kbd_pingroup,
2363 &i2c6_dis_sd_pingroup, 2363 &i2c6_dis_sd_pingroup,
2364 &i2c7_dis_sd_pingroup, 2364 &i2c7_dis_sd_pingroup,
2365 &can0_dis_nor_pingroup, 2365 &can0_dis_nor_pingroup,
2366 &can0_dis_sd_pingroup, 2366 &can0_dis_sd_pingroup,
2367 &can1_dis_sd_pingroup, 2367 &can1_dis_sd_pingroup,
2368 &can1_dis_kbd_pingroup, 2368 &can1_dis_kbd_pingroup,
2369 &pci_pingroup, 2369 &pci_pingroup,
2370 &pcie0_pingroup, 2370 &pcie0_pingroup,
2371 &pcie1_pingroup, 2371 &pcie1_pingroup,
2372 &pcie2_pingroup, 2372 &pcie2_pingroup,
2373 &sata0_pingroup, 2373 &sata0_pingroup,
2374 &sata1_pingroup, 2374 &sata1_pingroup,
2375 &sata2_pingroup, 2375 &sata2_pingroup,
2376 &ssp1_dis_kbd_pingroup, 2376 &ssp1_dis_kbd_pingroup,
2377 &ssp1_dis_sd_pingroup, 2377 &ssp1_dis_sd_pingroup,
2378 &gpt64_pingroup, 2378 &gpt64_pingroup,
2379 }; 2379 };
2380 2380
2381 /* functions */ 2381 /* functions */
2382 static struct spear_function *spear1310_functions[] = { 2382 static struct spear_function *spear1310_functions[] = {
2383 &i2c0_function, 2383 &i2c0_function,
2384 &ssp0_function, 2384 &ssp0_function,
2385 &i2s0_function, 2385 &i2s0_function,
2386 &i2s1_function, 2386 &i2s1_function,
2387 &clcd_function, 2387 &clcd_function,
2388 &arm_gpio_function, 2388 &arm_gpio_function,
2389 &smi_function, 2389 &smi_function,
2390 &gmii_function, 2390 &gmii_function,
2391 &rgmii_function, 2391 &rgmii_function,
2392 &smii_0_1_2_function, 2392 &smii_0_1_2_function,
2393 &ras_mii_txclk_function, 2393 &ras_mii_txclk_function,
2394 &nand_function, 2394 &nand_function,
2395 &keyboard_function, 2395 &keyboard_function,
2396 &uart0_function, 2396 &uart0_function,
2397 &gpt0_function, 2397 &gpt0_function,
2398 &gpt1_function, 2398 &gpt1_function,
2399 &sdhci_function, 2399 &sdhci_function,
2400 &cf_function, 2400 &cf_function,
2401 &xd_function, 2401 &xd_function,
2402 &touch_xy_function, 2402 &touch_xy_function,
2403 &uart1_function, 2403 &uart1_function,
2404 &uart2_3_function, 2404 &uart2_3_function,
2405 &uart4_function, 2405 &uart4_function,
2406 &uart5_function, 2406 &uart5_function,
2407 &rs485_0_1_tdm_0_1_function, 2407 &rs485_0_1_tdm_0_1_function,
2408 &i2c_1_2_function, 2408 &i2c_1_2_function,
2409 &i2c3_unction, 2409 &i2c3_unction,
2410 &i2c_4_5_function, 2410 &i2c_4_5_function,
2411 &i2c_6_7_function, 2411 &i2c_6_7_function,
2412 &can0_function, 2412 &can0_function,
2413 &can1_function, 2413 &can1_function,
2414 &pci_function, 2414 &pci_function,
2415 &pcie_function, 2415 &pcie_function,
2416 &sata_function, 2416 &sata_function,
2417 &ssp1_function, 2417 &ssp1_function,
2418 &gpt64_function, 2418 &gpt64_function,
2419 }; 2419 };
2420 2420
2421 static const unsigned pin18[] = { 18, };
2422 static const unsigned pin19[] = { 19, };
2423 static const unsigned pin20[] = { 20, };
2424 static const unsigned pin21[] = { 21, };
2425 static const unsigned pin22[] = { 22, };
2426 static const unsigned pin23[] = { 23, };
2427 static const unsigned pin54[] = { 54, };
2428 static const unsigned pin55[] = { 55, };
2429 static const unsigned pin56[] = { 56, };
2430 static const unsigned pin57[] = { 57, };
2431 static const unsigned pin58[] = { 58, };
2432 static const unsigned pin59[] = { 59, };
2433 static const unsigned pin60[] = { 60, };
2434 static const unsigned pin61[] = { 61, };
2435 static const unsigned pin62[] = { 62, };
2436 static const unsigned pin63[] = { 63, };
2437 static const unsigned pin143[] = { 143, };
2438 static const unsigned pin144[] = { 144, };
2439 static const unsigned pin145[] = { 145, };
2440 static const unsigned pin146[] = { 146, };
2441 static const unsigned pin147[] = { 147, };
2442 static const unsigned pin148[] = { 148, };
2443 static const unsigned pin149[] = { 149, };
2444 static const unsigned pin150[] = { 150, };
2445 static const unsigned pin151[] = { 151, };
2446 static const unsigned pin152[] = { 152, };
2447 static const unsigned pin205[] = { 205, };
2448 static const unsigned pin206[] = { 206, };
2449 static const unsigned pin211[] = { 211, };
2450 static const unsigned pin212[] = { 212, };
2451 static const unsigned pin213[] = { 213, };
2452 static const unsigned pin214[] = { 214, };
2453 static const unsigned pin215[] = { 215, };
2454 static const unsigned pin216[] = { 216, };
2455 static const unsigned pin217[] = { 217, };
2456 static const unsigned pin218[] = { 218, };
2457 static const unsigned pin219[] = { 219, };
2458 static const unsigned pin220[] = { 220, };
2459 static const unsigned pin221[] = { 221, };
2460 static const unsigned pin222[] = { 222, };
2461 static const unsigned pin223[] = { 223, };
2462 static const unsigned pin224[] = { 224, };
2463 static const unsigned pin225[] = { 225, };
2464 static const unsigned pin226[] = { 226, };
2465 static const unsigned pin227[] = { 227, };
2466 static const unsigned pin228[] = { 228, };
2467 static const unsigned pin229[] = { 229, };
2468 static const unsigned pin230[] = { 230, };
2469 static const unsigned pin231[] = { 231, };
2470 static const unsigned pin232[] = { 232, };
2471 static const unsigned pin233[] = { 233, };
2472 static const unsigned pin234[] = { 234, };
2473 static const unsigned pin235[] = { 235, };
2474 static const unsigned pin236[] = { 236, };
2475 static const unsigned pin237[] = { 237, };
2476 static const unsigned pin238[] = { 238, };
2477 static const unsigned pin239[] = { 239, };
2478 static const unsigned pin240[] = { 240, };
2479 static const unsigned pin241[] = { 241, };
2480 static const unsigned pin242[] = { 242, };
2481 static const unsigned pin243[] = { 243, };
2482 static const unsigned pin244[] = { 244, };
2483 static const unsigned pin245[] = { 245, };
2484
2485 static const unsigned pin_grp0[] = { 173, 174, };
2486 static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };
2487 static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,
2488 190, 191, 192, };
2489 static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };
2490 static const unsigned pin_grp4[] = { 199, 200, };
2491 static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
2492 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
2493 static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };
2494 static const unsigned pin_grp7[] = { 98, 99, };
2495 static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,
2496 166, 167, 168, 169, 170, 171, 172, };
2497
2498 /* Define muxreg arrays */
2499 DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);
2500 DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);
2501 DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);
2502 DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);
2503 DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);
2504 DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);
2505 DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);
2506 DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);
2507 DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);
2508 DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);
2509 DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);
2510 DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);
2511 DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);
2512 DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);
2513 DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);
2514 DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);
2515 DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);
2516 DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);
2517 DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);
2518 DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);
2519 DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);
2520 DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);
2521 DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);
2522 DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);
2523 DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);
2524 DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);
2525 DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);
2526 DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);
2527 DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);
2528 DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);
2529 DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);
2530 DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);
2531 DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);
2532 DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);
2533 DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);
2534 DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);
2535 DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);
2536 DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);
2537 DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);
2538 DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);
2539 DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);
2540 DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);
2541 DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);
2542 DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);
2543 DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);
2544 DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);
2545 DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);
2546 DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);
2547 DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);
2548 DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);
2549 DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);
2550 DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);
2551 DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);
2552 DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);
2553 DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);
2554 DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);
2555 DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);
2556 DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);
2557 DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);
2558 DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);
2559 DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);
2560 DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);
2561 DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);
2562 DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);
2563 DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);
2564 DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);
2565 DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);
2566 DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);
2567 DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);
2568 DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);
2569 DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);
2570 DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);
2571 DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);
2572 DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);
2573 DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);
2574 DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);
2575 DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);
2576 DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);
2577 DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);
2578 DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);
2579 DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);
2580 DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);
2581 DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);
2582 DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);
2583 DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);
2584 DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);
2585 DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);
2586 DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);
2587 DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);
2588 DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);
2589
2590 static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {
2591 GPIO_PINGROUP(i2c0_pins),
2592 GPIO_PINGROUP(ssp0_pins),
2593 GPIO_PINGROUP(ssp0_cs0_pins),
2594 GPIO_PINGROUP(ssp0_cs1_2_pins),
2595 GPIO_PINGROUP(i2s0_pins),
2596 GPIO_PINGROUP(i2s1_pins),
2597 GPIO_PINGROUP(clcd_pins),
2598 GPIO_PINGROUP(clcd_high_res_pins),
2599 GPIO_PINGROUP(pin18),
2600 GPIO_PINGROUP(pin19),
2601 GPIO_PINGROUP(pin20),
2602 GPIO_PINGROUP(pin21),
2603 GPIO_PINGROUP(pin22),
2604 GPIO_PINGROUP(pin23),
2605 GPIO_PINGROUP(pin143),
2606 GPIO_PINGROUP(pin144),
2607 GPIO_PINGROUP(pin145),
2608 GPIO_PINGROUP(pin146),
2609 GPIO_PINGROUP(pin147),
2610 GPIO_PINGROUP(pin148),
2611 GPIO_PINGROUP(pin149),
2612 GPIO_PINGROUP(pin150),
2613 GPIO_PINGROUP(pin151),
2614 GPIO_PINGROUP(pin152),
2615 GPIO_PINGROUP(smi_2_chips_pins),
2616 GPIO_PINGROUP(pin54),
2617 GPIO_PINGROUP(pin55),
2618 GPIO_PINGROUP(pin56),
2619 GPIO_PINGROUP(pin57),
2620 GPIO_PINGROUP(pin58),
2621 GPIO_PINGROUP(pin59),
2622 GPIO_PINGROUP(pin60),
2623 GPIO_PINGROUP(pin61),
2624 GPIO_PINGROUP(pin62),
2625 GPIO_PINGROUP(pin63),
2626 GPIO_PINGROUP(pin_grp0),
2627 GPIO_PINGROUP(pin_grp1),
2628 GPIO_PINGROUP(pin_grp2),
2629 GPIO_PINGROUP(pin_grp3),
2630 GPIO_PINGROUP(pin_grp4),
2631 GPIO_PINGROUP(pin_grp5),
2632 GPIO_PINGROUP(pin_grp6),
2633 GPIO_PINGROUP(pin_grp7),
2634 GPIO_PINGROUP(pin_grp8),
2635 GPIO_PINGROUP(nand_16bit_pins),
2636 GPIO_PINGROUP(pin205),
2637 GPIO_PINGROUP(pin206),
2638 GPIO_PINGROUP(pin211),
2639 GPIO_PINGROUP(pin212),
2640 GPIO_PINGROUP(pin213),
2641 GPIO_PINGROUP(pin214),
2642 GPIO_PINGROUP(pin215),
2643 GPIO_PINGROUP(pin216),
2644 GPIO_PINGROUP(pin217),
2645 GPIO_PINGROUP(pin218),
2646 GPIO_PINGROUP(pin219),
2647 GPIO_PINGROUP(pin220),
2648 GPIO_PINGROUP(pin221),
2649 GPIO_PINGROUP(pin222),
2650 GPIO_PINGROUP(pin223),
2651 GPIO_PINGROUP(pin224),
2652 GPIO_PINGROUP(pin225),
2653 GPIO_PINGROUP(pin226),
2654 GPIO_PINGROUP(pin227),
2655 GPIO_PINGROUP(pin228),
2656 GPIO_PINGROUP(pin229),
2657 GPIO_PINGROUP(pin230),
2658 GPIO_PINGROUP(pin231),
2659 GPIO_PINGROUP(pin232),
2660 GPIO_PINGROUP(pin233),
2661 GPIO_PINGROUP(pin234),
2662 GPIO_PINGROUP(pin235),
2663 GPIO_PINGROUP(pin236),
2664 GPIO_PINGROUP(pin237),
2665 GPIO_PINGROUP(pin238),
2666 GPIO_PINGROUP(pin239),
2667 GPIO_PINGROUP(pin240),
2668 GPIO_PINGROUP(pin241),
2669 GPIO_PINGROUP(pin242),
2670 GPIO_PINGROUP(pin243),
2671 GPIO_PINGROUP(pin244),
2672 GPIO_PINGROUP(pin245),
2673 GPIO_PINGROUP(keyboard_rowcol6_8_pins),
2674 GPIO_PINGROUP(uart0_pins),
2675 GPIO_PINGROUP(uart0_modem_pins),
2676 GPIO_PINGROUP(gpt0_tmr0_pins),
2677 GPIO_PINGROUP(gpt0_tmr1_pins),
2678 GPIO_PINGROUP(gpt1_tmr0_pins),
2679 GPIO_PINGROUP(gpt1_tmr1_pins),
2680 GPIO_PINGROUP(touch_xy_pins),
2681 };
2682
2421 static struct spear_pinctrl_machdata spear1310_machdata = { 2683 static struct spear_pinctrl_machdata spear1310_machdata = {
2422 .pins = spear1310_pins, 2684 .pins = spear1310_pins,
2423 .npins = ARRAY_SIZE(spear1310_pins), 2685 .npins = ARRAY_SIZE(spear1310_pins),
2424 .groups = spear1310_pingroups, 2686 .groups = spear1310_pingroups,
2425 .ngroups = ARRAY_SIZE(spear1310_pingroups), 2687 .ngroups = ARRAY_SIZE(spear1310_pingroups),
2426 .functions = spear1310_functions, 2688 .functions = spear1310_functions,
2427 .nfunctions = ARRAY_SIZE(spear1310_functions), 2689 .nfunctions = ARRAY_SIZE(spear1310_functions),
2690 .gpio_pingroups = spear1310_gpio_pingroup,
2691 .ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),
2428 .modes_supported = false, 2692 .modes_supported = false,
2429 }; 2693 };
2430 2694
2431 static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = { 2695 static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = {
2432 { 2696 {
2433 .compatible = "st,spear1310-pinmux", 2697 .compatible = "st,spear1310-pinmux",
2434 }, 2698 },
2435 {}, 2699 {},
2436 }; 2700 };
2437 2701
2438 static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev) 2702 static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
2439 { 2703 {
2440 return spear_pinctrl_probe(pdev, &spear1310_machdata); 2704 return spear_pinctrl_probe(pdev, &spear1310_machdata);
2441 } 2705 }
2442 2706
2443 static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev) 2707 static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev)
2444 { 2708 {
2445 return spear_pinctrl_remove(pdev); 2709 return spear_pinctrl_remove(pdev);
2446 } 2710 }
2447 2711
2448 static struct platform_driver spear1310_pinctrl_driver = { 2712 static struct platform_driver spear1310_pinctrl_driver = {
2449 .driver = { 2713 .driver = {
2450 .name = DRIVER_NAME, 2714 .name = DRIVER_NAME,
2451 .owner = THIS_MODULE, 2715 .owner = THIS_MODULE,
2452 .of_match_table = spear1310_pinctrl_of_match, 2716 .of_match_table = spear1310_pinctrl_of_match,
2453 }, 2717 },
2454 .probe = spear1310_pinctrl_probe, 2718 .probe = spear1310_pinctrl_probe,
2455 .remove = __devexit_p(spear1310_pinctrl_remove), 2719 .remove = __devexit_p(spear1310_pinctrl_remove),
2456 }; 2720 };
2457 2721
2458 static int __init spear1310_pinctrl_init(void) 2722 static int __init spear1310_pinctrl_init(void)
2459 { 2723 {
2460 return platform_driver_register(&spear1310_pinctrl_driver); 2724 return platform_driver_register(&spear1310_pinctrl_driver);
2461 } 2725 }
2462 arch_initcall(spear1310_pinctrl_init); 2726 arch_initcall(spear1310_pinctrl_init);
2463 2727
2464 static void __exit spear1310_pinctrl_exit(void) 2728 static void __exit spear1310_pinctrl_exit(void)
2465 { 2729 {
2466 platform_driver_unregister(&spear1310_pinctrl_driver); 2730 platform_driver_unregister(&spear1310_pinctrl_driver);
2467 } 2731 }
2468 module_exit(spear1310_pinctrl_exit); 2732 module_exit(spear1310_pinctrl_exit);
2469 2733
2470 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 2734 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
2471 MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver"); 2735 MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
2472 MODULE_LICENSE("GPL v2"); 2736 MODULE_LICENSE("GPL v2");
2473 MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match); 2737 MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
2474 2738
drivers/pinctrl/spear/pinctrl-spear300.c
Diff comments   View file @ f4f8e56
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr300 pinmux 2 * Driver for the ST Microelectronics SPEAr300 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear3xx.h" 17 #include "pinctrl-spear3xx.h"
18 18
19 #define DRIVER_NAME "spear300-pinmux" 19 #define DRIVER_NAME "spear300-pinmux"
20 20
21 /* addresses */ 21 /* addresses */
22 #define PMX_CONFIG_REG 0x00 22 #define PMX_CONFIG_REG 0x00
23 #define MODE_CONFIG_REG 0x04 23 #define MODE_CONFIG_REG 0x04
24 24
25 /* modes */ 25 /* modes */
26 #define NAND_MODE (1 << 0) 26 #define NAND_MODE (1 << 0)
27 #define NOR_MODE (1 << 1) 27 #define NOR_MODE (1 << 1)
28 #define PHOTO_FRAME_MODE (1 << 2) 28 #define PHOTO_FRAME_MODE (1 << 2)
29 #define LEND_IP_PHONE_MODE (1 << 3) 29 #define LEND_IP_PHONE_MODE (1 << 3)
30 #define HEND_IP_PHONE_MODE (1 << 4) 30 #define HEND_IP_PHONE_MODE (1 << 4)
31 #define LEND_WIFI_PHONE_MODE (1 << 5) 31 #define LEND_WIFI_PHONE_MODE (1 << 5)
32 #define HEND_WIFI_PHONE_MODE (1 << 6) 32 #define HEND_WIFI_PHONE_MODE (1 << 6)
33 #define ATA_PABX_WI2S_MODE (1 << 7) 33 #define ATA_PABX_WI2S_MODE (1 << 7)
34 #define ATA_PABX_I2S_MODE (1 << 8) 34 #define ATA_PABX_I2S_MODE (1 << 8)
35 #define CAML_LCDW_MODE (1 << 9) 35 #define CAML_LCDW_MODE (1 << 9)
36 #define CAMU_LCD_MODE (1 << 10) 36 #define CAMU_LCD_MODE (1 << 10)
37 #define CAMU_WLCD_MODE (1 << 11) 37 #define CAMU_WLCD_MODE (1 << 11)
38 #define CAML_LCD_MODE (1 << 12) 38 #define CAML_LCD_MODE (1 << 12)
39 39
40 static struct spear_pmx_mode pmx_mode_nand = { 40 static struct spear_pmx_mode pmx_mode_nand = {
41 .name = "nand", 41 .name = "nand",
42 .mode = NAND_MODE, 42 .mode = NAND_MODE,
43 .reg = MODE_CONFIG_REG, 43 .reg = MODE_CONFIG_REG,
44 .mask = 0x0000000F, 44 .mask = 0x0000000F,
45 .val = 0x00, 45 .val = 0x00,
46 }; 46 };
47 47
48 static struct spear_pmx_mode pmx_mode_nor = { 48 static struct spear_pmx_mode pmx_mode_nor = {
49 .name = "nor", 49 .name = "nor",
50 .mode = NOR_MODE, 50 .mode = NOR_MODE,
51 .reg = MODE_CONFIG_REG, 51 .reg = MODE_CONFIG_REG,
52 .mask = 0x0000000F, 52 .mask = 0x0000000F,
53 .val = 0x01, 53 .val = 0x01,
54 }; 54 };
55 55
56 static struct spear_pmx_mode pmx_mode_photo_frame = { 56 static struct spear_pmx_mode pmx_mode_photo_frame = {
57 .name = "photo frame mode", 57 .name = "photo frame mode",
58 .mode = PHOTO_FRAME_MODE, 58 .mode = PHOTO_FRAME_MODE,
59 .reg = MODE_CONFIG_REG, 59 .reg = MODE_CONFIG_REG,
60 .mask = 0x0000000F, 60 .mask = 0x0000000F,
61 .val = 0x02, 61 .val = 0x02,
62 }; 62 };
63 63
64 static struct spear_pmx_mode pmx_mode_lend_ip_phone = { 64 static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
65 .name = "lend ip phone mode", 65 .name = "lend ip phone mode",
66 .mode = LEND_IP_PHONE_MODE, 66 .mode = LEND_IP_PHONE_MODE,
67 .reg = MODE_CONFIG_REG, 67 .reg = MODE_CONFIG_REG,
68 .mask = 0x0000000F, 68 .mask = 0x0000000F,
69 .val = 0x03, 69 .val = 0x03,
70 }; 70 };
71 71
72 static struct spear_pmx_mode pmx_mode_hend_ip_phone = { 72 static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
73 .name = "hend ip phone mode", 73 .name = "hend ip phone mode",
74 .mode = HEND_IP_PHONE_MODE, 74 .mode = HEND_IP_PHONE_MODE,
75 .reg = MODE_CONFIG_REG, 75 .reg = MODE_CONFIG_REG,
76 .mask = 0x0000000F, 76 .mask = 0x0000000F,
77 .val = 0x04, 77 .val = 0x04,
78 }; 78 };
79 79
80 static struct spear_pmx_mode pmx_mode_lend_wifi_phone = { 80 static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
81 .name = "lend wifi phone mode", 81 .name = "lend wifi phone mode",
82 .mode = LEND_WIFI_PHONE_MODE, 82 .mode = LEND_WIFI_PHONE_MODE,
83 .reg = MODE_CONFIG_REG, 83 .reg = MODE_CONFIG_REG,
84 .mask = 0x0000000F, 84 .mask = 0x0000000F,
85 .val = 0x05, 85 .val = 0x05,
86 }; 86 };
87 87
88 static struct spear_pmx_mode pmx_mode_hend_wifi_phone = { 88 static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
89 .name = "hend wifi phone mode", 89 .name = "hend wifi phone mode",
90 .mode = HEND_WIFI_PHONE_MODE, 90 .mode = HEND_WIFI_PHONE_MODE,
91 .reg = MODE_CONFIG_REG, 91 .reg = MODE_CONFIG_REG,
92 .mask = 0x0000000F, 92 .mask = 0x0000000F,
93 .val = 0x06, 93 .val = 0x06,
94 }; 94 };
95 95
96 static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = { 96 static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
97 .name = "ata pabx wi2s mode", 97 .name = "ata pabx wi2s mode",
98 .mode = ATA_PABX_WI2S_MODE, 98 .mode = ATA_PABX_WI2S_MODE,
99 .reg = MODE_CONFIG_REG, 99 .reg = MODE_CONFIG_REG,
100 .mask = 0x0000000F, 100 .mask = 0x0000000F,
101 .val = 0x07, 101 .val = 0x07,
102 }; 102 };
103 103
104 static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = { 104 static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
105 .name = "ata pabx i2s mode", 105 .name = "ata pabx i2s mode",
106 .mode = ATA_PABX_I2S_MODE, 106 .mode = ATA_PABX_I2S_MODE,
107 .reg = MODE_CONFIG_REG, 107 .reg = MODE_CONFIG_REG,
108 .mask = 0x0000000F, 108 .mask = 0x0000000F,
109 .val = 0x08, 109 .val = 0x08,
110 }; 110 };
111 111
112 static struct spear_pmx_mode pmx_mode_caml_lcdw = { 112 static struct spear_pmx_mode pmx_mode_caml_lcdw = {
113 .name = "caml lcdw mode", 113 .name = "caml lcdw mode",
114 .mode = CAML_LCDW_MODE, 114 .mode = CAML_LCDW_MODE,
115 .reg = MODE_CONFIG_REG, 115 .reg = MODE_CONFIG_REG,
116 .mask = 0x0000000F, 116 .mask = 0x0000000F,
117 .val = 0x0C, 117 .val = 0x0C,
118 }; 118 };
119 119
120 static struct spear_pmx_mode pmx_mode_camu_lcd = { 120 static struct spear_pmx_mode pmx_mode_camu_lcd = {
121 .name = "camu lcd mode", 121 .name = "camu lcd mode",
122 .mode = CAMU_LCD_MODE, 122 .mode = CAMU_LCD_MODE,
123 .reg = MODE_CONFIG_REG, 123 .reg = MODE_CONFIG_REG,
124 .mask = 0x0000000F, 124 .mask = 0x0000000F,
125 .val = 0x0D, 125 .val = 0x0D,
126 }; 126 };
127 127
128 static struct spear_pmx_mode pmx_mode_camu_wlcd = { 128 static struct spear_pmx_mode pmx_mode_camu_wlcd = {
129 .name = "camu wlcd mode", 129 .name = "camu wlcd mode",
130 .mode = CAMU_WLCD_MODE, 130 .mode = CAMU_WLCD_MODE,
131 .reg = MODE_CONFIG_REG, 131 .reg = MODE_CONFIG_REG,
132 .mask = 0x0000000F, 132 .mask = 0x0000000F,
133 .val = 0xE, 133 .val = 0xE,
134 }; 134 };
135 135
136 static struct spear_pmx_mode pmx_mode_caml_lcd = { 136 static struct spear_pmx_mode pmx_mode_caml_lcd = {
137 .name = "caml lcd mode", 137 .name = "caml lcd mode",
138 .mode = CAML_LCD_MODE, 138 .mode = CAML_LCD_MODE,
139 .reg = MODE_CONFIG_REG, 139 .reg = MODE_CONFIG_REG,
140 .mask = 0x0000000F, 140 .mask = 0x0000000F,
141 .val = 0x0F, 141 .val = 0x0F,
142 }; 142 };
143 143
144 static struct spear_pmx_mode *spear300_pmx_modes[] = { 144 static struct spear_pmx_mode *spear300_pmx_modes[] = {
145 &pmx_mode_nand, 145 &pmx_mode_nand,
146 &pmx_mode_nor, 146 &pmx_mode_nor,
147 &pmx_mode_photo_frame, 147 &pmx_mode_photo_frame,
148 &pmx_mode_lend_ip_phone, 148 &pmx_mode_lend_ip_phone,
149 &pmx_mode_hend_ip_phone, 149 &pmx_mode_hend_ip_phone,
150 &pmx_mode_lend_wifi_phone, 150 &pmx_mode_lend_wifi_phone,
151 &pmx_mode_hend_wifi_phone, 151 &pmx_mode_hend_wifi_phone,
152 &pmx_mode_ata_pabx_wi2s, 152 &pmx_mode_ata_pabx_wi2s,
153 &pmx_mode_ata_pabx_i2s, 153 &pmx_mode_ata_pabx_i2s,
154 &pmx_mode_caml_lcdw, 154 &pmx_mode_caml_lcdw,
155 &pmx_mode_camu_lcd, 155 &pmx_mode_camu_lcd,
156 &pmx_mode_camu_wlcd, 156 &pmx_mode_camu_wlcd,
157 &pmx_mode_caml_lcd, 157 &pmx_mode_caml_lcd,
158 }; 158 };
159 159
160 /* fsmc_2chips_pins */ 160 /* fsmc_2chips_pins */
161 static const unsigned fsmc_2chips_pins[] = { 1, 97 }; 161 static const unsigned fsmc_2chips_pins[] = { 1, 97 };
162 static struct spear_muxreg fsmc_2chips_muxreg[] = { 162 static struct spear_muxreg fsmc_2chips_muxreg[] = {
163 { 163 {
164 .reg = PMX_CONFIG_REG, 164 .reg = PMX_CONFIG_REG,
165 .mask = PMX_FIRDA_MASK, 165 .mask = PMX_FIRDA_MASK,
166 .val = 0, 166 .val = 0,
167 }, 167 },
168 }; 168 };
169 169
170 static struct spear_modemux fsmc_2chips_modemux[] = { 170 static struct spear_modemux fsmc_2chips_modemux[] = {
171 { 171 {
172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
174 .muxregs = fsmc_2chips_muxreg, 174 .muxregs = fsmc_2chips_muxreg,
175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg), 175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
176 }, 176 },
177 }; 177 };
178 178
179 static struct spear_pingroup fsmc_2chips_pingroup = { 179 static struct spear_pingroup fsmc_2chips_pingroup = {
180 .name = "fsmc_2chips_grp", 180 .name = "fsmc_2chips_grp",
181 .pins = fsmc_2chips_pins, 181 .pins = fsmc_2chips_pins,
182 .npins = ARRAY_SIZE(fsmc_2chips_pins), 182 .npins = ARRAY_SIZE(fsmc_2chips_pins),
183 .modemuxs = fsmc_2chips_modemux, 183 .modemuxs = fsmc_2chips_modemux,
184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux), 184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
185 }; 185 };
186 186
187 /* fsmc_4chips_pins */ 187 /* fsmc_4chips_pins */
188 static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 }; 188 static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
189 static struct spear_muxreg fsmc_4chips_muxreg[] = { 189 static struct spear_muxreg fsmc_4chips_muxreg[] = {
190 { 190 {
191 .reg = PMX_CONFIG_REG, 191 .reg = PMX_CONFIG_REG,
192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, 192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
193 .val = 0, 193 .val = 0,
194 }, 194 },
195 }; 195 };
196 196
197 static struct spear_modemux fsmc_4chips_modemux[] = { 197 static struct spear_modemux fsmc_4chips_modemux[] = {
198 { 198 {
199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
201 .muxregs = fsmc_4chips_muxreg, 201 .muxregs = fsmc_4chips_muxreg,
202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg), 202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
203 }, 203 },
204 }; 204 };
205 205
206 static struct spear_pingroup fsmc_4chips_pingroup = { 206 static struct spear_pingroup fsmc_4chips_pingroup = {
207 .name = "fsmc_4chips_grp", 207 .name = "fsmc_4chips_grp",
208 .pins = fsmc_4chips_pins, 208 .pins = fsmc_4chips_pins,
209 .npins = ARRAY_SIZE(fsmc_4chips_pins), 209 .npins = ARRAY_SIZE(fsmc_4chips_pins),
210 .modemuxs = fsmc_4chips_modemux, 210 .modemuxs = fsmc_4chips_modemux,
211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux), 211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
212 }; 212 };
213 213
214 static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp" 214 static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
215 }; 215 };
216 static struct spear_function fsmc_function = { 216 static struct spear_function fsmc_function = {
217 .name = "fsmc", 217 .name = "fsmc",
218 .groups = fsmc_grps, 218 .groups = fsmc_grps,
219 .ngroups = ARRAY_SIZE(fsmc_grps), 219 .ngroups = ARRAY_SIZE(fsmc_grps),
220 }; 220 };
221 221
222 /* clcd_lcdmode_pins */ 222 /* clcd_lcdmode_pins */
223 static const unsigned clcd_lcdmode_pins[] = { 49, 50 }; 223 static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
224 static struct spear_muxreg clcd_lcdmode_muxreg[] = { 224 static struct spear_muxreg clcd_lcdmode_muxreg[] = {
225 { 225 {
226 .reg = PMX_CONFIG_REG, 226 .reg = PMX_CONFIG_REG,
227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
228 .val = 0, 228 .val = 0,
229 }, 229 },
230 }; 230 };
231 231
232 static struct spear_modemux clcd_lcdmode_modemux[] = { 232 static struct spear_modemux clcd_lcdmode_modemux[] = {
233 { 233 {
234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | 234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
235 CAMU_LCD_MODE | CAML_LCD_MODE, 235 CAMU_LCD_MODE | CAML_LCD_MODE,
236 .muxregs = clcd_lcdmode_muxreg, 236 .muxregs = clcd_lcdmode_muxreg,
237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg), 237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
238 }, 238 },
239 }; 239 };
240 240
241 static struct spear_pingroup clcd_lcdmode_pingroup = { 241 static struct spear_pingroup clcd_lcdmode_pingroup = {
242 .name = "clcd_lcdmode_grp", 242 .name = "clcd_lcdmode_grp",
243 .pins = clcd_lcdmode_pins, 243 .pins = clcd_lcdmode_pins,
244 .npins = ARRAY_SIZE(clcd_lcdmode_pins), 244 .npins = ARRAY_SIZE(clcd_lcdmode_pins),
245 .modemuxs = clcd_lcdmode_modemux, 245 .modemuxs = clcd_lcdmode_modemux,
246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux), 246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
247 }; 247 };
248 248
249 /* clcd_pfmode_pins */ 249 /* clcd_pfmode_pins */
250 static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 }; 250 static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
251 static struct spear_muxreg clcd_pfmode_muxreg[] = { 251 static struct spear_muxreg clcd_pfmode_muxreg[] = {
252 { 252 {
253 .reg = PMX_CONFIG_REG, 253 .reg = PMX_CONFIG_REG,
254 .mask = PMX_TIMER_2_3_MASK, 254 .mask = PMX_TIMER_2_3_MASK,
255 .val = 0, 255 .val = 0,
256 }, 256 },
257 }; 257 };
258 258
259 static struct spear_modemux clcd_pfmode_modemux[] = { 259 static struct spear_modemux clcd_pfmode_modemux[] = {
260 { 260 {
261 .modes = PHOTO_FRAME_MODE, 261 .modes = PHOTO_FRAME_MODE,
262 .muxregs = clcd_pfmode_muxreg, 262 .muxregs = clcd_pfmode_muxreg,
263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg), 263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
264 }, 264 },
265 }; 265 };
266 266
267 static struct spear_pingroup clcd_pfmode_pingroup = { 267 static struct spear_pingroup clcd_pfmode_pingroup = {
268 .name = "clcd_pfmode_grp", 268 .name = "clcd_pfmode_grp",
269 .pins = clcd_pfmode_pins, 269 .pins = clcd_pfmode_pins,
270 .npins = ARRAY_SIZE(clcd_pfmode_pins), 270 .npins = ARRAY_SIZE(clcd_pfmode_pins),
271 .modemuxs = clcd_pfmode_modemux, 271 .modemuxs = clcd_pfmode_modemux,
272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux), 272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
273 }; 273 };
274 274
275 static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp" 275 static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
276 }; 276 };
277 static struct spear_function clcd_function = { 277 static struct spear_function clcd_function = {
278 .name = "clcd", 278 .name = "clcd",
279 .groups = clcd_grps, 279 .groups = clcd_grps,
280 .ngroups = ARRAY_SIZE(clcd_grps), 280 .ngroups = ARRAY_SIZE(clcd_grps),
281 }; 281 };
282 282
283 /* tdm_pins */ 283 /* tdm_pins */
284 static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 }; 284 static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
285 static struct spear_muxreg tdm_muxreg[] = { 285 static struct spear_muxreg tdm_muxreg[] = {
286 { 286 {
287 .reg = PMX_CONFIG_REG, 287 .reg = PMX_CONFIG_REG,
288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, 288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
289 .val = 0, 289 .val = 0,
290 }, 290 },
291 }; 291 };
292 292
293 static struct spear_modemux tdm_modemux[] = { 293 static struct spear_modemux tdm_modemux[] = {
294 { 294 {
295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE 296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE 297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
299 | CAMU_WLCD_MODE | CAML_LCD_MODE, 299 | CAMU_WLCD_MODE | CAML_LCD_MODE,
300 .muxregs = tdm_muxreg, 300 .muxregs = tdm_muxreg,
301 .nmuxregs = ARRAY_SIZE(tdm_muxreg), 301 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
302 }, 302 },
303 }; 303 };
304 304
305 static struct spear_pingroup tdm_pingroup = { 305 static struct spear_pingroup tdm_pingroup = {
306 .name = "tdm_grp", 306 .name = "tdm_grp",
307 .pins = tdm_pins, 307 .pins = tdm_pins,
308 .npins = ARRAY_SIZE(tdm_pins), 308 .npins = ARRAY_SIZE(tdm_pins),
309 .modemuxs = tdm_modemux, 309 .modemuxs = tdm_modemux,
310 .nmodemuxs = ARRAY_SIZE(tdm_modemux), 310 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
311 }; 311 };
312 312
313 static const char *const tdm_grps[] = { "tdm_grp" }; 313 static const char *const tdm_grps[] = { "tdm_grp" };
314 static struct spear_function tdm_function = { 314 static struct spear_function tdm_function = {
315 .name = "tdm", 315 .name = "tdm",
316 .groups = tdm_grps, 316 .groups = tdm_grps,
317 .ngroups = ARRAY_SIZE(tdm_grps), 317 .ngroups = ARRAY_SIZE(tdm_grps),
318 }; 318 };
319 319
320 /* i2c_clk_pins */ 320 /* i2c_clk_pins */
321 static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 }; 321 static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
322 static struct spear_muxreg i2c_clk_muxreg[] = { 322 static struct spear_muxreg i2c_clk_muxreg[] = {
323 { 323 {
324 .reg = PMX_CONFIG_REG, 324 .reg = PMX_CONFIG_REG,
325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
326 .val = 0, 326 .val = 0,
327 }, 327 },
328 }; 328 };
329 329
330 static struct spear_modemux i2c_clk_modemux[] = { 330 static struct spear_modemux i2c_clk_modemux[] = {
331 { 331 {
332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | 332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE 334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
335 | CAML_LCD_MODE, 335 | CAML_LCD_MODE,
336 .muxregs = i2c_clk_muxreg, 336 .muxregs = i2c_clk_muxreg,
337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg), 337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
338 }, 338 },
339 }; 339 };
340 340
341 static struct spear_pingroup i2c_clk_pingroup = { 341 static struct spear_pingroup i2c_clk_pingroup = {
342 .name = "i2c_clk_grp_grp", 342 .name = "i2c_clk_grp_grp",
343 .pins = i2c_clk_pins, 343 .pins = i2c_clk_pins,
344 .npins = ARRAY_SIZE(i2c_clk_pins), 344 .npins = ARRAY_SIZE(i2c_clk_pins),
345 .modemuxs = i2c_clk_modemux, 345 .modemuxs = i2c_clk_modemux,
346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux), 346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
347 }; 347 };
348 348
349 static const char *const i2c_grps[] = { "i2c_clk_grp" }; 349 static const char *const i2c_grps[] = { "i2c_clk_grp" };
350 static struct spear_function i2c_function = { 350 static struct spear_function i2c_function = {
351 .name = "i2c1", 351 .name = "i2c1",
352 .groups = i2c_grps, 352 .groups = i2c_grps,
353 .ngroups = ARRAY_SIZE(i2c_grps), 353 .ngroups = ARRAY_SIZE(i2c_grps),
354 }; 354 };
355 355
356 /* caml_pins */ 356 /* caml_pins */
357 static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 }; 357 static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
358 static struct spear_muxreg caml_muxreg[] = { 358 static struct spear_muxreg caml_muxreg[] = {
359 { 359 {
360 .reg = PMX_CONFIG_REG, 360 .reg = PMX_CONFIG_REG,
361 .mask = PMX_MII_MASK, 361 .mask = PMX_MII_MASK,
362 .val = 0, 362 .val = 0,
363 }, 363 },
364 }; 364 };
365 365
366 static struct spear_modemux caml_modemux[] = { 366 static struct spear_modemux caml_modemux[] = {
367 { 367 {
368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE, 368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
369 .muxregs = caml_muxreg, 369 .muxregs = caml_muxreg,
370 .nmuxregs = ARRAY_SIZE(caml_muxreg), 370 .nmuxregs = ARRAY_SIZE(caml_muxreg),
371 }, 371 },
372 }; 372 };
373 373
374 static struct spear_pingroup caml_pingroup = { 374 static struct spear_pingroup caml_pingroup = {
375 .name = "caml_grp", 375 .name = "caml_grp",
376 .pins = caml_pins, 376 .pins = caml_pins,
377 .npins = ARRAY_SIZE(caml_pins), 377 .npins = ARRAY_SIZE(caml_pins),
378 .modemuxs = caml_modemux, 378 .modemuxs = caml_modemux,
379 .nmodemuxs = ARRAY_SIZE(caml_modemux), 379 .nmodemuxs = ARRAY_SIZE(caml_modemux),
380 }; 380 };
381 381
382 /* camu_pins */ 382 /* camu_pins */
383 static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 }; 383 static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
384 static struct spear_muxreg camu_muxreg[] = { 384 static struct spear_muxreg camu_muxreg[] = {
385 { 385 {
386 .reg = PMX_CONFIG_REG, 386 .reg = PMX_CONFIG_REG,
387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, 387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
388 .val = 0, 388 .val = 0,
389 }, 389 },
390 }; 390 };
391 391
392 static struct spear_modemux camu_modemux[] = { 392 static struct spear_modemux camu_modemux[] = {
393 { 393 {
394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE, 394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
395 .muxregs = camu_muxreg, 395 .muxregs = camu_muxreg,
396 .nmuxregs = ARRAY_SIZE(camu_muxreg), 396 .nmuxregs = ARRAY_SIZE(camu_muxreg),
397 }, 397 },
398 }; 398 };
399 399
400 static struct spear_pingroup camu_pingroup = { 400 static struct spear_pingroup camu_pingroup = {
401 .name = "camu_grp", 401 .name = "camu_grp",
402 .pins = camu_pins, 402 .pins = camu_pins,
403 .npins = ARRAY_SIZE(camu_pins), 403 .npins = ARRAY_SIZE(camu_pins),
404 .modemuxs = camu_modemux, 404 .modemuxs = camu_modemux,
405 .nmodemuxs = ARRAY_SIZE(camu_modemux), 405 .nmodemuxs = ARRAY_SIZE(camu_modemux),
406 }; 406 };
407 407
408 static const char *const cam_grps[] = { "caml_grp", "camu_grp" }; 408 static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
409 static struct spear_function cam_function = { 409 static struct spear_function cam_function = {
410 .name = "cam", 410 .name = "cam",
411 .groups = cam_grps, 411 .groups = cam_grps,
412 .ngroups = ARRAY_SIZE(cam_grps), 412 .ngroups = ARRAY_SIZE(cam_grps),
413 }; 413 };
414 414
415 /* dac_pins */ 415 /* dac_pins */
416 static const unsigned dac_pins[] = { 43, 44 }; 416 static const unsigned dac_pins[] = { 43, 44 };
417 static struct spear_muxreg dac_muxreg[] = { 417 static struct spear_muxreg dac_muxreg[] = {
418 { 418 {
419 .reg = PMX_CONFIG_REG, 419 .reg = PMX_CONFIG_REG,
420 .mask = PMX_TIMER_0_1_MASK, 420 .mask = PMX_TIMER_0_1_MASK,
421 .val = 0, 421 .val = 0,
422 }, 422 },
423 }; 423 };
424 424
425 static struct spear_modemux dac_modemux[] = { 425 static struct spear_modemux dac_modemux[] = {
426 { 426 {
427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
428 | CAMU_WLCD_MODE | CAML_LCD_MODE, 428 | CAMU_WLCD_MODE | CAML_LCD_MODE,
429 .muxregs = dac_muxreg, 429 .muxregs = dac_muxreg,
430 .nmuxregs = ARRAY_SIZE(dac_muxreg), 430 .nmuxregs = ARRAY_SIZE(dac_muxreg),
431 }, 431 },
432 }; 432 };
433 433
434 static struct spear_pingroup dac_pingroup = { 434 static struct spear_pingroup dac_pingroup = {
435 .name = "dac_grp", 435 .name = "dac_grp",
436 .pins = dac_pins, 436 .pins = dac_pins,
437 .npins = ARRAY_SIZE(dac_pins), 437 .npins = ARRAY_SIZE(dac_pins),
438 .modemuxs = dac_modemux, 438 .modemuxs = dac_modemux,
439 .nmodemuxs = ARRAY_SIZE(dac_modemux), 439 .nmodemuxs = ARRAY_SIZE(dac_modemux),
440 }; 440 };
441 441
442 static const char *const dac_grps[] = { "dac_grp" }; 442 static const char *const dac_grps[] = { "dac_grp" };
443 static struct spear_function dac_function = { 443 static struct spear_function dac_function = {
444 .name = "dac", 444 .name = "dac",
445 .groups = dac_grps, 445 .groups = dac_grps,
446 .ngroups = ARRAY_SIZE(dac_grps), 446 .ngroups = ARRAY_SIZE(dac_grps),
447 }; 447 };
448 448
449 /* i2s_pins */ 449 /* i2s_pins */
450 static const unsigned i2s_pins[] = { 39, 40, 41, 42 }; 450 static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
451 static struct spear_muxreg i2s_muxreg[] = { 451 static struct spear_muxreg i2s_muxreg[] = {
452 { 452 {
453 .reg = PMX_CONFIG_REG, 453 .reg = PMX_CONFIG_REG,
454 .mask = PMX_UART0_MODEM_MASK, 454 .mask = PMX_UART0_MODEM_MASK,
455 .val = 0, 455 .val = 0,
456 }, 456 },
457 }; 457 };
458 458
459 static struct spear_modemux i2s_modemux[] = { 459 static struct spear_modemux i2s_modemux[] = {
460 { 460 {
461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE 461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
464 | CAMU_WLCD_MODE | CAML_LCD_MODE, 464 | CAMU_WLCD_MODE | CAML_LCD_MODE,
465 .muxregs = i2s_muxreg, 465 .muxregs = i2s_muxreg,
466 .nmuxregs = ARRAY_SIZE(i2s_muxreg), 466 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
467 }, 467 },
468 }; 468 };
469 469
470 static struct spear_pingroup i2s_pingroup = { 470 static struct spear_pingroup i2s_pingroup = {
471 .name = "i2s_grp", 471 .name = "i2s_grp",
472 .pins = i2s_pins, 472 .pins = i2s_pins,
473 .npins = ARRAY_SIZE(i2s_pins), 473 .npins = ARRAY_SIZE(i2s_pins),
474 .modemuxs = i2s_modemux, 474 .modemuxs = i2s_modemux,
475 .nmodemuxs = ARRAY_SIZE(i2s_modemux), 475 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
476 }; 476 };
477 477
478 static const char *const i2s_grps[] = { "i2s_grp" }; 478 static const char *const i2s_grps[] = { "i2s_grp" };
479 static struct spear_function i2s_function = { 479 static struct spear_function i2s_function = {
480 .name = "i2s", 480 .name = "i2s",
481 .groups = i2s_grps, 481 .groups = i2s_grps,
482 .ngroups = ARRAY_SIZE(i2s_grps), 482 .ngroups = ARRAY_SIZE(i2s_grps),
483 }; 483 };
484 484
485 /* sdhci_4bit_pins */ 485 /* sdhci_4bit_pins */
486 static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 }; 486 static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
487 static struct spear_muxreg sdhci_4bit_muxreg[] = { 487 static struct spear_muxreg sdhci_4bit_muxreg[] = {
488 { 488 {
489 .reg = PMX_CONFIG_REG, 489 .reg = PMX_CONFIG_REG,
490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | 490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, 492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
493 .val = 0, 493 .val = 0,
494 }, 494 },
495 }; 495 };
496 496
497 static struct spear_modemux sdhci_4bit_modemux[] = { 497 static struct spear_modemux sdhci_4bit_modemux[] = {
498 { 498 {
499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | 501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE, 502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
503 .muxregs = sdhci_4bit_muxreg, 503 .muxregs = sdhci_4bit_muxreg,
504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg), 504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
505 }, 505 },
506 }; 506 };
507 507
508 static struct spear_pingroup sdhci_4bit_pingroup = { 508 static struct spear_pingroup sdhci_4bit_pingroup = {
509 .name = "sdhci_4bit_grp", 509 .name = "sdhci_4bit_grp",
510 .pins = sdhci_4bit_pins, 510 .pins = sdhci_4bit_pins,
511 .npins = ARRAY_SIZE(sdhci_4bit_pins), 511 .npins = ARRAY_SIZE(sdhci_4bit_pins),
512 .modemuxs = sdhci_4bit_modemux, 512 .modemuxs = sdhci_4bit_modemux,
513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux), 513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
514 }; 514 };
515 515
516 /* sdhci_8bit_pins */ 516 /* sdhci_8bit_pins */
517 static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, 517 static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
518 33 }; 518 33 };
519 static struct spear_muxreg sdhci_8bit_muxreg[] = { 519 static struct spear_muxreg sdhci_8bit_muxreg[] = {
520 { 520 {
521 .reg = PMX_CONFIG_REG, 521 .reg = PMX_CONFIG_REG,
522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | 522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, 524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
525 .val = 0, 525 .val = 0,
526 }, 526 },
527 }; 527 };
528 528
529 static struct spear_modemux sdhci_8bit_modemux[] = { 529 static struct spear_modemux sdhci_8bit_modemux[] = {
530 { 530 {
531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | 533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
534 CAMU_WLCD_MODE | CAML_LCD_MODE, 534 CAMU_WLCD_MODE | CAML_LCD_MODE,
535 .muxregs = sdhci_8bit_muxreg, 535 .muxregs = sdhci_8bit_muxreg,
536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg), 536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
537 }, 537 },
538 }; 538 };
539 539
540 static struct spear_pingroup sdhci_8bit_pingroup = { 540 static struct spear_pingroup sdhci_8bit_pingroup = {
541 .name = "sdhci_8bit_grp", 541 .name = "sdhci_8bit_grp",
542 .pins = sdhci_8bit_pins, 542 .pins = sdhci_8bit_pins,
543 .npins = ARRAY_SIZE(sdhci_8bit_pins), 543 .npins = ARRAY_SIZE(sdhci_8bit_pins),
544 .modemuxs = sdhci_8bit_modemux, 544 .modemuxs = sdhci_8bit_modemux,
545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux), 545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
546 }; 546 };
547 547
548 static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" }; 548 static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
549 static struct spear_function sdhci_function = { 549 static struct spear_function sdhci_function = {
550 .name = "sdhci", 550 .name = "sdhci",
551 .groups = sdhci_grps, 551 .groups = sdhci_grps,
552 .ngroups = ARRAY_SIZE(sdhci_grps), 552 .ngroups = ARRAY_SIZE(sdhci_grps),
553 }; 553 };
554 554
555 /* gpio1_0_to_3_pins */ 555 /* gpio1_0_to_3_pins */
556 static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 }; 556 static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
557 static struct spear_muxreg gpio1_0_to_3_muxreg[] = { 557 static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
558 { 558 {
559 .reg = PMX_CONFIG_REG, 559 .reg = PMX_CONFIG_REG,
560 .mask = PMX_UART0_MODEM_MASK, 560 .mask = PMX_UART0_MODEM_MASK,
561 .val = 0, 561 .val = 0,
562 }, 562 },
563 }; 563 };
564 564
565 static struct spear_modemux gpio1_0_to_3_modemux[] = { 565 static struct spear_modemux gpio1_0_to_3_modemux[] = {
566 { 566 {
567 .modes = PHOTO_FRAME_MODE, 567 .modes = PHOTO_FRAME_MODE,
568 .muxregs = gpio1_0_to_3_muxreg, 568 .muxregs = gpio1_0_to_3_muxreg,
569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg), 569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
570 }, 570 },
571 }; 571 };
572 572
573 static struct spear_pingroup gpio1_0_to_3_pingroup = { 573 static struct spear_pingroup gpio1_0_to_3_pingroup = {
574 .name = "gpio1_0_to_3_grp", 574 .name = "gpio1_0_to_3_grp",
575 .pins = gpio1_0_to_3_pins, 575 .pins = gpio1_0_to_3_pins,
576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins), 576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
577 .modemuxs = gpio1_0_to_3_modemux, 577 .modemuxs = gpio1_0_to_3_modemux,
578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux), 578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
579 }; 579 };
580 580
581 /* gpio1_4_to_7_pins */ 581 /* gpio1_4_to_7_pins */
582 static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 }; 582 static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
583 583
584 static struct spear_muxreg gpio1_4_to_7_muxreg[] = { 584 static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
585 { 585 {
586 .reg = PMX_CONFIG_REG, 586 .reg = PMX_CONFIG_REG,
587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
588 .val = 0, 588 .val = 0,
589 }, 589 },
590 }; 590 };
591 591
592 static struct spear_modemux gpio1_4_to_7_modemux[] = { 592 static struct spear_modemux gpio1_4_to_7_modemux[] = {
593 { 593 {
594 .modes = PHOTO_FRAME_MODE, 594 .modes = PHOTO_FRAME_MODE,
595 .muxregs = gpio1_4_to_7_muxreg, 595 .muxregs = gpio1_4_to_7_muxreg,
596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg), 596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
597 }, 597 },
598 }; 598 };
599 599
600 static struct spear_pingroup gpio1_4_to_7_pingroup = { 600 static struct spear_pingroup gpio1_4_to_7_pingroup = {
601 .name = "gpio1_4_to_7_grp", 601 .name = "gpio1_4_to_7_grp",
602 .pins = gpio1_4_to_7_pins, 602 .pins = gpio1_4_to_7_pins,
603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins), 603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
604 .modemuxs = gpio1_4_to_7_modemux, 604 .modemuxs = gpio1_4_to_7_modemux,
605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux), 605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
606 }; 606 };
607 607
608 static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" 608 static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
609 }; 609 };
610 static struct spear_function gpio1_function = { 610 static struct spear_function gpio1_function = {
611 .name = "gpio1", 611 .name = "gpio1",
612 .groups = gpio1_grps, 612 .groups = gpio1_grps,
613 .ngroups = ARRAY_SIZE(gpio1_grps), 613 .ngroups = ARRAY_SIZE(gpio1_grps),
614 }; 614 };
615 615
616 /* pingroups */ 616 /* pingroups */
617 static struct spear_pingroup *spear300_pingroups[] = { 617 static struct spear_pingroup *spear300_pingroups[] = {
618 SPEAR3XX_COMMON_PINGROUPS, 618 SPEAR3XX_COMMON_PINGROUPS,
619 &fsmc_2chips_pingroup, 619 &fsmc_2chips_pingroup,
620 &fsmc_4chips_pingroup, 620 &fsmc_4chips_pingroup,
621 &clcd_lcdmode_pingroup, 621 &clcd_lcdmode_pingroup,
622 &clcd_pfmode_pingroup, 622 &clcd_pfmode_pingroup,
623 &tdm_pingroup, 623 &tdm_pingroup,
624 &i2c_clk_pingroup, 624 &i2c_clk_pingroup,
625 &caml_pingroup, 625 &caml_pingroup,
626 &camu_pingroup, 626 &camu_pingroup,
627 &dac_pingroup, 627 &dac_pingroup,
628 &i2s_pingroup, 628 &i2s_pingroup,
629 &sdhci_4bit_pingroup, 629 &sdhci_4bit_pingroup,
630 &sdhci_8bit_pingroup, 630 &sdhci_8bit_pingroup,
631 &gpio1_0_to_3_pingroup, 631 &gpio1_0_to_3_pingroup,
632 &gpio1_4_to_7_pingroup, 632 &gpio1_4_to_7_pingroup,
633 }; 633 };
634 634
635 /* functions */ 635 /* functions */
636 static struct spear_function *spear300_functions[] = { 636 static struct spear_function *spear300_functions[] = {
637 SPEAR3XX_COMMON_FUNCTIONS, 637 SPEAR3XX_COMMON_FUNCTIONS,
638 &fsmc_function, 638 &fsmc_function,
639 &clcd_function, 639 &clcd_function,
640 &tdm_function, 640 &tdm_function,
641 &i2c_function, 641 &i2c_function,
642 &cam_function, 642 &cam_function,
643 &dac_function, 643 &dac_function,
644 &i2s_function, 644 &i2s_function,
645 &sdhci_function, 645 &sdhci_function,
646 &gpio1_function, 646 &gpio1_function,
647 }; 647 };
648 648
649 static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = { 649 static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
650 { 650 {
651 .compatible = "st,spear300-pinmux", 651 .compatible = "st,spear300-pinmux",
652 }, 652 },
653 {}, 653 {},
654 }; 654 };
655 655
656 static int __devinit spear300_pinctrl_probe(struct platform_device *pdev) 656 static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
657 { 657 {
658 int ret; 658 int ret;
659 659
660 spear3xx_machdata.groups = spear300_pingroups; 660 spear3xx_machdata.groups = spear300_pingroups;
661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); 661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662 spear3xx_machdata.functions = spear300_functions; 662 spear3xx_machdata.functions = spear300_functions;
663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions); 663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
664 spear3xx_machdata.gpio_pingroups = NULL;
665 spear3xx_machdata.ngpio_pingroups = 0;
664 666
665 spear3xx_machdata.modes_supported = true; 667 spear3xx_machdata.modes_supported = true;
666 spear3xx_machdata.pmx_modes = spear300_pmx_modes; 668 spear3xx_machdata.pmx_modes = spear300_pmx_modes;
667 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes); 669 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
668 670
669 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); 671 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
670 672
671 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); 673 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
672 if (ret) 674 if (ret)
673 return ret; 675 return ret;
674 676
675 return 0; 677 return 0;
676 } 678 }
677 679
678 static int __devexit spear300_pinctrl_remove(struct platform_device *pdev) 680 static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
679 { 681 {
680 return spear_pinctrl_remove(pdev); 682 return spear_pinctrl_remove(pdev);
681 } 683 }
682 684
683 static struct platform_driver spear300_pinctrl_driver = { 685 static struct platform_driver spear300_pinctrl_driver = {
684 .driver = { 686 .driver = {
685 .name = DRIVER_NAME, 687 .name = DRIVER_NAME,
686 .owner = THIS_MODULE, 688 .owner = THIS_MODULE,
687 .of_match_table = spear300_pinctrl_of_match, 689 .of_match_table = spear300_pinctrl_of_match,
688 }, 690 },
689 .probe = spear300_pinctrl_probe, 691 .probe = spear300_pinctrl_probe,
690 .remove = __devexit_p(spear300_pinctrl_remove), 692 .remove = __devexit_p(spear300_pinctrl_remove),
691 }; 693 };
692 694
693 static int __init spear300_pinctrl_init(void) 695 static int __init spear300_pinctrl_init(void)
694 { 696 {
695 return platform_driver_register(&spear300_pinctrl_driver); 697 return platform_driver_register(&spear300_pinctrl_driver);
696 } 698 }
697 arch_initcall(spear300_pinctrl_init); 699 arch_initcall(spear300_pinctrl_init);
698 700
699 static void __exit spear300_pinctrl_exit(void) 701 static void __exit spear300_pinctrl_exit(void)
700 { 702 {
701 platform_driver_unregister(&spear300_pinctrl_driver); 703 platform_driver_unregister(&spear300_pinctrl_driver);
702 } 704 }
703 module_exit(spear300_pinctrl_exit); 705 module_exit(spear300_pinctrl_exit);
704 706
705 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 707 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
706 MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver"); 708 MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
707 MODULE_LICENSE("GPL v2"); 709 MODULE_LICENSE("GPL v2");
708 MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match); 710 MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
709 711
drivers/pinctrl/spear/pinctrl-spear310.c
Diff comments   View file @ f4f8e56
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr310 pinmux 2 * Driver for the ST Microelectronics SPEAr310 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear3xx.h" 17 #include "pinctrl-spear3xx.h"
18 18
19 #define DRIVER_NAME "spear310-pinmux" 19 #define DRIVER_NAME "spear310-pinmux"
20 20
21 /* addresses */ 21 /* addresses */
22 #define PMX_CONFIG_REG 0x08 22 #define PMX_CONFIG_REG 0x08
23 23
24 /* emi_cs_0_to_5_pins */ 24 /* emi_cs_0_to_5_pins */
25 static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 }; 25 static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
26 static struct spear_muxreg emi_cs_0_to_5_muxreg[] = { 26 static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
27 { 27 {
28 .reg = PMX_CONFIG_REG, 28 .reg = PMX_CONFIG_REG,
29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
30 .val = 0, 30 .val = 0,
31 }, 31 },
32 }; 32 };
33 33
34 static struct spear_modemux emi_cs_0_to_5_modemux[] = { 34 static struct spear_modemux emi_cs_0_to_5_modemux[] = {
35 { 35 {
36 .muxregs = emi_cs_0_to_5_muxreg, 36 .muxregs = emi_cs_0_to_5_muxreg,
37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg), 37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
38 }, 38 },
39 }; 39 };
40 40
41 static struct spear_pingroup emi_cs_0_to_5_pingroup = { 41 static struct spear_pingroup emi_cs_0_to_5_pingroup = {
42 .name = "emi_cs_0_to_5_grp", 42 .name = "emi_cs_0_to_5_grp",
43 .pins = emi_cs_0_to_5_pins, 43 .pins = emi_cs_0_to_5_pins,
44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins), 44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
45 .modemuxs = emi_cs_0_to_5_modemux, 45 .modemuxs = emi_cs_0_to_5_modemux,
46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux), 46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
47 }; 47 };
48 48
49 static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" }; 49 static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
50 static struct spear_function emi_cs_0_to_5_function = { 50 static struct spear_function emi_cs_0_to_5_function = {
51 .name = "emi", 51 .name = "emi",
52 .groups = emi_cs_0_to_5_grps, 52 .groups = emi_cs_0_to_5_grps,
53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps), 53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
54 }; 54 };
55 55
56 /* uart1_pins */ 56 /* uart1_pins */
57 static const unsigned uart1_pins[] = { 0, 1 }; 57 static const unsigned uart1_pins[] = { 0, 1 };
58 static struct spear_muxreg uart1_muxreg[] = { 58 static struct spear_muxreg uart1_muxreg[] = {
59 { 59 {
60 .reg = PMX_CONFIG_REG, 60 .reg = PMX_CONFIG_REG,
61 .mask = PMX_FIRDA_MASK, 61 .mask = PMX_FIRDA_MASK,
62 .val = 0, 62 .val = 0,
63 }, 63 },
64 }; 64 };
65 65
66 static struct spear_modemux uart1_modemux[] = { 66 static struct spear_modemux uart1_modemux[] = {
67 { 67 {
68 .muxregs = uart1_muxreg, 68 .muxregs = uart1_muxreg,
69 .nmuxregs = ARRAY_SIZE(uart1_muxreg), 69 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
70 }, 70 },
71 }; 71 };
72 72
73 static struct spear_pingroup uart1_pingroup = { 73 static struct spear_pingroup uart1_pingroup = {
74 .name = "uart1_grp", 74 .name = "uart1_grp",
75 .pins = uart1_pins, 75 .pins = uart1_pins,
76 .npins = ARRAY_SIZE(uart1_pins), 76 .npins = ARRAY_SIZE(uart1_pins),
77 .modemuxs = uart1_modemux, 77 .modemuxs = uart1_modemux,
78 .nmodemuxs = ARRAY_SIZE(uart1_modemux), 78 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
79 }; 79 };
80 80
81 static const char *const uart1_grps[] = { "uart1_grp" }; 81 static const char *const uart1_grps[] = { "uart1_grp" };
82 static struct spear_function uart1_function = { 82 static struct spear_function uart1_function = {
83 .name = "uart1", 83 .name = "uart1",
84 .groups = uart1_grps, 84 .groups = uart1_grps,
85 .ngroups = ARRAY_SIZE(uart1_grps), 85 .ngroups = ARRAY_SIZE(uart1_grps),
86 }; 86 };
87 87
88 /* uart2_pins */ 88 /* uart2_pins */
89 static const unsigned uart2_pins[] = { 43, 44 }; 89 static const unsigned uart2_pins[] = { 43, 44 };
90 static struct spear_muxreg uart2_muxreg[] = { 90 static struct spear_muxreg uart2_muxreg[] = {
91 { 91 {
92 .reg = PMX_CONFIG_REG, 92 .reg = PMX_CONFIG_REG,
93 .mask = PMX_TIMER_0_1_MASK, 93 .mask = PMX_TIMER_0_1_MASK,
94 .val = 0, 94 .val = 0,
95 }, 95 },
96 }; 96 };
97 97
98 static struct spear_modemux uart2_modemux[] = { 98 static struct spear_modemux uart2_modemux[] = {
99 { 99 {
100 .muxregs = uart2_muxreg, 100 .muxregs = uart2_muxreg,
101 .nmuxregs = ARRAY_SIZE(uart2_muxreg), 101 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
102 }, 102 },
103 }; 103 };
104 104
105 static struct spear_pingroup uart2_pingroup = { 105 static struct spear_pingroup uart2_pingroup = {
106 .name = "uart2_grp", 106 .name = "uart2_grp",
107 .pins = uart2_pins, 107 .pins = uart2_pins,
108 .npins = ARRAY_SIZE(uart2_pins), 108 .npins = ARRAY_SIZE(uart2_pins),
109 .modemuxs = uart2_modemux, 109 .modemuxs = uart2_modemux,
110 .nmodemuxs = ARRAY_SIZE(uart2_modemux), 110 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
111 }; 111 };
112 112
113 static const char *const uart2_grps[] = { "uart2_grp" }; 113 static const char *const uart2_grps[] = { "uart2_grp" };
114 static struct spear_function uart2_function = { 114 static struct spear_function uart2_function = {
115 .name = "uart2", 115 .name = "uart2",
116 .groups = uart2_grps, 116 .groups = uart2_grps,
117 .ngroups = ARRAY_SIZE(uart2_grps), 117 .ngroups = ARRAY_SIZE(uart2_grps),
118 }; 118 };
119 119
120 /* uart3_pins */ 120 /* uart3_pins */
121 static const unsigned uart3_pins[] = { 37, 38 }; 121 static const unsigned uart3_pins[] = { 37, 38 };
122 static struct spear_muxreg uart3_muxreg[] = { 122 static struct spear_muxreg uart3_muxreg[] = {
123 { 123 {
124 .reg = PMX_CONFIG_REG, 124 .reg = PMX_CONFIG_REG,
125 .mask = PMX_UART0_MODEM_MASK, 125 .mask = PMX_UART0_MODEM_MASK,
126 .val = 0, 126 .val = 0,
127 }, 127 },
128 }; 128 };
129 129
130 static struct spear_modemux uart3_modemux[] = { 130 static struct spear_modemux uart3_modemux[] = {
131 { 131 {
132 .muxregs = uart3_muxreg, 132 .muxregs = uart3_muxreg,
133 .nmuxregs = ARRAY_SIZE(uart3_muxreg), 133 .nmuxregs = ARRAY_SIZE(uart3_muxreg),
134 }, 134 },
135 }; 135 };
136 136
137 static struct spear_pingroup uart3_pingroup = { 137 static struct spear_pingroup uart3_pingroup = {
138 .name = "uart3_grp", 138 .name = "uart3_grp",
139 .pins = uart3_pins, 139 .pins = uart3_pins,
140 .npins = ARRAY_SIZE(uart3_pins), 140 .npins = ARRAY_SIZE(uart3_pins),
141 .modemuxs = uart3_modemux, 141 .modemuxs = uart3_modemux,
142 .nmodemuxs = ARRAY_SIZE(uart3_modemux), 142 .nmodemuxs = ARRAY_SIZE(uart3_modemux),
143 }; 143 };
144 144
145 static const char *const uart3_grps[] = { "uart3_grp" }; 145 static const char *const uart3_grps[] = { "uart3_grp" };
146 static struct spear_function uart3_function = { 146 static struct spear_function uart3_function = {
147 .name = "uart3", 147 .name = "uart3",
148 .groups = uart3_grps, 148 .groups = uart3_grps,
149 .ngroups = ARRAY_SIZE(uart3_grps), 149 .ngroups = ARRAY_SIZE(uart3_grps),
150 }; 150 };
151 151
152 /* uart4_pins */ 152 /* uart4_pins */
153 static const unsigned uart4_pins[] = { 39, 40 }; 153 static const unsigned uart4_pins[] = { 39, 40 };
154 static struct spear_muxreg uart4_muxreg[] = { 154 static struct spear_muxreg uart4_muxreg[] = {
155 { 155 {
156 .reg = PMX_CONFIG_REG, 156 .reg = PMX_CONFIG_REG,
157 .mask = PMX_UART0_MODEM_MASK, 157 .mask = PMX_UART0_MODEM_MASK,
158 .val = 0, 158 .val = 0,
159 }, 159 },
160 }; 160 };
161 161
162 static struct spear_modemux uart4_modemux[] = { 162 static struct spear_modemux uart4_modemux[] = {
163 { 163 {
164 .muxregs = uart4_muxreg, 164 .muxregs = uart4_muxreg,
165 .nmuxregs = ARRAY_SIZE(uart4_muxreg), 165 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
166 }, 166 },
167 }; 167 };
168 168
169 static struct spear_pingroup uart4_pingroup = { 169 static struct spear_pingroup uart4_pingroup = {
170 .name = "uart4_grp", 170 .name = "uart4_grp",
171 .pins = uart4_pins, 171 .pins = uart4_pins,
172 .npins = ARRAY_SIZE(uart4_pins), 172 .npins = ARRAY_SIZE(uart4_pins),
173 .modemuxs = uart4_modemux, 173 .modemuxs = uart4_modemux,
174 .nmodemuxs = ARRAY_SIZE(uart4_modemux), 174 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
175 }; 175 };
176 176
177 static const char *const uart4_grps[] = { "uart4_grp" }; 177 static const char *const uart4_grps[] = { "uart4_grp" };
178 static struct spear_function uart4_function = { 178 static struct spear_function uart4_function = {
179 .name = "uart4", 179 .name = "uart4",
180 .groups = uart4_grps, 180 .groups = uart4_grps,
181 .ngroups = ARRAY_SIZE(uart4_grps), 181 .ngroups = ARRAY_SIZE(uart4_grps),
182 }; 182 };
183 183
184 /* uart5_pins */ 184 /* uart5_pins */
185 static const unsigned uart5_pins[] = { 41, 42 }; 185 static const unsigned uart5_pins[] = { 41, 42 };
186 static struct spear_muxreg uart5_muxreg[] = { 186 static struct spear_muxreg uart5_muxreg[] = {
187 { 187 {
188 .reg = PMX_CONFIG_REG, 188 .reg = PMX_CONFIG_REG,
189 .mask = PMX_UART0_MODEM_MASK, 189 .mask = PMX_UART0_MODEM_MASK,
190 .val = 0, 190 .val = 0,
191 }, 191 },
192 }; 192 };
193 193
194 static struct spear_modemux uart5_modemux[] = { 194 static struct spear_modemux uart5_modemux[] = {
195 { 195 {
196 .muxregs = uart5_muxreg, 196 .muxregs = uart5_muxreg,
197 .nmuxregs = ARRAY_SIZE(uart5_muxreg), 197 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
198 }, 198 },
199 }; 199 };
200 200
201 static struct spear_pingroup uart5_pingroup = { 201 static struct spear_pingroup uart5_pingroup = {
202 .name = "uart5_grp", 202 .name = "uart5_grp",
203 .pins = uart5_pins, 203 .pins = uart5_pins,
204 .npins = ARRAY_SIZE(uart5_pins), 204 .npins = ARRAY_SIZE(uart5_pins),
205 .modemuxs = uart5_modemux, 205 .modemuxs = uart5_modemux,
206 .nmodemuxs = ARRAY_SIZE(uart5_modemux), 206 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
207 }; 207 };
208 208
209 static const char *const uart5_grps[] = { "uart5_grp" }; 209 static const char *const uart5_grps[] = { "uart5_grp" };
210 static struct spear_function uart5_function = { 210 static struct spear_function uart5_function = {
211 .name = "uart5", 211 .name = "uart5",
212 .groups = uart5_grps, 212 .groups = uart5_grps,
213 .ngroups = ARRAY_SIZE(uart5_grps), 213 .ngroups = ARRAY_SIZE(uart5_grps),
214 }; 214 };
215 215
216 /* fsmc_pins */ 216 /* fsmc_pins */
217 static const unsigned fsmc_pins[] = { 34, 35, 36 }; 217 static const unsigned fsmc_pins[] = { 34, 35, 36 };
218 static struct spear_muxreg fsmc_muxreg[] = { 218 static struct spear_muxreg fsmc_muxreg[] = {
219 { 219 {
220 .reg = PMX_CONFIG_REG, 220 .reg = PMX_CONFIG_REG,
221 .mask = PMX_SSP_CS_MASK, 221 .mask = PMX_SSP_CS_MASK,
222 .val = 0, 222 .val = 0,
223 }, 223 },
224 }; 224 };
225 225
226 static struct spear_modemux fsmc_modemux[] = { 226 static struct spear_modemux fsmc_modemux[] = {
227 { 227 {
228 .muxregs = fsmc_muxreg, 228 .muxregs = fsmc_muxreg,
229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg), 229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
230 }, 230 },
231 }; 231 };
232 232
233 static struct spear_pingroup fsmc_pingroup = { 233 static struct spear_pingroup fsmc_pingroup = {
234 .name = "fsmc_grp", 234 .name = "fsmc_grp",
235 .pins = fsmc_pins, 235 .pins = fsmc_pins,
236 .npins = ARRAY_SIZE(fsmc_pins), 236 .npins = ARRAY_SIZE(fsmc_pins),
237 .modemuxs = fsmc_modemux, 237 .modemuxs = fsmc_modemux,
238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux), 238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
239 }; 239 };
240 240
241 static const char *const fsmc_grps[] = { "fsmc_grp" }; 241 static const char *const fsmc_grps[] = { "fsmc_grp" };
242 static struct spear_function fsmc_function = { 242 static struct spear_function fsmc_function = {
243 .name = "fsmc", 243 .name = "fsmc",
244 .groups = fsmc_grps, 244 .groups = fsmc_grps,
245 .ngroups = ARRAY_SIZE(fsmc_grps), 245 .ngroups = ARRAY_SIZE(fsmc_grps),
246 }; 246 };
247 247
248 /* rs485_0_pins */ 248 /* rs485_0_pins */
249 static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 }; 249 static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
250 static struct spear_muxreg rs485_0_muxreg[] = { 250 static struct spear_muxreg rs485_0_muxreg[] = {
251 { 251 {
252 .reg = PMX_CONFIG_REG, 252 .reg = PMX_CONFIG_REG,
253 .mask = PMX_MII_MASK, 253 .mask = PMX_MII_MASK,
254 .val = 0, 254 .val = 0,
255 }, 255 },
256 }; 256 };
257 257
258 static struct spear_modemux rs485_0_modemux[] = { 258 static struct spear_modemux rs485_0_modemux[] = {
259 { 259 {
260 .muxregs = rs485_0_muxreg, 260 .muxregs = rs485_0_muxreg,
261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg), 261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
262 }, 262 },
263 }; 263 };
264 264
265 static struct spear_pingroup rs485_0_pingroup = { 265 static struct spear_pingroup rs485_0_pingroup = {
266 .name = "rs485_0_grp", 266 .name = "rs485_0_grp",
267 .pins = rs485_0_pins, 267 .pins = rs485_0_pins,
268 .npins = ARRAY_SIZE(rs485_0_pins), 268 .npins = ARRAY_SIZE(rs485_0_pins),
269 .modemuxs = rs485_0_modemux, 269 .modemuxs = rs485_0_modemux,
270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux), 270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
271 }; 271 };
272 272
273 static const char *const rs485_0_grps[] = { "rs485_0" }; 273 static const char *const rs485_0_grps[] = { "rs485_0" };
274 static struct spear_function rs485_0_function = { 274 static struct spear_function rs485_0_function = {
275 .name = "rs485_0", 275 .name = "rs485_0",
276 .groups = rs485_0_grps, 276 .groups = rs485_0_grps,
277 .ngroups = ARRAY_SIZE(rs485_0_grps), 277 .ngroups = ARRAY_SIZE(rs485_0_grps),
278 }; 278 };
279 279
280 /* rs485_1_pins */ 280 /* rs485_1_pins */
281 static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 }; 281 static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
282 static struct spear_muxreg rs485_1_muxreg[] = { 282 static struct spear_muxreg rs485_1_muxreg[] = {
283 { 283 {
284 .reg = PMX_CONFIG_REG, 284 .reg = PMX_CONFIG_REG,
285 .mask = PMX_MII_MASK, 285 .mask = PMX_MII_MASK,
286 .val = 0, 286 .val = 0,
287 }, 287 },
288 }; 288 };
289 289
290 static struct spear_modemux rs485_1_modemux[] = { 290 static struct spear_modemux rs485_1_modemux[] = {
291 { 291 {
292 .muxregs = rs485_1_muxreg, 292 .muxregs = rs485_1_muxreg,
293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg), 293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
294 }, 294 },
295 }; 295 };
296 296
297 static struct spear_pingroup rs485_1_pingroup = { 297 static struct spear_pingroup rs485_1_pingroup = {
298 .name = "rs485_1_grp", 298 .name = "rs485_1_grp",
299 .pins = rs485_1_pins, 299 .pins = rs485_1_pins,
300 .npins = ARRAY_SIZE(rs485_1_pins), 300 .npins = ARRAY_SIZE(rs485_1_pins),
301 .modemuxs = rs485_1_modemux, 301 .modemuxs = rs485_1_modemux,
302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux), 302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
303 }; 303 };
304 304
305 static const char *const rs485_1_grps[] = { "rs485_1" }; 305 static const char *const rs485_1_grps[] = { "rs485_1" };
306 static struct spear_function rs485_1_function = { 306 static struct spear_function rs485_1_function = {
307 .name = "rs485_1", 307 .name = "rs485_1",
308 .groups = rs485_1_grps, 308 .groups = rs485_1_grps,
309 .ngroups = ARRAY_SIZE(rs485_1_grps), 309 .ngroups = ARRAY_SIZE(rs485_1_grps),
310 }; 310 };
311 311
312 /* tdm_pins */ 312 /* tdm_pins */
313 static const unsigned tdm_pins[] = { 10, 11, 12, 13 }; 313 static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
314 static struct spear_muxreg tdm_muxreg[] = { 314 static struct spear_muxreg tdm_muxreg[] = {
315 { 315 {
316 .reg = PMX_CONFIG_REG, 316 .reg = PMX_CONFIG_REG,
317 .mask = PMX_MII_MASK, 317 .mask = PMX_MII_MASK,
318 .val = 0, 318 .val = 0,
319 }, 319 },
320 }; 320 };
321 321
322 static struct spear_modemux tdm_modemux[] = { 322 static struct spear_modemux tdm_modemux[] = {
323 { 323 {
324 .muxregs = tdm_muxreg, 324 .muxregs = tdm_muxreg,
325 .nmuxregs = ARRAY_SIZE(tdm_muxreg), 325 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
326 }, 326 },
327 }; 327 };
328 328
329 static struct spear_pingroup tdm_pingroup = { 329 static struct spear_pingroup tdm_pingroup = {
330 .name = "tdm_grp", 330 .name = "tdm_grp",
331 .pins = tdm_pins, 331 .pins = tdm_pins,
332 .npins = ARRAY_SIZE(tdm_pins), 332 .npins = ARRAY_SIZE(tdm_pins),
333 .modemuxs = tdm_modemux, 333 .modemuxs = tdm_modemux,
334 .nmodemuxs = ARRAY_SIZE(tdm_modemux), 334 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
335 }; 335 };
336 336
337 static const char *const tdm_grps[] = { "tdm_grp" }; 337 static const char *const tdm_grps[] = { "tdm_grp" };
338 static struct spear_function tdm_function = { 338 static struct spear_function tdm_function = {
339 .name = "tdm", 339 .name = "tdm",
340 .groups = tdm_grps, 340 .groups = tdm_grps,
341 .ngroups = ARRAY_SIZE(tdm_grps), 341 .ngroups = ARRAY_SIZE(tdm_grps),
342 }; 342 };
343 343
344 /* pingroups */ 344 /* pingroups */
345 static struct spear_pingroup *spear310_pingroups[] = { 345 static struct spear_pingroup *spear310_pingroups[] = {
346 SPEAR3XX_COMMON_PINGROUPS, 346 SPEAR3XX_COMMON_PINGROUPS,
347 &emi_cs_0_to_5_pingroup, 347 &emi_cs_0_to_5_pingroup,
348 &uart1_pingroup, 348 &uart1_pingroup,
349 &uart2_pingroup, 349 &uart2_pingroup,
350 &uart3_pingroup, 350 &uart3_pingroup,
351 &uart4_pingroup, 351 &uart4_pingroup,
352 &uart5_pingroup, 352 &uart5_pingroup,
353 &fsmc_pingroup, 353 &fsmc_pingroup,
354 &rs485_0_pingroup, 354 &rs485_0_pingroup,
355 &rs485_1_pingroup, 355 &rs485_1_pingroup,
356 &tdm_pingroup, 356 &tdm_pingroup,
357 }; 357 };
358 358
359 /* functions */ 359 /* functions */
360 static struct spear_function *spear310_functions[] = { 360 static struct spear_function *spear310_functions[] = {
361 SPEAR3XX_COMMON_FUNCTIONS, 361 SPEAR3XX_COMMON_FUNCTIONS,
362 &emi_cs_0_to_5_function, 362 &emi_cs_0_to_5_function,
363 &uart1_function, 363 &uart1_function,
364 &uart2_function, 364 &uart2_function,
365 &uart3_function, 365 &uart3_function,
366 &uart4_function, 366 &uart4_function,
367 &uart5_function, 367 &uart5_function,
368 &fsmc_function, 368 &fsmc_function,
369 &rs485_0_function, 369 &rs485_0_function,
370 &rs485_1_function, 370 &rs485_1_function,
371 &tdm_function, 371 &tdm_function,
372 }; 372 };
373 373
374 static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = { 374 static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
375 { 375 {
376 .compatible = "st,spear310-pinmux", 376 .compatible = "st,spear310-pinmux",
377 }, 377 },
378 {}, 378 {},
379 }; 379 };
380 380
381 static int __devinit spear310_pinctrl_probe(struct platform_device *pdev) 381 static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
382 { 382 {
383 int ret; 383 int ret;
384 384
385 spear3xx_machdata.groups = spear310_pingroups; 385 spear3xx_machdata.groups = spear310_pingroups;
386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); 386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
387 spear3xx_machdata.functions = spear310_functions; 387 spear3xx_machdata.functions = spear310_functions;
388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions); 388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389 389
390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); 390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
391 pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
392 spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
391 393
392 spear3xx_machdata.modes_supported = false; 394 spear3xx_machdata.modes_supported = false;
393 395
394 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); 396 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
395 if (ret) 397 if (ret)
396 return ret; 398 return ret;
397 399
398 return 0; 400 return 0;
399 } 401 }
400 402
401 static int __devexit spear310_pinctrl_remove(struct platform_device *pdev) 403 static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
402 { 404 {
403 return spear_pinctrl_remove(pdev); 405 return spear_pinctrl_remove(pdev);
404 } 406 }
405 407
406 static struct platform_driver spear310_pinctrl_driver = { 408 static struct platform_driver spear310_pinctrl_driver = {
407 .driver = { 409 .driver = {
408 .name = DRIVER_NAME, 410 .name = DRIVER_NAME,
409 .owner = THIS_MODULE, 411 .owner = THIS_MODULE,
410 .of_match_table = spear310_pinctrl_of_match, 412 .of_match_table = spear310_pinctrl_of_match,
411 }, 413 },
412 .probe = spear310_pinctrl_probe, 414 .probe = spear310_pinctrl_probe,
413 .remove = __devexit_p(spear310_pinctrl_remove), 415 .remove = __devexit_p(spear310_pinctrl_remove),
414 }; 416 };
415 417
416 static int __init spear310_pinctrl_init(void) 418 static int __init spear310_pinctrl_init(void)
417 { 419 {
418 return platform_driver_register(&spear310_pinctrl_driver); 420 return platform_driver_register(&spear310_pinctrl_driver);
419 } 421 }
420 arch_initcall(spear310_pinctrl_init); 422 arch_initcall(spear310_pinctrl_init);
421 423
422 static void __exit spear310_pinctrl_exit(void) 424 static void __exit spear310_pinctrl_exit(void)
423 { 425 {
424 platform_driver_unregister(&spear310_pinctrl_driver); 426 platform_driver_unregister(&spear310_pinctrl_driver);
425 } 427 }
426 module_exit(spear310_pinctrl_exit); 428 module_exit(spear310_pinctrl_exit);
427 429
428 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 430 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
429 MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver"); 431 MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
430 MODULE_LICENSE("GPL v2"); 432 MODULE_LICENSE("GPL v2");
431 MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match); 433 MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
432 434
drivers/pinctrl/spear/pinctrl-spear320.c
Diff comments   View file @ f4f8e56
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr320 pinmux 2 * Driver for the ST Microelectronics SPEAr320 pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/err.h> 12 #include <linux/err.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/of_device.h> 15 #include <linux/of_device.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include "pinctrl-spear3xx.h" 17 #include "pinctrl-spear3xx.h"
18 18
19 #define DRIVER_NAME "spear320-pinmux" 19 #define DRIVER_NAME "spear320-pinmux"
20 20
21 /* addresses */ 21 /* addresses */
22 #define PMX_CONFIG_REG 0x0C 22 #define PMX_CONFIG_REG 0x0C
23 #define MODE_CONFIG_REG 0x10 23 #define MODE_CONFIG_REG 0x10
24 #define MODE_EXT_CONFIG_REG 0x18 24 #define MODE_EXT_CONFIG_REG 0x18
25 25
26 /* modes */ 26 /* modes */
27 #define AUTO_NET_SMII_MODE (1 << 0) 27 #define AUTO_NET_SMII_MODE (1 << 0)
28 #define AUTO_NET_MII_MODE (1 << 1) 28 #define AUTO_NET_MII_MODE (1 << 1)
29 #define AUTO_EXP_MODE (1 << 2) 29 #define AUTO_EXP_MODE (1 << 2)
30 #define SMALL_PRINTERS_MODE (1 << 3) 30 #define SMALL_PRINTERS_MODE (1 << 3)
31 #define EXTENDED_MODE (1 << 4) 31 #define EXTENDED_MODE (1 << 4)
32 32
33 static struct spear_pmx_mode pmx_mode_auto_net_smii = { 33 static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34 .name = "Automation Networking SMII mode", 34 .name = "Automation Networking SMII mode",
35 .mode = AUTO_NET_SMII_MODE, 35 .mode = AUTO_NET_SMII_MODE,
36 .reg = MODE_CONFIG_REG, 36 .reg = MODE_CONFIG_REG,
37 .mask = 0x00000007, 37 .mask = 0x00000007,
38 .val = 0x0, 38 .val = 0x0,
39 }; 39 };
40 40
41 static struct spear_pmx_mode pmx_mode_auto_net_mii = { 41 static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42 .name = "Automation Networking MII mode", 42 .name = "Automation Networking MII mode",
43 .mode = AUTO_NET_MII_MODE, 43 .mode = AUTO_NET_MII_MODE,
44 .reg = MODE_CONFIG_REG, 44 .reg = MODE_CONFIG_REG,
45 .mask = 0x00000007, 45 .mask = 0x00000007,
46 .val = 0x1, 46 .val = 0x1,
47 }; 47 };
48 48
49 static struct spear_pmx_mode pmx_mode_auto_exp = { 49 static struct spear_pmx_mode pmx_mode_auto_exp = {
50 .name = "Automation Expanded mode", 50 .name = "Automation Expanded mode",
51 .mode = AUTO_EXP_MODE, 51 .mode = AUTO_EXP_MODE,
52 .reg = MODE_CONFIG_REG, 52 .reg = MODE_CONFIG_REG,
53 .mask = 0x00000007, 53 .mask = 0x00000007,
54 .val = 0x2, 54 .val = 0x2,
55 }; 55 };
56 56
57 static struct spear_pmx_mode pmx_mode_small_printers = { 57 static struct spear_pmx_mode pmx_mode_small_printers = {
58 .name = "Small Printers mode", 58 .name = "Small Printers mode",
59 .mode = SMALL_PRINTERS_MODE, 59 .mode = SMALL_PRINTERS_MODE,
60 .reg = MODE_CONFIG_REG, 60 .reg = MODE_CONFIG_REG,
61 .mask = 0x00000007, 61 .mask = 0x00000007,
62 .val = 0x3, 62 .val = 0x3,
63 }; 63 };
64 64
65 static struct spear_pmx_mode pmx_mode_extended = { 65 static struct spear_pmx_mode pmx_mode_extended = {
66 .name = "extended mode", 66 .name = "extended mode",
67 .mode = EXTENDED_MODE, 67 .mode = EXTENDED_MODE,
68 .reg = MODE_EXT_CONFIG_REG, 68 .reg = MODE_EXT_CONFIG_REG,
69 .mask = 0x00000001, 69 .mask = 0x00000001,
70 .val = 0x1, 70 .val = 0x1,
71 }; 71 };
72 72
73 static struct spear_pmx_mode *spear320_pmx_modes[] = { 73 static struct spear_pmx_mode *spear320_pmx_modes[] = {
74 &pmx_mode_auto_net_smii, 74 &pmx_mode_auto_net_smii,
75 &pmx_mode_auto_net_mii, 75 &pmx_mode_auto_net_mii,
76 &pmx_mode_auto_exp, 76 &pmx_mode_auto_exp,
77 &pmx_mode_small_printers, 77 &pmx_mode_small_printers,
78 &pmx_mode_extended, 78 &pmx_mode_extended,
79 }; 79 };
80 80
81 /* Extended mode registers and their offsets */ 81 /* Extended mode registers and their offsets */
82 #define EXT_CTRL_REG 0x0018 82 #define EXT_CTRL_REG 0x0018
83 #define MII_MDIO_MASK (1 << 4) 83 #define MII_MDIO_MASK (1 << 4)
84 #define MII_MDIO_10_11_VAL 0 84 #define MII_MDIO_10_11_VAL 0
85 #define MII_MDIO_81_VAL (1 << 4) 85 #define MII_MDIO_81_VAL (1 << 4)
86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5) 86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
87 #define MAC_MODE_MII 0 87 #define MAC_MODE_MII 0
88 #define MAC_MODE_RMII 1 88 #define MAC_MODE_RMII 1
89 #define MAC_MODE_SMII 2 89 #define MAC_MODE_SMII 2
90 #define MAC_MODE_SS_SMII 3 90 #define MAC_MODE_SS_SMII 3
91 #define MAC_MODE_MASK 0x3 91 #define MAC_MODE_MASK 0x3
92 #define MAC1_MODE_SHIFT 16 92 #define MAC1_MODE_SHIFT 16
93 #define MAC2_MODE_SHIFT 18 93 #define MAC2_MODE_SHIFT 18
94 94
95 #define IP_SEL_PAD_0_9_REG 0x00A4 95 #define IP_SEL_PAD_0_9_REG 0x00A4
96 #define PMX_PL_0_1_MASK (0x3F << 0) 96 #define PMX_PL_0_1_MASK (0x3F << 0)
97 #define PMX_UART2_PL_0_1_VAL 0x0 97 #define PMX_UART2_PL_0_1_VAL 0x0
98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3)) 98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
99 99
100 #define PMX_PL_2_3_MASK (0x3F << 6) 100 #define PMX_PL_2_3_MASK (0x3F << 6)
101 #define PMX_I2C2_PL_2_3_VAL 0x0 101 #define PMX_I2C2_PL_2_3_VAL 0x0
102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9)) 102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9)) 103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
104 104
105 #define PMX_PL_4_5_MASK (0x3F << 12) 105 #define PMX_PL_4_5_MASK (0x3F << 12)
106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15)) 106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15)) 107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
108 #define PMX_PL_5_MASK (0x7 << 15) 108 #define PMX_PL_5_MASK (0x7 << 15)
109 #define PMX_TOUCH_Y_PL_5_VAL 0x0 109 #define PMX_TOUCH_Y_PL_5_VAL 0x0
110 110
111 #define PMX_PL_6_7_MASK (0x3F << 18) 111 #define PMX_PL_6_7_MASK (0x3F << 18)
112 #define PMX_PL_6_MASK (0x7 << 18) 112 #define PMX_PL_6_MASK (0x7 << 18)
113 #define PMX_PL_7_MASK (0x7 << 21) 113 #define PMX_PL_7_MASK (0x7 << 21)
114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21)) 114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18) 115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21) 116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21)) 117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
118 118
119 #define PMX_PL_8_9_MASK (0x3F << 24) 119 #define PMX_PL_8_9_MASK (0x3F << 24)
120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27)) 120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27)) 121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27)) 122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
123 123
124 #define IP_SEL_PAD_10_19_REG 0x00A8 124 #define IP_SEL_PAD_10_19_REG 0x00A8
125 #define PMX_PL_10_11_MASK (0x3F << 0) 125 #define PMX_PL_10_11_MASK (0x3F << 0)
126 #define PMX_SMII_PL_10_11_VAL 0 126 #define PMX_SMII_PL_10_11_VAL 0
127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3)) 127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
128 128
129 #define PMX_PL_12_MASK (0x7 << 6) 129 #define PMX_PL_12_MASK (0x7 << 6)
130 #define PMX_PWM3_PL_12_VAL 0 130 #define PMX_PWM3_PL_12_VAL 0
131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6) 131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
132 132
133 #define PMX_PL_13_14_MASK (0x3F << 9) 133 #define PMX_PL_13_14_MASK (0x3F << 9)
134 #define PMX_PL_13_MASK (0x7 << 9) 134 #define PMX_PL_13_MASK (0x7 << 9)
135 #define PMX_PL_14_MASK (0x7 << 12) 135 #define PMX_PL_14_MASK (0x7 << 12)
136 #define PMX_SSP2_PL_13_14_15_16_VAL 0 136 #define PMX_SSP2_PL_13_14_15_16_VAL 0
137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12)) 137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12)) 138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
139 #define PMX_PWM2_PL_13_VAL (0x2 << 9) 139 #define PMX_PWM2_PL_13_VAL (0x2 << 9)
140 #define PMX_PWM1_PL_14_VAL (0x2 << 12) 140 #define PMX_PWM1_PL_14_VAL (0x2 << 12)
141 141
142 #define PMX_PL_15_MASK (0x7 << 15) 142 #define PMX_PL_15_MASK (0x7 << 15)
143 #define PMX_PWM0_PL_15_VAL (0x2 << 15) 143 #define PMX_PWM0_PL_15_VAL (0x2 << 15)
144 #define PMX_PL_15_16_MASK (0x3F << 15) 144 #define PMX_PL_15_16_MASK (0x3F << 15)
145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18)) 145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18)) 146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
147 147
148 #define PMX_PL_17_18_MASK (0x3F << 21) 148 #define PMX_PL_17_18_MASK (0x3F << 21)
149 #define PMX_SSP1_PL_17_18_19_20_VAL 0 149 #define PMX_SSP1_PL_17_18_19_20_VAL 0
150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24)) 150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
151 151
152 #define PMX_PL_19_MASK (0x7 << 27) 152 #define PMX_PL_19_MASK (0x7 << 27)
153 #define PMX_I2C2_PL_19_VAL (0x1 << 27) 153 #define PMX_I2C2_PL_19_VAL (0x1 << 27)
154 #define PMX_RMII_PL_19_VAL (0x4 << 27) 154 #define PMX_RMII_PL_19_VAL (0x4 << 27)
155 155
156 #define IP_SEL_PAD_20_29_REG 0x00AC 156 #define IP_SEL_PAD_20_29_REG 0x00AC
157 #define PMX_PL_20_MASK (0x7 << 0) 157 #define PMX_PL_20_MASK (0x7 << 0)
158 #define PMX_I2C2_PL_20_VAL (0x1 << 0) 158 #define PMX_I2C2_PL_20_VAL (0x1 << 0)
159 #define PMX_RMII_PL_20_VAL (0x4 << 0) 159 #define PMX_RMII_PL_20_VAL (0x4 << 0)
160 160
161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3) 161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
162 #define PMX_SMII_PL_21_TO_27_VAL 0 162 #define PMX_SMII_PL_21_TO_27_VAL 0
163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21)) 163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164 164
165 #define PMX_PL_28_29_MASK (0x3F << 24) 165 #define PMX_PL_28_29_MASK (0x3F << 24)
166 #define PMX_PL_28_MASK (0x7 << 24) 166 #define PMX_PL_28_MASK (0x7 << 24)
167 #define PMX_PL_29_MASK (0x7 << 27) 167 #define PMX_PL_29_MASK (0x7 << 27)
168 #define PMX_UART1_PL_28_29_VAL 0 168 #define PMX_UART1_PL_28_29_VAL 0
169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24) 169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27) 170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
171 171
172 #define IP_SEL_PAD_30_39_REG 0x00B0 172 #define IP_SEL_PAD_30_39_REG 0x00B0
173 #define PMX_PL_30_31_MASK (0x3F << 0) 173 #define PMX_PL_30_31_MASK (0x3F << 0)
174 #define PMX_CAN1_PL_30_31_VAL (0) 174 #define PMX_CAN1_PL_30_31_VAL (0)
175 #define PMX_PL_30_MASK (0x7 << 0) 175 #define PMX_PL_30_MASK (0x7 << 0)
176 #define PMX_PL_31_MASK (0x7 << 3) 176 #define PMX_PL_31_MASK (0x7 << 3)
177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0) 177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3) 178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3) 179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
180 180
181 #define PMX_PL_32_33_MASK (0x3F << 6) 181 #define PMX_PL_32_33_MASK (0x3F << 6)
182 #define PMX_CAN0_PL_32_33_VAL 0 182 #define PMX_CAN0_PL_32_33_VAL 0
183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9)) 183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9)) 184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
185 185
186 #define PMX_PL_34_MASK (0x7 << 12) 186 #define PMX_PL_34_MASK (0x7 << 12)
187 #define PMX_PWM2_PL_34_VAL 0 187 #define PMX_PWM2_PL_34_VAL 0
188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12) 188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
189 #define PMX_SSP2_PL_34_VAL (0x4 << 12) 189 #define PMX_SSP2_PL_34_VAL (0x4 << 12)
190 190
191 #define PMX_PL_35_MASK (0x7 << 15) 191 #define PMX_PL_35_MASK (0x7 << 15)
192 #define PMX_I2S_REF_CLK_PL_35_VAL 0 192 #define PMX_I2S_REF_CLK_PL_35_VAL 0
193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15) 193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
194 #define PMX_SSP2_PL_35_VAL (0x4 << 15) 194 #define PMX_SSP2_PL_35_VAL (0x4 << 15)
195 195
196 #define PMX_PL_36_MASK (0x7 << 18) 196 #define PMX_PL_36_MASK (0x7 << 18)
197 #define PMX_TOUCH_X_PL_36_VAL 0 197 #define PMX_TOUCH_X_PL_36_VAL 0
198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18) 198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
199 #define PMX_SSP1_PL_36_VAL (0x4 << 18) 199 #define PMX_SSP1_PL_36_VAL (0x4 << 18)
200 200
201 #define PMX_PL_37_38_MASK (0x3F << 21) 201 #define PMX_PL_37_38_MASK (0x3F << 21)
202 #define PMX_PWM0_1_PL_37_38_VAL 0 202 #define PMX_PWM0_1_PL_37_38_VAL 0
203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24)) 203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24)) 204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
205 205
206 #define PMX_PL_39_MASK (0x7 << 27) 206 #define PMX_PL_39_MASK (0x7 << 27)
207 #define PMX_I2S_PL_39_VAL 0 207 #define PMX_I2S_PL_39_VAL 0
208 #define PMX_UART4_PL_39_VAL (0x2 << 27) 208 #define PMX_UART4_PL_39_VAL (0x2 << 27)
209 #define PMX_SSP1_PL_39_VAL (0x4 << 27) 209 #define PMX_SSP1_PL_39_VAL (0x4 << 27)
210 210
211 #define IP_SEL_PAD_40_49_REG 0x00B4 211 #define IP_SEL_PAD_40_49_REG 0x00B4
212 #define PMX_PL_40_MASK (0x7 << 0) 212 #define PMX_PL_40_MASK (0x7 << 0)
213 #define PMX_I2S_PL_40_VAL 0 213 #define PMX_I2S_PL_40_VAL 0
214 #define PMX_UART4_PL_40_VAL (0x2 << 0) 214 #define PMX_UART4_PL_40_VAL (0x2 << 0)
215 #define PMX_PWM3_PL_40_VAL (0x4 << 0) 215 #define PMX_PWM3_PL_40_VAL (0x4 << 0)
216 216
217 #define PMX_PL_41_42_MASK (0x3F << 3) 217 #define PMX_PL_41_42_MASK (0x3F << 3)
218 #define PMX_PL_41_MASK (0x7 << 3) 218 #define PMX_PL_41_MASK (0x7 << 3)
219 #define PMX_PL_42_MASK (0x7 << 6) 219 #define PMX_PL_42_MASK (0x7 << 6)
220 #define PMX_I2S_PL_41_42_VAL 0 220 #define PMX_I2S_PL_41_42_VAL 0
221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6)) 221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
222 #define PMX_PWM2_PL_41_VAL (0x4 << 3) 222 #define PMX_PWM2_PL_41_VAL (0x4 << 3)
223 #define PMX_PWM1_PL_42_VAL (0x4 << 6) 223 #define PMX_PWM1_PL_42_VAL (0x4 << 6)
224 224
225 #define PMX_PL_43_MASK (0x7 << 9) 225 #define PMX_PL_43_MASK (0x7 << 9)
226 #define PMX_SDHCI_PL_43_VAL 0 226 #define PMX_SDHCI_PL_43_VAL 0
227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9) 227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
228 #define PMX_PWM0_PL_43_VAL (0x4 << 9) 228 #define PMX_PWM0_PL_43_VAL (0x4 << 9)
229 229
230 #define PMX_PL_44_45_MASK (0x3F << 12) 230 #define PMX_PL_44_45_MASK (0x3F << 12)
231 #define PMX_SDHCI_PL_44_45_VAL 0 231 #define PMX_SDHCI_PL_44_45_VAL 0
232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15)) 232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15)) 233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
234 234
235 #define PMX_PL_46_47_MASK (0x3F << 18) 235 #define PMX_PL_46_47_MASK (0x3F << 18)
236 #define PMX_SDHCI_PL_46_47_VAL 0 236 #define PMX_SDHCI_PL_46_47_VAL 0
237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21)) 237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21)) 238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
239 239
240 #define PMX_PL_48_49_MASK (0x3F << 24) 240 #define PMX_PL_48_49_MASK (0x3F << 24)
241 #define PMX_SDHCI_PL_48_49_VAL 0 241 #define PMX_SDHCI_PL_48_49_VAL 0
242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27)) 242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27)) 243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
244 244
245 #define IP_SEL_PAD_50_59_REG 0x00B8 245 #define IP_SEL_PAD_50_59_REG 0x00B8
246 #define PMX_PL_50_51_MASK (0x3F << 0) 246 #define PMX_PL_50_51_MASK (0x3F << 0)
247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3)) 247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3)) 248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
249 #define PMX_PL_50_MASK (0x7 << 0) 249 #define PMX_PL_50_MASK (0x7 << 0)
250 #define PMX_PL_51_MASK (0x7 << 3) 250 #define PMX_PL_51_MASK (0x7 << 3)
251 #define PMX_SDHCI_PL_50_VAL 0 251 #define PMX_SDHCI_PL_50_VAL 0
252 #define PMX_SDHCI_CD_PL_51_VAL 0 252 #define PMX_SDHCI_CD_PL_51_VAL 0
253 253
254 #define PMX_PL_52_53_MASK (0x3F << 6) 254 #define PMX_PL_52_53_MASK (0x3F << 6)
255 #define PMX_FSMC_PL_52_53_VAL 0 255 #define PMX_FSMC_PL_52_53_VAL 0
256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9)) 256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9)) 257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
258 258
259 #define PMX_PL_54_55_56_MASK (0x1FF << 12) 259 #define PMX_PL_54_55_56_MASK (0x1FF << 12)
260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18)) 260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261 261
262 #define PMX_PL_57_MASK (0x7 << 21) 262 #define PMX_PL_57_MASK (0x7 << 21)
263 #define PMX_FSMC_PL_57_VAL 0 263 #define PMX_FSMC_PL_57_VAL 0
264 #define PMX_PWM3_PL_57_VAL (0x4 << 21) 264 #define PMX_PWM3_PL_57_VAL (0x4 << 21)
265 265
266 #define PMX_PL_58_59_MASK (0x3F << 24) 266 #define PMX_PL_58_59_MASK (0x3F << 24)
267 #define PMX_PL_58_MASK (0x7 << 24) 267 #define PMX_PL_58_MASK (0x7 << 24)
268 #define PMX_PL_59_MASK (0x7 << 27) 268 #define PMX_PL_59_MASK (0x7 << 27)
269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27)) 269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
270 #define PMX_PWM2_PL_58_VAL (0x4 << 24) 270 #define PMX_PWM2_PL_58_VAL (0x4 << 24)
271 #define PMX_PWM1_PL_59_VAL (0x4 << 27) 271 #define PMX_PWM1_PL_59_VAL (0x4 << 27)
272 272
273 #define IP_SEL_PAD_60_69_REG 0x00BC 273 #define IP_SEL_PAD_60_69_REG 0x00BC
274 #define PMX_PL_60_MASK (0x7 << 0) 274 #define PMX_PL_60_MASK (0x7 << 0)
275 #define PMX_FSMC_PL_60_VAL 0 275 #define PMX_FSMC_PL_60_VAL 0
276 #define PMX_PWM0_PL_60_VAL (0x4 << 0) 276 #define PMX_PWM0_PL_60_VAL (0x4 << 0)
277 277
278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3) 278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12)) 279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12)) 280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281 281
282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15) 282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24)) 283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24)) 284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285 285
286 #define PMX_PL_69_MASK (0x7 << 27) 286 #define PMX_PL_69_MASK (0x7 << 27)
287 #define PMX_CLCD_PL_69_VAL (0) 287 #define PMX_CLCD_PL_69_VAL (0)
288 #define PMX_EMI_PL_69_VAL (0x2 << 27) 288 #define PMX_EMI_PL_69_VAL (0x2 << 27)
289 #define PMX_SPP_PL_69_VAL (0x3 << 27) 289 #define PMX_SPP_PL_69_VAL (0x3 << 27)
290 #define PMX_UART5_PL_69_VAL (0x4 << 27) 290 #define PMX_UART5_PL_69_VAL (0x4 << 27)
291 291
292 #define IP_SEL_PAD_70_79_REG 0x00C0 292 #define IP_SEL_PAD_70_79_REG 0x00C0
293 #define PMX_PL_70_MASK (0x7 << 0) 293 #define PMX_PL_70_MASK (0x7 << 0)
294 #define PMX_CLCD_PL_70_VAL (0) 294 #define PMX_CLCD_PL_70_VAL (0)
295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0) 295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
296 #define PMX_SPP_PL_70_VAL (0x3 << 0) 296 #define PMX_SPP_PL_70_VAL (0x3 << 0)
297 #define PMX_UART5_PL_70_VAL (0x4 << 0) 297 #define PMX_UART5_PL_70_VAL (0x4 << 0)
298 298
299 #define PMX_PL_71_72_MASK (0x3F << 3) 299 #define PMX_PL_71_72_MASK (0x3F << 3)
300 #define PMX_CLCD_PL_71_72_VAL (0) 300 #define PMX_CLCD_PL_71_72_VAL (0)
301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6)) 301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6)) 302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6)) 303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
304 304
305 #define PMX_PL_73_MASK (0x7 << 9) 305 #define PMX_PL_73_MASK (0x7 << 9)
306 #define PMX_CLCD_PL_73_VAL (0) 306 #define PMX_CLCD_PL_73_VAL (0)
307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9) 307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
308 #define PMX_SPP_PL_73_VAL (0x3 << 9) 308 #define PMX_SPP_PL_73_VAL (0x3 << 9)
309 #define PMX_UART3_PL_73_VAL (0x4 << 9) 309 #define PMX_UART3_PL_73_VAL (0x4 << 9)
310 310
311 #define PMX_PL_74_MASK (0x7 << 12) 311 #define PMX_PL_74_MASK (0x7 << 12)
312 #define PMX_CLCD_PL_74_VAL (0) 312 #define PMX_CLCD_PL_74_VAL (0)
313 #define PMX_EMI_PL_74_VAL (0x2 << 12) 313 #define PMX_EMI_PL_74_VAL (0x2 << 12)
314 #define PMX_SPP_PL_74_VAL (0x3 << 12) 314 #define PMX_SPP_PL_74_VAL (0x3 << 12)
315 #define PMX_UART3_PL_74_VAL (0x4 << 12) 315 #define PMX_UART3_PL_74_VAL (0x4 << 12)
316 316
317 #define PMX_PL_75_76_MASK (0x3F << 15) 317 #define PMX_PL_75_76_MASK (0x3F << 15)
318 #define PMX_CLCD_PL_75_76_VAL (0) 318 #define PMX_CLCD_PL_75_76_VAL (0)
319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18)) 319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18)) 320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18)) 321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
322 322
323 #define PMX_PL_77_78_79_MASK (0x1FF << 21) 323 #define PMX_PL_77_78_79_MASK (0x1FF << 21)
324 #define PMX_CLCD_PL_77_78_79_VAL (0) 324 #define PMX_CLCD_PL_77_78_79_VAL (0)
325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27)) 325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27)) 326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27)) 327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328 328
329 #define IP_SEL_PAD_80_89_REG 0x00C4 329 #define IP_SEL_PAD_80_89_REG 0x00C4
330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0) 330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
331 #define PMX_CLCD_PL_80_TO_85_VAL 0 331 #define PMX_CLCD_PL_80_TO_85_VAL 0
332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15)) 332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15)) 333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15)) 334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15)) 335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336 336
337 #define PMX_PL_86_87_MASK (0x3F << 18) 337 #define PMX_PL_86_87_MASK (0x3F << 18)
338 #define PMX_PL_86_MASK (0x7 << 18) 338 #define PMX_PL_86_MASK (0x7 << 18)
339 #define PMX_PL_87_MASK (0x7 << 21) 339 #define PMX_PL_87_MASK (0x7 << 21)
340 #define PMX_CLCD_PL_86_87_VAL 0 340 #define PMX_CLCD_PL_86_87_VAL 0
341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21)) 341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21)) 342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
343 #define PMX_PWM3_PL_86_VAL (0x4 << 18) 343 #define PMX_PWM3_PL_86_VAL (0x4 << 18)
344 #define PMX_PWM2_PL_87_VAL (0x4 << 21) 344 #define PMX_PWM2_PL_87_VAL (0x4 << 21)
345 345
346 #define PMX_PL_88_89_MASK (0x3F << 24) 346 #define PMX_PL_88_89_MASK (0x3F << 24)
347 #define PMX_CLCD_PL_88_89_VAL 0 347 #define PMX_CLCD_PL_88_89_VAL 0
348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27)) 348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27)) 349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27)) 350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27)) 351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
352 352
353 #define IP_SEL_PAD_90_99_REG 0x00C8 353 #define IP_SEL_PAD_90_99_REG 0x00C8
354 #define PMX_PL_90_91_MASK (0x3F << 0) 354 #define PMX_PL_90_91_MASK (0x3F << 0)
355 #define PMX_CLCD_PL_90_91_VAL 0 355 #define PMX_CLCD_PL_90_91_VAL 0
356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3)) 356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3)) 357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3)) 358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3)) 359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
360 360
361 #define PMX_PL_92_93_MASK (0x3F << 6) 361 #define PMX_PL_92_93_MASK (0x3F << 6)
362 #define PMX_CLCD_PL_92_93_VAL 0 362 #define PMX_CLCD_PL_92_93_VAL 0
363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9)) 363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9)) 364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9)) 365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9)) 366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
367 367
368 #define PMX_PL_94_95_MASK (0x3F << 12) 368 #define PMX_PL_94_95_MASK (0x3F << 12)
369 #define PMX_CLCD_PL_94_95_VAL 0 369 #define PMX_CLCD_PL_94_95_VAL 0
370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15)) 370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15)) 371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15)) 372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15)) 373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
374 374
375 #define PMX_PL_96_97_MASK (0x3F << 18) 375 #define PMX_PL_96_97_MASK (0x3F << 18)
376 #define PMX_CLCD_PL_96_97_VAL 0 376 #define PMX_CLCD_PL_96_97_VAL 0
377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21)) 377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21)) 378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21)) 379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21)) 380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
381 381
382 #define PMX_PL_98_MASK (0x7 << 24) 382 #define PMX_PL_98_MASK (0x7 << 24)
383 #define PMX_CLCD_PL_98_VAL 0 383 #define PMX_CLCD_PL_98_VAL 0
384 #define PMX_I2C1_PL_98_VAL (0x2 << 24) 384 #define PMX_I2C1_PL_98_VAL (0x2 << 24)
385 #define PMX_UART3_PL_98_VAL (0x4 << 24) 385 #define PMX_UART3_PL_98_VAL (0x4 << 24)
386 386
387 #define PMX_PL_99_MASK (0x7 << 27) 387 #define PMX_PL_99_MASK (0x7 << 27)
388 #define PMX_SDHCI_PL_99_VAL 0 388 #define PMX_SDHCI_PL_99_VAL 0
389 #define PMX_I2C1_PL_99_VAL (0x2 << 27) 389 #define PMX_I2C1_PL_99_VAL (0x2 << 27)
390 #define PMX_UART3_PL_99_VAL (0x4 << 27) 390 #define PMX_UART3_PL_99_VAL (0x4 << 27)
391 391
392 #define IP_SEL_MIX_PAD_REG 0x00CC 392 #define IP_SEL_MIX_PAD_REG 0x00CC
393 #define PMX_PL_100_101_MASK (0x3F << 0) 393 #define PMX_PL_100_101_MASK (0x3F << 0)
394 #define PMX_SDHCI_PL_100_101_VAL 0 394 #define PMX_SDHCI_PL_100_101_VAL 0
395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3)) 395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
396 396
397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8) 397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
398 #define PMX_SSP1_PORT_94_TO_97_VAL 0 398 #define PMX_SSP1_PORT_94_TO_97_VAL 0
399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8) 399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8) 400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8) 401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8) 402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
403 403
404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11) 404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
405 #define PMX_SSP2_PORT_90_TO_93_VAL 0 405 #define PMX_SSP2_PORT_90_TO_93_VAL 0
406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11) 406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11) 407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11) 408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11) 409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
410 410
411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14) 411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0 412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14) 413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14) 414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14) 415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
416 416
417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16) 417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
418 #define PMX_UART3_PORT_94_VAL 0 418 #define PMX_UART3_PORT_94_VAL 0
419 #define PMX_UART3_PORT_73_VAL (0x1 << 16) 419 #define PMX_UART3_PORT_73_VAL (0x1 << 16)
420 #define PMX_UART3_PORT_52_VAL (0x2 << 16) 420 #define PMX_UART3_PORT_52_VAL (0x2 << 16)
421 #define PMX_UART3_PORT_41_VAL (0x3 << 16) 421 #define PMX_UART3_PORT_41_VAL (0x3 << 16)
422 #define PMX_UART3_PORT_15_VAL (0x4 << 16) 422 #define PMX_UART3_PORT_15_VAL (0x4 << 16)
423 #define PMX_UART3_PORT_8_VAL (0x5 << 16) 423 #define PMX_UART3_PORT_8_VAL (0x5 << 16)
424 #define PMX_UART3_PORT_99_VAL (0x6 << 16) 424 #define PMX_UART3_PORT_99_VAL (0x6 << 16)
425 425
426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19) 426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
427 #define PMX_UART4_PORT_92_VAL 0 427 #define PMX_UART4_PORT_92_VAL 0
428 #define PMX_UART4_PORT_71_VAL (0x1 << 19) 428 #define PMX_UART4_PORT_71_VAL (0x1 << 19)
429 #define PMX_UART4_PORT_39_VAL (0x2 << 19) 429 #define PMX_UART4_PORT_39_VAL (0x2 << 19)
430 #define PMX_UART4_PORT_13_VAL (0x3 << 19) 430 #define PMX_UART4_PORT_13_VAL (0x3 << 19)
431 #define PMX_UART4_PORT_6_VAL (0x4 << 19) 431 #define PMX_UART4_PORT_6_VAL (0x4 << 19)
432 #define PMX_UART4_PORT_101_VAL (0x5 << 19) 432 #define PMX_UART4_PORT_101_VAL (0x5 << 19)
433 433
434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22) 434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
435 #define PMX_UART5_PORT_90_VAL 0 435 #define PMX_UART5_PORT_90_VAL 0
436 #define PMX_UART5_PORT_69_VAL (0x1 << 22) 436 #define PMX_UART5_PORT_69_VAL (0x1 << 22)
437 #define PMX_UART5_PORT_37_VAL (0x2 << 22) 437 #define PMX_UART5_PORT_37_VAL (0x2 << 22)
438 #define PMX_UART5_PORT_4_VAL (0x3 << 22) 438 #define PMX_UART5_PORT_4_VAL (0x3 << 22)
439 439
440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24) 440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
441 #define PMX_UART6_PORT_88_VAL 0 441 #define PMX_UART6_PORT_88_VAL 0
442 #define PMX_UART6_PORT_2_VAL (0x1 << 24) 442 #define PMX_UART6_PORT_2_VAL (0x1 << 24)
443 443
444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25) 444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
445 #define PMX_I2C1_PORT_8_9_VAL 0 445 #define PMX_I2C1_PORT_8_9_VAL 0
446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25) 446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
447 447
448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26) 448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
449 #define PMX_I2C2_PORT_96_97_VAL 0 449 #define PMX_I2C2_PORT_96_97_VAL 0
450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26) 450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26) 451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26) 452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26) 453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
454 454
455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29) 455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
456 #define PMX_SDHCI_CD_PORT_12_VAL 0 456 #define PMX_SDHCI_CD_PORT_12_VAL 0
457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29) 457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
458 458
459 /* Pad multiplexing for CLCD device */ 459 /* Pad multiplexing for CLCD device */
460 static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 460 static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462 97 }; 462 97 };
463 static struct spear_muxreg clcd_muxreg[] = { 463 static struct spear_muxreg clcd_muxreg[] = {
464 { 464 {
465 .reg = IP_SEL_PAD_60_69_REG, 465 .reg = IP_SEL_PAD_60_69_REG,
466 .mask = PMX_PL_69_MASK, 466 .mask = PMX_PL_69_MASK,
467 .val = PMX_CLCD_PL_69_VAL, 467 .val = PMX_CLCD_PL_69_VAL,
468 }, { 468 }, {
469 .reg = IP_SEL_PAD_70_79_REG, 469 .reg = IP_SEL_PAD_70_79_REG,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | 470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471 PMX_PL_74_MASK | PMX_PL_75_76_MASK | 471 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472 PMX_PL_77_78_79_MASK, 472 PMX_PL_77_78_79_MASK,
473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | 473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL | 474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL, 475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476 }, { 476 }, {
477 .reg = IP_SEL_PAD_80_89_REG, 477 .reg = IP_SEL_PAD_80_89_REG,
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | 478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479 PMX_PL_88_89_MASK, 479 PMX_PL_88_89_MASK,
480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | 480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481 PMX_CLCD_PL_88_89_VAL, 481 PMX_CLCD_PL_88_89_VAL,
482 }, { 482 }, {
483 .reg = IP_SEL_PAD_90_99_REG, 483 .reg = IP_SEL_PAD_90_99_REG,
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | 484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK, 485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | 486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL | 487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488 PMX_CLCD_PL_98_VAL, 488 PMX_CLCD_PL_98_VAL,
489 }, 489 },
490 }; 490 };
491 491
492 static struct spear_modemux clcd_modemux[] = { 492 static struct spear_modemux clcd_modemux[] = {
493 { 493 {
494 .modes = EXTENDED_MODE, 494 .modes = EXTENDED_MODE,
495 .muxregs = clcd_muxreg, 495 .muxregs = clcd_muxreg,
496 .nmuxregs = ARRAY_SIZE(clcd_muxreg), 496 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
497 }, 497 },
498 }; 498 };
499 499
500 static struct spear_pingroup clcd_pingroup = { 500 static struct spear_pingroup clcd_pingroup = {
501 .name = "clcd_grp", 501 .name = "clcd_grp",
502 .pins = clcd_pins, 502 .pins = clcd_pins,
503 .npins = ARRAY_SIZE(clcd_pins), 503 .npins = ARRAY_SIZE(clcd_pins),
504 .modemuxs = clcd_modemux, 504 .modemuxs = clcd_modemux,
505 .nmodemuxs = ARRAY_SIZE(clcd_modemux), 505 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
506 }; 506 };
507 507
508 static const char *const clcd_grps[] = { "clcd_grp" }; 508 static const char *const clcd_grps[] = { "clcd_grp" };
509 static struct spear_function clcd_function = { 509 static struct spear_function clcd_function = {
510 .name = "clcd", 510 .name = "clcd",
511 .groups = clcd_grps, 511 .groups = clcd_grps,
512 .ngroups = ARRAY_SIZE(clcd_grps), 512 .ngroups = ARRAY_SIZE(clcd_grps),
513 }; 513 };
514 514
515 /* Pad multiplexing for EMI (Parallel NOR flash) device */ 515 /* Pad multiplexing for EMI (Parallel NOR flash) device */
516 static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 516 static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519 93, 94, 95, 96, 97 }; 519 93, 94, 95, 96, 97 };
520 static struct spear_muxreg emi_muxreg[] = { 520 static struct spear_muxreg emi_muxreg[] = {
521 { 521 {
522 .reg = PMX_CONFIG_REG, 522 .reg = PMX_CONFIG_REG,
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524 .val = 0, 524 .val = 0,
525 }, 525 },
526 }; 526 };
527 527
528 static struct spear_muxreg emi_ext_muxreg[] = { 528 static struct spear_muxreg emi_ext_muxreg[] = {
529 { 529 {
530 .reg = IP_SEL_PAD_40_49_REG, 530 .reg = IP_SEL_PAD_40_49_REG,
531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, 531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, 532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533 }, { 533 }, {
534 .reg = IP_SEL_PAD_50_59_REG, 534 .reg = IP_SEL_PAD_50_59_REG,
535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | 535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK, 536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | 537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538 PMX_FSMC_EMI_PL_54_55_56_VAL | 538 PMX_FSMC_EMI_PL_54_55_56_VAL |
539 PMX_FSMC_EMI_PL_58_59_VAL, 539 PMX_FSMC_EMI_PL_58_59_VAL,
540 }, { 540 }, {
541 .reg = IP_SEL_PAD_60_69_REG, 541 .reg = IP_SEL_PAD_60_69_REG,
542 .mask = PMX_PL_69_MASK, 542 .mask = PMX_PL_69_MASK,
543 .val = PMX_EMI_PL_69_VAL, 543 .val = PMX_EMI_PL_69_VAL,
544 }, { 544 }, {
545 .reg = IP_SEL_PAD_70_79_REG, 545 .reg = IP_SEL_PAD_70_79_REG,
546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | 546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547 PMX_PL_74_MASK | PMX_PL_75_76_MASK | 547 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548 PMX_PL_77_78_79_MASK, 548 PMX_PL_77_78_79_MASK,
549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | 549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL | 550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL, 551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552 }, { 552 }, {
553 .reg = IP_SEL_PAD_80_89_REG, 553 .reg = IP_SEL_PAD_80_89_REG,
554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | 554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555 PMX_PL_88_89_MASK, 555 PMX_PL_88_89_MASK,
556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | 556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557 PMX_EMI_PL_88_89_VAL, 557 PMX_EMI_PL_88_89_VAL,
558 }, { 558 }, {
559 .reg = IP_SEL_PAD_90_99_REG, 559 .reg = IP_SEL_PAD_90_99_REG,
560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | 560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, 561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | 562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL, 563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564 }, { 564 }, {
565 .reg = EXT_CTRL_REG, 565 .reg = EXT_CTRL_REG,
566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK, 566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567 .val = EMI_FSMC_DYNAMIC_MUX_MASK, 567 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
568 }, 568 },
569 }; 569 };
570 570
571 static struct spear_modemux emi_modemux[] = { 571 static struct spear_modemux emi_modemux[] = {
572 { 572 {
573 .modes = AUTO_EXP_MODE | EXTENDED_MODE, 573 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
574 .muxregs = emi_muxreg, 574 .muxregs = emi_muxreg,
575 .nmuxregs = ARRAY_SIZE(emi_muxreg), 575 .nmuxregs = ARRAY_SIZE(emi_muxreg),
576 }, { 576 }, {
577 .modes = EXTENDED_MODE, 577 .modes = EXTENDED_MODE,
578 .muxregs = emi_ext_muxreg, 578 .muxregs = emi_ext_muxreg,
579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg), 579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580 }, 580 },
581 }; 581 };
582 582
583 static struct spear_pingroup emi_pingroup = { 583 static struct spear_pingroup emi_pingroup = {
584 .name = "emi_grp", 584 .name = "emi_grp",
585 .pins = emi_pins, 585 .pins = emi_pins,
586 .npins = ARRAY_SIZE(emi_pins), 586 .npins = ARRAY_SIZE(emi_pins),
587 .modemuxs = emi_modemux, 587 .modemuxs = emi_modemux,
588 .nmodemuxs = ARRAY_SIZE(emi_modemux), 588 .nmodemuxs = ARRAY_SIZE(emi_modemux),
589 }; 589 };
590 590
591 static const char *const emi_grps[] = { "emi_grp" }; 591 static const char *const emi_grps[] = { "emi_grp" };
592 static struct spear_function emi_function = { 592 static struct spear_function emi_function = {
593 .name = "emi", 593 .name = "emi",
594 .groups = emi_grps, 594 .groups = emi_grps,
595 .ngroups = ARRAY_SIZE(emi_grps), 595 .ngroups = ARRAY_SIZE(emi_grps),
596 }; 596 };
597 597
598 /* Pad multiplexing for FSMC (NAND flash) device */ 598 /* Pad multiplexing for FSMC (NAND flash) device */
599 static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60, 599 static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600 61, 62, 63, 64, 65, 66, 67, 68 }; 600 61, 62, 63, 64, 65, 66, 67, 68 };
601 static struct spear_muxreg fsmc_8bit_muxreg[] = { 601 static struct spear_muxreg fsmc_8bit_muxreg[] = {
602 { 602 {
603 .reg = IP_SEL_PAD_50_59_REG, 603 .reg = IP_SEL_PAD_50_59_REG,
604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | 604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605 PMX_PL_57_MASK | PMX_PL_58_59_MASK, 605 PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | 606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL, 607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608 }, { 608 }, {
609 .reg = IP_SEL_PAD_60_69_REG, 609 .reg = IP_SEL_PAD_60_69_REG,
610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | 610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611 PMX_PL_65_TO_68_MASK, 611 PMX_PL_65_TO_68_MASK,
612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | 612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613 PMX_FSMC_PL_65_TO_68_VAL, 613 PMX_FSMC_PL_65_TO_68_VAL,
614 }, { 614 }, {
615 .reg = EXT_CTRL_REG, 615 .reg = EXT_CTRL_REG,
616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK, 616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617 .val = EMI_FSMC_DYNAMIC_MUX_MASK, 617 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
618 }, 618 },
619 }; 619 };
620 620
621 static struct spear_modemux fsmc_8bit_modemux[] = { 621 static struct spear_modemux fsmc_8bit_modemux[] = {
622 { 622 {
623 .modes = EXTENDED_MODE, 623 .modes = EXTENDED_MODE,
624 .muxregs = fsmc_8bit_muxreg, 624 .muxregs = fsmc_8bit_muxreg,
625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), 625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626 }, 626 },
627 }; 627 };
628 628
629 static struct spear_pingroup fsmc_8bit_pingroup = { 629 static struct spear_pingroup fsmc_8bit_pingroup = {
630 .name = "fsmc_8bit_grp", 630 .name = "fsmc_8bit_grp",
631 .pins = fsmc_8bit_pins, 631 .pins = fsmc_8bit_pins,
632 .npins = ARRAY_SIZE(fsmc_8bit_pins), 632 .npins = ARRAY_SIZE(fsmc_8bit_pins),
633 .modemuxs = fsmc_8bit_modemux, 633 .modemuxs = fsmc_8bit_modemux,
634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), 634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635 }; 635 };
636 636
637 static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56, 637 static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 }; 638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639 static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = { 639 static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640 { 640 {
641 .reg = PMX_CONFIG_REG, 641 .reg = PMX_CONFIG_REG,
642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643 .val = 0, 643 .val = 0,
644 }, 644 },
645 }; 645 };
646 646
647 static struct spear_muxreg fsmc_16bit_muxreg[] = { 647 static struct spear_muxreg fsmc_16bit_muxreg[] = {
648 { 648 {
649 .reg = IP_SEL_PAD_40_49_REG, 649 .reg = IP_SEL_PAD_40_49_REG,
650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, 650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, 651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652 }, { 652 }, {
653 .reg = IP_SEL_PAD_70_79_REG, 653 .reg = IP_SEL_PAD_70_79_REG,
654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, 654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | 655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656 PMX_FSMC_EMI_PL_73_VAL, 656 PMX_FSMC_EMI_PL_73_VAL,
657 } 657 }
658 }; 658 };
659 659
660 static struct spear_modemux fsmc_16bit_modemux[] = { 660 static struct spear_modemux fsmc_16bit_modemux[] = {
661 { 661 {
662 .modes = EXTENDED_MODE, 662 .modes = EXTENDED_MODE,
663 .muxregs = fsmc_8bit_muxreg, 663 .muxregs = fsmc_8bit_muxreg,
664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), 664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665 }, { 665 }, {
666 .modes = AUTO_EXP_MODE | EXTENDED_MODE, 666 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
667 .muxregs = fsmc_16bit_autoexp_muxreg, 667 .muxregs = fsmc_16bit_autoexp_muxreg,
668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg), 668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669 }, { 669 }, {
670 .modes = EXTENDED_MODE, 670 .modes = EXTENDED_MODE,
671 .muxregs = fsmc_16bit_muxreg, 671 .muxregs = fsmc_16bit_muxreg,
672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), 672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673 }, 673 },
674 }; 674 };
675 675
676 static struct spear_pingroup fsmc_16bit_pingroup = { 676 static struct spear_pingroup fsmc_16bit_pingroup = {
677 .name = "fsmc_16bit_grp", 677 .name = "fsmc_16bit_grp",
678 .pins = fsmc_16bit_pins, 678 .pins = fsmc_16bit_pins,
679 .npins = ARRAY_SIZE(fsmc_16bit_pins), 679 .npins = ARRAY_SIZE(fsmc_16bit_pins),
680 .modemuxs = fsmc_16bit_modemux, 680 .modemuxs = fsmc_16bit_modemux,
681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), 681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682 }; 682 };
683 683
684 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" }; 684 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685 static struct spear_function fsmc_function = { 685 static struct spear_function fsmc_function = {
686 .name = "fsmc", 686 .name = "fsmc",
687 .groups = fsmc_grps, 687 .groups = fsmc_grps,
688 .ngroups = ARRAY_SIZE(fsmc_grps), 688 .ngroups = ARRAY_SIZE(fsmc_grps),
689 }; 689 };
690 690
691 /* Pad multiplexing for SPP device */ 691 /* Pad multiplexing for SPP device */
692 static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 692 static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693 80, 81, 82, 83, 84, 85 }; 693 80, 81, 82, 83, 84, 85 };
694 static struct spear_muxreg spp_muxreg[] = { 694 static struct spear_muxreg spp_muxreg[] = {
695 { 695 {
696 .reg = IP_SEL_PAD_60_69_REG, 696 .reg = IP_SEL_PAD_60_69_REG,
697 .mask = PMX_PL_69_MASK, 697 .mask = PMX_PL_69_MASK,
698 .val = PMX_SPP_PL_69_VAL, 698 .val = PMX_SPP_PL_69_VAL,
699 }, { 699 }, {
700 .reg = IP_SEL_PAD_70_79_REG, 700 .reg = IP_SEL_PAD_70_79_REG,
701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | 701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702 PMX_PL_74_MASK | PMX_PL_75_76_MASK | 702 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703 PMX_PL_77_78_79_MASK, 703 PMX_PL_77_78_79_MASK,
704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | 704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL | 705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL, 706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707 }, { 707 }, {
708 .reg = IP_SEL_PAD_80_89_REG, 708 .reg = IP_SEL_PAD_80_89_REG,
709 .mask = PMX_PL_80_TO_85_MASK, 709 .mask = PMX_PL_80_TO_85_MASK,
710 .val = PMX_SPP_PL_80_TO_85_VAL, 710 .val = PMX_SPP_PL_80_TO_85_VAL,
711 }, 711 },
712 }; 712 };
713 713
714 static struct spear_modemux spp_modemux[] = { 714 static struct spear_modemux spp_modemux[] = {
715 { 715 {
716 .modes = EXTENDED_MODE, 716 .modes = EXTENDED_MODE,
717 .muxregs = spp_muxreg, 717 .muxregs = spp_muxreg,
718 .nmuxregs = ARRAY_SIZE(spp_muxreg), 718 .nmuxregs = ARRAY_SIZE(spp_muxreg),
719 }, 719 },
720 }; 720 };
721 721
722 static struct spear_pingroup spp_pingroup = { 722 static struct spear_pingroup spp_pingroup = {
723 .name = "spp_grp", 723 .name = "spp_grp",
724 .pins = spp_pins, 724 .pins = spp_pins,
725 .npins = ARRAY_SIZE(spp_pins), 725 .npins = ARRAY_SIZE(spp_pins),
726 .modemuxs = spp_modemux, 726 .modemuxs = spp_modemux,
727 .nmodemuxs = ARRAY_SIZE(spp_modemux), 727 .nmodemuxs = ARRAY_SIZE(spp_modemux),
728 }; 728 };
729 729
730 static const char *const spp_grps[] = { "spp_grp" }; 730 static const char *const spp_grps[] = { "spp_grp" };
731 static struct spear_function spp_function = { 731 static struct spear_function spp_function = {
732 .name = "spp", 732 .name = "spp",
733 .groups = spp_grps, 733 .groups = spp_grps,
734 .ngroups = ARRAY_SIZE(spp_grps), 734 .ngroups = ARRAY_SIZE(spp_grps),
735 }; 735 };
736 736
737 /* Pad multiplexing for SDHCI device */ 737 /* Pad multiplexing for SDHCI device */
738 static const unsigned sdhci_led_pins[] = { 34 }; 738 static const unsigned sdhci_led_pins[] = { 34 };
739 static struct spear_muxreg sdhci_led_muxreg[] = { 739 static struct spear_muxreg sdhci_led_muxreg[] = {
740 { 740 {
741 .reg = PMX_CONFIG_REG, 741 .reg = PMX_CONFIG_REG,
742 .mask = PMX_SSP_CS_MASK, 742 .mask = PMX_SSP_CS_MASK,
743 .val = 0, 743 .val = 0,
744 }, 744 },
745 }; 745 };
746 746
747 static struct spear_muxreg sdhci_led_ext_muxreg[] = { 747 static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748 { 748 {
749 .reg = IP_SEL_PAD_30_39_REG, 749 .reg = IP_SEL_PAD_30_39_REG,
750 .mask = PMX_PL_34_MASK, 750 .mask = PMX_PL_34_MASK,
751 .val = PMX_PWM2_PL_34_VAL, 751 .val = PMX_PWM2_PL_34_VAL,
752 }, 752 },
753 }; 753 };
754 754
755 static struct spear_modemux sdhci_led_modemux[] = { 755 static struct spear_modemux sdhci_led_modemux[] = {
756 { 756 {
757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758 .muxregs = sdhci_led_muxreg, 758 .muxregs = sdhci_led_muxreg,
759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg), 759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760 }, { 760 }, {
761 .modes = EXTENDED_MODE, 761 .modes = EXTENDED_MODE,
762 .muxregs = sdhci_led_ext_muxreg, 762 .muxregs = sdhci_led_ext_muxreg,
763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg), 763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764 }, 764 },
765 }; 765 };
766 766
767 static struct spear_pingroup sdhci_led_pingroup = { 767 static struct spear_pingroup sdhci_led_pingroup = {
768 .name = "sdhci_led_grp", 768 .name = "sdhci_led_grp",
769 .pins = sdhci_led_pins, 769 .pins = sdhci_led_pins,
770 .npins = ARRAY_SIZE(sdhci_led_pins), 770 .npins = ARRAY_SIZE(sdhci_led_pins),
771 .modemuxs = sdhci_led_modemux, 771 .modemuxs = sdhci_led_modemux,
772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux), 772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773 }; 773 };
774 774
775 static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49, 775 static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776 50}; 776 50};
777 static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51 777 static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778 }; 778 };
779 static struct spear_muxreg sdhci_muxreg[] = { 779 static struct spear_muxreg sdhci_muxreg[] = {
780 { 780 {
781 .reg = PMX_CONFIG_REG, 781 .reg = PMX_CONFIG_REG,
782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783 .val = 0, 783 .val = 0,
784 }, 784 },
785 }; 785 };
786 786
787 static struct spear_muxreg sdhci_ext_muxreg[] = { 787 static struct spear_muxreg sdhci_ext_muxreg[] = {
788 { 788 {
789 .reg = IP_SEL_PAD_40_49_REG, 789 .reg = IP_SEL_PAD_40_49_REG,
790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | 790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791 PMX_PL_48_49_MASK, 791 PMX_PL_48_49_MASK,
792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | 792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL, 793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794 }, { 794 }, {
795 .reg = IP_SEL_PAD_50_59_REG, 795 .reg = IP_SEL_PAD_50_59_REG,
796 .mask = PMX_PL_50_MASK, 796 .mask = PMX_PL_50_MASK,
797 .val = PMX_SDHCI_PL_50_VAL, 797 .val = PMX_SDHCI_PL_50_VAL,
798 }, { 798 }, {
799 .reg = IP_SEL_PAD_90_99_REG, 799 .reg = IP_SEL_PAD_90_99_REG,
800 .mask = PMX_PL_99_MASK, 800 .mask = PMX_PL_99_MASK,
801 .val = PMX_SDHCI_PL_99_VAL, 801 .val = PMX_SDHCI_PL_99_VAL,
802 }, { 802 }, {
803 .reg = IP_SEL_MIX_PAD_REG, 803 .reg = IP_SEL_MIX_PAD_REG,
804 .mask = PMX_PL_100_101_MASK, 804 .mask = PMX_PL_100_101_MASK,
805 .val = PMX_SDHCI_PL_100_101_VAL, 805 .val = PMX_SDHCI_PL_100_101_VAL,
806 }, 806 },
807 }; 807 };
808 808
809 static struct spear_muxreg sdhci_cd_12_muxreg[] = { 809 static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810 { 810 {
811 .reg = PMX_CONFIG_REG, 811 .reg = PMX_CONFIG_REG,
812 .mask = PMX_MII_MASK, 812 .mask = PMX_MII_MASK,
813 .val = 0, 813 .val = 0,
814 }, { 814 }, {
815 .reg = IP_SEL_PAD_10_19_REG, 815 .reg = IP_SEL_PAD_10_19_REG,
816 .mask = PMX_PL_12_MASK, 816 .mask = PMX_PL_12_MASK,
817 .val = PMX_SDHCI_CD_PL_12_VAL, 817 .val = PMX_SDHCI_CD_PL_12_VAL,
818 }, { 818 }, {
819 .reg = IP_SEL_MIX_PAD_REG, 819 .reg = IP_SEL_MIX_PAD_REG,
820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK, 820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821 .val = PMX_SDHCI_CD_PORT_12_VAL, 821 .val = PMX_SDHCI_CD_PORT_12_VAL,
822 }, 822 },
823 }; 823 };
824 824
825 static struct spear_muxreg sdhci_cd_51_muxreg[] = { 825 static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826 { 826 {
827 .reg = IP_SEL_PAD_50_59_REG, 827 .reg = IP_SEL_PAD_50_59_REG,
828 .mask = PMX_PL_51_MASK, 828 .mask = PMX_PL_51_MASK,
829 .val = PMX_SDHCI_CD_PL_51_VAL, 829 .val = PMX_SDHCI_CD_PL_51_VAL,
830 }, { 830 }, {
831 .reg = IP_SEL_MIX_PAD_REG, 831 .reg = IP_SEL_MIX_PAD_REG,
832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK, 832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833 .val = PMX_SDHCI_CD_PORT_51_VAL, 833 .val = PMX_SDHCI_CD_PORT_51_VAL,
834 }, 834 },
835 }; 835 };
836 836
837 #define pmx_sdhci_common_modemux \ 837 #define pmx_sdhci_common_modemux \
838 { \ 838 { \
839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \ 839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \ 840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \
841 .muxregs = sdhci_muxreg, \ 841 .muxregs = sdhci_muxreg, \
842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \ 842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
843 }, { \ 843 }, { \
844 .modes = EXTENDED_MODE, \ 844 .modes = EXTENDED_MODE, \
845 .muxregs = sdhci_ext_muxreg, \ 845 .muxregs = sdhci_ext_muxreg, \
846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \ 846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
847 } 847 }
848 848
849 static struct spear_modemux sdhci_modemux[][3] = { 849 static struct spear_modemux sdhci_modemux[][3] = {
850 { 850 {
851 /* select pin 12 for cd */ 851 /* select pin 12 for cd */
852 pmx_sdhci_common_modemux, 852 pmx_sdhci_common_modemux,
853 { 853 {
854 .modes = EXTENDED_MODE, 854 .modes = EXTENDED_MODE,
855 .muxregs = sdhci_cd_12_muxreg, 855 .muxregs = sdhci_cd_12_muxreg,
856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg), 856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857 }, 857 },
858 }, { 858 }, {
859 /* select pin 51 for cd */ 859 /* select pin 51 for cd */
860 pmx_sdhci_common_modemux, 860 pmx_sdhci_common_modemux,
861 { 861 {
862 .modes = EXTENDED_MODE, 862 .modes = EXTENDED_MODE,
863 .muxregs = sdhci_cd_51_muxreg, 863 .muxregs = sdhci_cd_51_muxreg,
864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg), 864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865 }, 865 },
866 } 866 }
867 }; 867 };
868 868
869 static struct spear_pingroup sdhci_pingroup[] = { 869 static struct spear_pingroup sdhci_pingroup[] = {
870 { 870 {
871 .name = "sdhci_cd_12_grp", 871 .name = "sdhci_cd_12_grp",
872 .pins = sdhci_cd_12_pins, 872 .pins = sdhci_cd_12_pins,
873 .npins = ARRAY_SIZE(sdhci_cd_12_pins), 873 .npins = ARRAY_SIZE(sdhci_cd_12_pins),
874 .modemuxs = sdhci_modemux[0], 874 .modemuxs = sdhci_modemux[0],
875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]), 875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876 }, { 876 }, {
877 .name = "sdhci_cd_51_grp", 877 .name = "sdhci_cd_51_grp",
878 .pins = sdhci_cd_51_pins, 878 .pins = sdhci_cd_51_pins,
879 .npins = ARRAY_SIZE(sdhci_cd_51_pins), 879 .npins = ARRAY_SIZE(sdhci_cd_51_pins),
880 .modemuxs = sdhci_modemux[1], 880 .modemuxs = sdhci_modemux[1],
881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]), 881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882 }, 882 },
883 }; 883 };
884 884
885 static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp", 885 static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886 "sdhci_led_grp" }; 886 "sdhci_led_grp" };
887 887
888 static struct spear_function sdhci_function = { 888 static struct spear_function sdhci_function = {
889 .name = "sdhci", 889 .name = "sdhci",
890 .groups = sdhci_grps, 890 .groups = sdhci_grps,
891 .ngroups = ARRAY_SIZE(sdhci_grps), 891 .ngroups = ARRAY_SIZE(sdhci_grps),
892 }; 892 };
893 893
894 /* Pad multiplexing for I2S device */ 894 /* Pad multiplexing for I2S device */
895 static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 }; 895 static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896 static struct spear_muxreg i2s_muxreg[] = { 896 static struct spear_muxreg i2s_muxreg[] = {
897 { 897 {
898 .reg = PMX_CONFIG_REG, 898 .reg = PMX_CONFIG_REG,
899 .mask = PMX_SSP_CS_MASK, 899 .mask = PMX_SSP_CS_MASK,
900 .val = 0, 900 .val = 0,
901 }, { 901 }, {
902 .reg = PMX_CONFIG_REG, 902 .reg = PMX_CONFIG_REG,
903 .mask = PMX_UART0_MODEM_MASK, 903 .mask = PMX_UART0_MODEM_MASK,
904 .val = 0, 904 .val = 0,
905 }, 905 },
906 }; 906 };
907 907
908 static struct spear_muxreg i2s_ext_muxreg[] = { 908 static struct spear_muxreg i2s_ext_muxreg[] = {
909 { 909 {
910 .reg = IP_SEL_PAD_30_39_REG, 910 .reg = IP_SEL_PAD_30_39_REG,
911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, 911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, 912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913 }, { 913 }, {
914 .reg = IP_SEL_PAD_40_49_REG, 914 .reg = IP_SEL_PAD_40_49_REG,
915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, 915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, 916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917 }, 917 },
918 }; 918 };
919 919
920 static struct spear_modemux i2s_modemux[] = { 920 static struct spear_modemux i2s_modemux[] = {
921 { 921 {
922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923 .muxregs = i2s_muxreg, 923 .muxregs = i2s_muxreg,
924 .nmuxregs = ARRAY_SIZE(i2s_muxreg), 924 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
925 }, { 925 }, {
926 .modes = EXTENDED_MODE, 926 .modes = EXTENDED_MODE,
927 .muxregs = i2s_ext_muxreg, 927 .muxregs = i2s_ext_muxreg,
928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg), 928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929 }, 929 },
930 }; 930 };
931 931
932 static struct spear_pingroup i2s_pingroup = { 932 static struct spear_pingroup i2s_pingroup = {
933 .name = "i2s_grp", 933 .name = "i2s_grp",
934 .pins = i2s_pins, 934 .pins = i2s_pins,
935 .npins = ARRAY_SIZE(i2s_pins), 935 .npins = ARRAY_SIZE(i2s_pins),
936 .modemuxs = i2s_modemux, 936 .modemuxs = i2s_modemux,
937 .nmodemuxs = ARRAY_SIZE(i2s_modemux), 937 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
938 }; 938 };
939 939
940 static const char *const i2s_grps[] = { "i2s_grp" }; 940 static const char *const i2s_grps[] = { "i2s_grp" };
941 static struct spear_function i2s_function = { 941 static struct spear_function i2s_function = {
942 .name = "i2s", 942 .name = "i2s",
943 .groups = i2s_grps, 943 .groups = i2s_grps,
944 .ngroups = ARRAY_SIZE(i2s_grps), 944 .ngroups = ARRAY_SIZE(i2s_grps),
945 }; 945 };
946 946
947 /* Pad multiplexing for UART1 device */ 947 /* Pad multiplexing for UART1 device */
948 static const unsigned uart1_pins[] = { 28, 29 }; 948 static const unsigned uart1_pins[] = { 28, 29 };
949 static struct spear_muxreg uart1_muxreg[] = { 949 static struct spear_muxreg uart1_muxreg[] = {
950 { 950 {
951 .reg = PMX_CONFIG_REG, 951 .reg = PMX_CONFIG_REG,
952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, 952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953 .val = 0, 953 .val = 0,
954 }, 954 },
955 }; 955 };
956 956
957 static struct spear_muxreg uart1_ext_muxreg[] = { 957 static struct spear_muxreg uart1_ext_muxreg[] = {
958 { 958 {
959 .reg = IP_SEL_PAD_20_29_REG, 959 .reg = IP_SEL_PAD_20_29_REG,
960 .mask = PMX_PL_28_29_MASK, 960 .mask = PMX_PL_28_29_MASK,
961 .val = PMX_UART1_PL_28_29_VAL, 961 .val = PMX_UART1_PL_28_29_VAL,
962 }, 962 },
963 }; 963 };
964 964
965 static struct spear_modemux uart1_modemux[] = { 965 static struct spear_modemux uart1_modemux[] = {
966 { 966 {
967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968 | SMALL_PRINTERS_MODE | EXTENDED_MODE, 968 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
969 .muxregs = uart1_muxreg, 969 .muxregs = uart1_muxreg,
970 .nmuxregs = ARRAY_SIZE(uart1_muxreg), 970 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
971 }, { 971 }, {
972 .modes = EXTENDED_MODE, 972 .modes = EXTENDED_MODE,
973 .muxregs = uart1_ext_muxreg, 973 .muxregs = uart1_ext_muxreg,
974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg), 974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975 }, 975 },
976 }; 976 };
977 977
978 static struct spear_pingroup uart1_pingroup = { 978 static struct spear_pingroup uart1_pingroup = {
979 .name = "uart1_grp", 979 .name = "uart1_grp",
980 .pins = uart1_pins, 980 .pins = uart1_pins,
981 .npins = ARRAY_SIZE(uart1_pins), 981 .npins = ARRAY_SIZE(uart1_pins),
982 .modemuxs = uart1_modemux, 982 .modemuxs = uart1_modemux,
983 .nmodemuxs = ARRAY_SIZE(uart1_modemux), 983 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
984 }; 984 };
985 985
986 static const char *const uart1_grps[] = { "uart1_grp" }; 986 static const char *const uart1_grps[] = { "uart1_grp" };
987 static struct spear_function uart1_function = { 987 static struct spear_function uart1_function = {
988 .name = "uart1", 988 .name = "uart1",
989 .groups = uart1_grps, 989 .groups = uart1_grps,
990 .ngroups = ARRAY_SIZE(uart1_grps), 990 .ngroups = ARRAY_SIZE(uart1_grps),
991 }; 991 };
992 992
993 /* Pad multiplexing for UART1 Modem device */ 993 /* Pad multiplexing for UART1 Modem device */
994 static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 }; 994 static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995 static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 }; 995 static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996 static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 }; 996 static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997 static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 }; 997 static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998 998
999 static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = { 999 static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000 { 1000 {
1001 .reg = PMX_CONFIG_REG, 1001 .reg = PMX_CONFIG_REG,
1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, 1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003 .val = 0, 1003 .val = 0,
1004 }, { 1004 }, {
1005 .reg = IP_SEL_PAD_0_9_REG, 1005 .reg = IP_SEL_PAD_0_9_REG,
1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, 1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | 1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008 PMX_UART1_ENH_PL_6_7_VAL, 1008 PMX_UART1_ENH_PL_6_7_VAL,
1009 }, { 1009 }, {
1010 .reg = IP_SEL_MIX_PAD_REG, 1010 .reg = IP_SEL_MIX_PAD_REG,
1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, 1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013 }, 1013 },
1014 }; 1014 };
1015 1015
1016 static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = { 1016 static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017 { 1017 {
1018 .reg = PMX_CONFIG_REG, 1018 .reg = PMX_CONFIG_REG,
1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | 1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, 1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021 .val = 0, 1021 .val = 0,
1022 }, 1022 },
1023 }; 1023 };
1024 1024
1025 static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = { 1025 static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026 { 1026 {
1027 .reg = IP_SEL_PAD_30_39_REG, 1027 .reg = IP_SEL_PAD_30_39_REG,
1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | 1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029 PMX_PL_35_MASK | PMX_PL_36_MASK, 1029 PMX_PL_35_MASK | PMX_PL_36_MASK,
1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | 1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | 1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032 PMX_UART1_ENH_PL_36_VAL, 1032 PMX_UART1_ENH_PL_36_VAL,
1033 }, { 1033 }, {
1034 .reg = IP_SEL_MIX_PAD_REG, 1034 .reg = IP_SEL_MIX_PAD_REG,
1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, 1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037 }, 1037 },
1038 }; 1038 };
1039 1039
1040 static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = { 1040 static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041 { 1041 {
1042 .reg = PMX_CONFIG_REG, 1042 .reg = PMX_CONFIG_REG,
1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | 1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044 PMX_SSP_CS_MASK, 1044 PMX_SSP_CS_MASK,
1045 .val = 0, 1045 .val = 0,
1046 }, 1046 },
1047 }; 1047 };
1048 1048
1049 static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = { 1049 static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050 { 1050 {
1051 .reg = IP_SEL_PAD_30_39_REG, 1051 .reg = IP_SEL_PAD_30_39_REG,
1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, 1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | 1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054 PMX_UART1_ENH_PL_36_VAL, 1054 PMX_UART1_ENH_PL_36_VAL,
1055 }, { 1055 }, {
1056 .reg = IP_SEL_PAD_40_49_REG, 1056 .reg = IP_SEL_PAD_40_49_REG,
1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, 1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, 1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059 }, { 1059 }, {
1060 .reg = IP_SEL_MIX_PAD_REG, 1060 .reg = IP_SEL_MIX_PAD_REG,
1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, 1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063 }, 1063 },
1064 }; 1064 };
1065 1065
1066 static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = { 1066 static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067 { 1067 {
1068 .reg = IP_SEL_PAD_80_89_REG, 1068 .reg = IP_SEL_PAD_80_89_REG,
1069 .mask = PMX_PL_80_TO_85_MASK, 1069 .mask = PMX_PL_80_TO_85_MASK,
1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL, 1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071 }, { 1071 }, {
1072 .reg = IP_SEL_PAD_40_49_REG, 1072 .reg = IP_SEL_PAD_40_49_REG,
1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, 1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, 1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075 }, { 1075 }, {
1076 .reg = IP_SEL_MIX_PAD_REG, 1076 .reg = IP_SEL_MIX_PAD_REG,
1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK, 1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, 1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079 }, 1079 },
1080 }; 1080 };
1081 1081
1082 static struct spear_modemux uart1_modem_2_to_7_modemux[] = { 1082 static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083 { 1083 {
1084 .modes = EXTENDED_MODE, 1084 .modes = EXTENDED_MODE,
1085 .muxregs = uart1_modem_ext_2_to_7_muxreg, 1085 .muxregs = uart1_modem_ext_2_to_7_muxreg,
1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg), 1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087 }, 1087 },
1088 }; 1088 };
1089 1089
1090 static struct spear_modemux uart1_modem_31_to_36_modemux[] = { 1090 static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091 { 1091 {
1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE, 1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093 .muxregs = uart1_modem_31_to_36_muxreg, 1093 .muxregs = uart1_modem_31_to_36_muxreg,
1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg), 1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095 }, { 1095 }, {
1096 .modes = EXTENDED_MODE, 1096 .modes = EXTENDED_MODE,
1097 .muxregs = uart1_modem_ext_31_to_36_muxreg, 1097 .muxregs = uart1_modem_ext_31_to_36_muxreg,
1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg), 1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099 }, 1099 },
1100 }; 1100 };
1101 1101
1102 static struct spear_modemux uart1_modem_34_to_45_modemux[] = { 1102 static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103 { 1103 {
1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE, 1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105 .muxregs = uart1_modem_34_to_45_muxreg, 1105 .muxregs = uart1_modem_34_to_45_muxreg,
1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg), 1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107 }, { 1107 }, {
1108 .modes = EXTENDED_MODE, 1108 .modes = EXTENDED_MODE,
1109 .muxregs = uart1_modem_ext_34_to_45_muxreg, 1109 .muxregs = uart1_modem_ext_34_to_45_muxreg,
1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg), 1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111 }, 1111 },
1112 }; 1112 };
1113 1113
1114 static struct spear_modemux uart1_modem_80_to_85_modemux[] = { 1114 static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115 { 1115 {
1116 .modes = EXTENDED_MODE, 1116 .modes = EXTENDED_MODE,
1117 .muxregs = uart1_modem_ext_80_to_85_muxreg, 1117 .muxregs = uart1_modem_ext_80_to_85_muxreg,
1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg), 1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119 }, 1119 },
1120 }; 1120 };
1121 1121
1122 static struct spear_pingroup uart1_modem_pingroup[] = { 1122 static struct spear_pingroup uart1_modem_pingroup[] = {
1123 { 1123 {
1124 .name = "uart1_modem_2_to_7_grp", 1124 .name = "uart1_modem_2_to_7_grp",
1125 .pins = uart1_modem_2_to_7_pins, 1125 .pins = uart1_modem_2_to_7_pins,
1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins), 1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127 .modemuxs = uart1_modem_2_to_7_modemux, 1127 .modemuxs = uart1_modem_2_to_7_modemux,
1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux), 1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129 }, { 1129 }, {
1130 .name = "uart1_modem_31_to_36_grp", 1130 .name = "uart1_modem_31_to_36_grp",
1131 .pins = uart1_modem_31_to_36_pins, 1131 .pins = uart1_modem_31_to_36_pins,
1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins), 1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133 .modemuxs = uart1_modem_31_to_36_modemux, 1133 .modemuxs = uart1_modem_31_to_36_modemux,
1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux), 1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135 }, { 1135 }, {
1136 .name = "uart1_modem_34_to_45_grp", 1136 .name = "uart1_modem_34_to_45_grp",
1137 .pins = uart1_modem_34_to_45_pins, 1137 .pins = uart1_modem_34_to_45_pins,
1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins), 1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139 .modemuxs = uart1_modem_34_to_45_modemux, 1139 .modemuxs = uart1_modem_34_to_45_modemux,
1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux), 1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141 }, { 1141 }, {
1142 .name = "uart1_modem_80_to_85_grp", 1142 .name = "uart1_modem_80_to_85_grp",
1143 .pins = uart1_modem_80_to_85_pins, 1143 .pins = uart1_modem_80_to_85_pins,
1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins), 1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145 .modemuxs = uart1_modem_80_to_85_modemux, 1145 .modemuxs = uart1_modem_80_to_85_modemux,
1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux), 1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147 }, 1147 },
1148 }; 1148 };
1149 1149
1150 static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp", 1150 static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp", 1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152 "uart1_modem_80_to_85_grp" }; 1152 "uart1_modem_80_to_85_grp" };
1153 static struct spear_function uart1_modem_function = { 1153 static struct spear_function uart1_modem_function = {
1154 .name = "uart1_modem", 1154 .name = "uart1_modem",
1155 .groups = uart1_modem_grps, 1155 .groups = uart1_modem_grps,
1156 .ngroups = ARRAY_SIZE(uart1_modem_grps), 1156 .ngroups = ARRAY_SIZE(uart1_modem_grps),
1157 }; 1157 };
1158 1158
1159 /* Pad multiplexing for UART2 device */ 1159 /* Pad multiplexing for UART2 device */
1160 static const unsigned uart2_pins[] = { 0, 1 }; 1160 static const unsigned uart2_pins[] = { 0, 1 };
1161 static struct spear_muxreg uart2_muxreg[] = { 1161 static struct spear_muxreg uart2_muxreg[] = {
1162 { 1162 {
1163 .reg = PMX_CONFIG_REG, 1163 .reg = PMX_CONFIG_REG,
1164 .mask = PMX_FIRDA_MASK, 1164 .mask = PMX_FIRDA_MASK,
1165 .val = 0, 1165 .val = 0,
1166 }, 1166 },
1167 }; 1167 };
1168 1168
1169 static struct spear_muxreg uart2_ext_muxreg[] = { 1169 static struct spear_muxreg uart2_ext_muxreg[] = {
1170 { 1170 {
1171 .reg = IP_SEL_PAD_0_9_REG, 1171 .reg = IP_SEL_PAD_0_9_REG,
1172 .mask = PMX_PL_0_1_MASK, 1172 .mask = PMX_PL_0_1_MASK,
1173 .val = PMX_UART2_PL_0_1_VAL, 1173 .val = PMX_UART2_PL_0_1_VAL,
1174 }, 1174 },
1175 }; 1175 };
1176 1176
1177 static struct spear_modemux uart2_modemux[] = { 1177 static struct spear_modemux uart2_modemux[] = {
1178 { 1178 {
1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE, 1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181 .muxregs = uart2_muxreg, 1181 .muxregs = uart2_muxreg,
1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg), 1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183 }, { 1183 }, {
1184 .modes = EXTENDED_MODE, 1184 .modes = EXTENDED_MODE,
1185 .muxregs = uart2_ext_muxreg, 1185 .muxregs = uart2_ext_muxreg,
1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg), 1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187 }, 1187 },
1188 }; 1188 };
1189 1189
1190 static struct spear_pingroup uart2_pingroup = { 1190 static struct spear_pingroup uart2_pingroup = {
1191 .name = "uart2_grp", 1191 .name = "uart2_grp",
1192 .pins = uart2_pins, 1192 .pins = uart2_pins,
1193 .npins = ARRAY_SIZE(uart2_pins), 1193 .npins = ARRAY_SIZE(uart2_pins),
1194 .modemuxs = uart2_modemux, 1194 .modemuxs = uart2_modemux,
1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux), 1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196 }; 1196 };
1197 1197
1198 static const char *const uart2_grps[] = { "uart2_grp" }; 1198 static const char *const uart2_grps[] = { "uart2_grp" };
1199 static struct spear_function uart2_function = { 1199 static struct spear_function uart2_function = {
1200 .name = "uart2", 1200 .name = "uart2",
1201 .groups = uart2_grps, 1201 .groups = uart2_grps,
1202 .ngroups = ARRAY_SIZE(uart2_grps), 1202 .ngroups = ARRAY_SIZE(uart2_grps),
1203 }; 1203 };
1204 1204
1205 /* Pad multiplexing for uart3 device */ 1205 /* Pad multiplexing for uart3 device */
1206 static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 }, 1206 static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } }; 1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208 1208
1209 static struct spear_muxreg uart3_ext_8_9_muxreg[] = { 1209 static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210 { 1210 {
1211 .reg = PMX_CONFIG_REG, 1211 .reg = PMX_CONFIG_REG,
1212 .mask = PMX_SSP_MASK, 1212 .mask = PMX_SSP_MASK,
1213 .val = 0, 1213 .val = 0,
1214 }, { 1214 }, {
1215 .reg = IP_SEL_PAD_0_9_REG, 1215 .reg = IP_SEL_PAD_0_9_REG,
1216 .mask = PMX_PL_8_9_MASK, 1216 .mask = PMX_PL_8_9_MASK,
1217 .val = PMX_UART3_PL_8_9_VAL, 1217 .val = PMX_UART3_PL_8_9_VAL,
1218 }, { 1218 }, {
1219 .reg = IP_SEL_MIX_PAD_REG, 1219 .reg = IP_SEL_MIX_PAD_REG,
1220 .mask = PMX_UART3_PORT_SEL_MASK, 1220 .mask = PMX_UART3_PORT_SEL_MASK,
1221 .val = PMX_UART3_PORT_8_VAL, 1221 .val = PMX_UART3_PORT_8_VAL,
1222 }, 1222 },
1223 }; 1223 };
1224 1224
1225 static struct spear_muxreg uart3_ext_15_16_muxreg[] = { 1225 static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226 { 1226 {
1227 .reg = PMX_CONFIG_REG, 1227 .reg = PMX_CONFIG_REG,
1228 .mask = PMX_MII_MASK, 1228 .mask = PMX_MII_MASK,
1229 .val = 0, 1229 .val = 0,
1230 }, { 1230 }, {
1231 .reg = IP_SEL_PAD_10_19_REG, 1231 .reg = IP_SEL_PAD_10_19_REG,
1232 .mask = PMX_PL_15_16_MASK, 1232 .mask = PMX_PL_15_16_MASK,
1233 .val = PMX_UART3_PL_15_16_VAL, 1233 .val = PMX_UART3_PL_15_16_VAL,
1234 }, { 1234 }, {
1235 .reg = IP_SEL_MIX_PAD_REG, 1235 .reg = IP_SEL_MIX_PAD_REG,
1236 .mask = PMX_UART3_PORT_SEL_MASK, 1236 .mask = PMX_UART3_PORT_SEL_MASK,
1237 .val = PMX_UART3_PORT_15_VAL, 1237 .val = PMX_UART3_PORT_15_VAL,
1238 }, 1238 },
1239 }; 1239 };
1240 1240
1241 static struct spear_muxreg uart3_ext_41_42_muxreg[] = { 1241 static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242 { 1242 {
1243 .reg = PMX_CONFIG_REG, 1243 .reg = PMX_CONFIG_REG,
1244 .mask = PMX_UART0_MODEM_MASK, 1244 .mask = PMX_UART0_MODEM_MASK,
1245 .val = 0, 1245 .val = 0,
1246 }, { 1246 }, {
1247 .reg = IP_SEL_PAD_40_49_REG, 1247 .reg = IP_SEL_PAD_40_49_REG,
1248 .mask = PMX_PL_41_42_MASK, 1248 .mask = PMX_PL_41_42_MASK,
1249 .val = PMX_UART3_PL_41_42_VAL, 1249 .val = PMX_UART3_PL_41_42_VAL,
1250 }, { 1250 }, {
1251 .reg = IP_SEL_MIX_PAD_REG, 1251 .reg = IP_SEL_MIX_PAD_REG,
1252 .mask = PMX_UART3_PORT_SEL_MASK, 1252 .mask = PMX_UART3_PORT_SEL_MASK,
1253 .val = PMX_UART3_PORT_41_VAL, 1253 .val = PMX_UART3_PORT_41_VAL,
1254 }, 1254 },
1255 }; 1255 };
1256 1256
1257 static struct spear_muxreg uart3_ext_52_53_muxreg[] = { 1257 static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258 { 1258 {
1259 .reg = IP_SEL_PAD_50_59_REG, 1259 .reg = IP_SEL_PAD_50_59_REG,
1260 .mask = PMX_PL_52_53_MASK, 1260 .mask = PMX_PL_52_53_MASK,
1261 .val = PMX_UART3_PL_52_53_VAL, 1261 .val = PMX_UART3_PL_52_53_VAL,
1262 }, { 1262 }, {
1263 .reg = IP_SEL_MIX_PAD_REG, 1263 .reg = IP_SEL_MIX_PAD_REG,
1264 .mask = PMX_UART3_PORT_SEL_MASK, 1264 .mask = PMX_UART3_PORT_SEL_MASK,
1265 .val = PMX_UART3_PORT_52_VAL, 1265 .val = PMX_UART3_PORT_52_VAL,
1266 }, 1266 },
1267 }; 1267 };
1268 1268
1269 static struct spear_muxreg uart3_ext_73_74_muxreg[] = { 1269 static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270 { 1270 {
1271 .reg = IP_SEL_PAD_70_79_REG, 1271 .reg = IP_SEL_PAD_70_79_REG,
1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, 1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, 1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274 }, { 1274 }, {
1275 .reg = IP_SEL_MIX_PAD_REG, 1275 .reg = IP_SEL_MIX_PAD_REG,
1276 .mask = PMX_UART3_PORT_SEL_MASK, 1276 .mask = PMX_UART3_PORT_SEL_MASK,
1277 .val = PMX_UART3_PORT_73_VAL, 1277 .val = PMX_UART3_PORT_73_VAL,
1278 }, 1278 },
1279 }; 1279 };
1280 1280
1281 static struct spear_muxreg uart3_ext_94_95_muxreg[] = { 1281 static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282 { 1282 {
1283 .reg = IP_SEL_PAD_90_99_REG, 1283 .reg = IP_SEL_PAD_90_99_REG,
1284 .mask = PMX_PL_94_95_MASK, 1284 .mask = PMX_PL_94_95_MASK,
1285 .val = PMX_UART3_PL_94_95_VAL, 1285 .val = PMX_UART3_PL_94_95_VAL,
1286 }, { 1286 }, {
1287 .reg = IP_SEL_MIX_PAD_REG, 1287 .reg = IP_SEL_MIX_PAD_REG,
1288 .mask = PMX_UART3_PORT_SEL_MASK, 1288 .mask = PMX_UART3_PORT_SEL_MASK,
1289 .val = PMX_UART3_PORT_94_VAL, 1289 .val = PMX_UART3_PORT_94_VAL,
1290 }, 1290 },
1291 }; 1291 };
1292 1292
1293 static struct spear_muxreg uart3_ext_98_99_muxreg[] = { 1293 static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294 { 1294 {
1295 .reg = IP_SEL_PAD_90_99_REG, 1295 .reg = IP_SEL_PAD_90_99_REG,
1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, 1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, 1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298 }, { 1298 }, {
1299 .reg = IP_SEL_MIX_PAD_REG, 1299 .reg = IP_SEL_MIX_PAD_REG,
1300 .mask = PMX_UART3_PORT_SEL_MASK, 1300 .mask = PMX_UART3_PORT_SEL_MASK,
1301 .val = PMX_UART3_PORT_99_VAL, 1301 .val = PMX_UART3_PORT_99_VAL,
1302 }, 1302 },
1303 }; 1303 };
1304 1304
1305 static struct spear_modemux uart3_modemux[][1] = { 1305 static struct spear_modemux uart3_modemux[][1] = {
1306 { 1306 {
1307 /* Select signals on pins 8_9 */ 1307 /* Select signals on pins 8_9 */
1308 { 1308 {
1309 .modes = EXTENDED_MODE, 1309 .modes = EXTENDED_MODE,
1310 .muxregs = uart3_ext_8_9_muxreg, 1310 .muxregs = uart3_ext_8_9_muxreg,
1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg), 1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312 }, 1312 },
1313 }, { 1313 }, {
1314 /* Select signals on pins 15_16 */ 1314 /* Select signals on pins 15_16 */
1315 { 1315 {
1316 .modes = EXTENDED_MODE, 1316 .modes = EXTENDED_MODE,
1317 .muxregs = uart3_ext_15_16_muxreg, 1317 .muxregs = uart3_ext_15_16_muxreg,
1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg), 1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319 }, 1319 },
1320 }, { 1320 }, {
1321 /* Select signals on pins 41_42 */ 1321 /* Select signals on pins 41_42 */
1322 { 1322 {
1323 .modes = EXTENDED_MODE, 1323 .modes = EXTENDED_MODE,
1324 .muxregs = uart3_ext_41_42_muxreg, 1324 .muxregs = uart3_ext_41_42_muxreg,
1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg), 1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326 }, 1326 },
1327 }, { 1327 }, {
1328 /* Select signals on pins 52_53 */ 1328 /* Select signals on pins 52_53 */
1329 { 1329 {
1330 .modes = EXTENDED_MODE, 1330 .modes = EXTENDED_MODE,
1331 .muxregs = uart3_ext_52_53_muxreg, 1331 .muxregs = uart3_ext_52_53_muxreg,
1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg), 1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333 }, 1333 },
1334 }, { 1334 }, {
1335 /* Select signals on pins 73_74 */ 1335 /* Select signals on pins 73_74 */
1336 { 1336 {
1337 .modes = EXTENDED_MODE, 1337 .modes = EXTENDED_MODE,
1338 .muxregs = uart3_ext_73_74_muxreg, 1338 .muxregs = uart3_ext_73_74_muxreg,
1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg), 1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340 }, 1340 },
1341 }, { 1341 }, {
1342 /* Select signals on pins 94_95 */ 1342 /* Select signals on pins 94_95 */
1343 { 1343 {
1344 .modes = EXTENDED_MODE, 1344 .modes = EXTENDED_MODE,
1345 .muxregs = uart3_ext_94_95_muxreg, 1345 .muxregs = uart3_ext_94_95_muxreg,
1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg), 1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347 }, 1347 },
1348 }, { 1348 }, {
1349 /* Select signals on pins 98_99 */ 1349 /* Select signals on pins 98_99 */
1350 { 1350 {
1351 .modes = EXTENDED_MODE, 1351 .modes = EXTENDED_MODE,
1352 .muxregs = uart3_ext_98_99_muxreg, 1352 .muxregs = uart3_ext_98_99_muxreg,
1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg), 1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354 }, 1354 },
1355 }, 1355 },
1356 }; 1356 };
1357 1357
1358 static struct spear_pingroup uart3_pingroup[] = { 1358 static struct spear_pingroup uart3_pingroup[] = {
1359 { 1359 {
1360 .name = "uart3_8_9_grp", 1360 .name = "uart3_8_9_grp",
1361 .pins = uart3_pins[0], 1361 .pins = uart3_pins[0],
1362 .npins = ARRAY_SIZE(uart3_pins[0]), 1362 .npins = ARRAY_SIZE(uart3_pins[0]),
1363 .modemuxs = uart3_modemux[0], 1363 .modemuxs = uart3_modemux[0],
1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]), 1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365 }, { 1365 }, {
1366 .name = "uart3_15_16_grp", 1366 .name = "uart3_15_16_grp",
1367 .pins = uart3_pins[1], 1367 .pins = uart3_pins[1],
1368 .npins = ARRAY_SIZE(uart3_pins[1]), 1368 .npins = ARRAY_SIZE(uart3_pins[1]),
1369 .modemuxs = uart3_modemux[1], 1369 .modemuxs = uart3_modemux[1],
1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]), 1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371 }, { 1371 }, {
1372 .name = "uart3_41_42_grp", 1372 .name = "uart3_41_42_grp",
1373 .pins = uart3_pins[2], 1373 .pins = uart3_pins[2],
1374 .npins = ARRAY_SIZE(uart3_pins[2]), 1374 .npins = ARRAY_SIZE(uart3_pins[2]),
1375 .modemuxs = uart3_modemux[2], 1375 .modemuxs = uart3_modemux[2],
1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]), 1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377 }, { 1377 }, {
1378 .name = "uart3_52_53_grp", 1378 .name = "uart3_52_53_grp",
1379 .pins = uart3_pins[3], 1379 .pins = uart3_pins[3],
1380 .npins = ARRAY_SIZE(uart3_pins[3]), 1380 .npins = ARRAY_SIZE(uart3_pins[3]),
1381 .modemuxs = uart3_modemux[3], 1381 .modemuxs = uart3_modemux[3],
1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]), 1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383 }, { 1383 }, {
1384 .name = "uart3_73_74_grp", 1384 .name = "uart3_73_74_grp",
1385 .pins = uart3_pins[4], 1385 .pins = uart3_pins[4],
1386 .npins = ARRAY_SIZE(uart3_pins[4]), 1386 .npins = ARRAY_SIZE(uart3_pins[4]),
1387 .modemuxs = uart3_modemux[4], 1387 .modemuxs = uart3_modemux[4],
1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]), 1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389 }, { 1389 }, {
1390 .name = "uart3_94_95_grp", 1390 .name = "uart3_94_95_grp",
1391 .pins = uart3_pins[5], 1391 .pins = uart3_pins[5],
1392 .npins = ARRAY_SIZE(uart3_pins[5]), 1392 .npins = ARRAY_SIZE(uart3_pins[5]),
1393 .modemuxs = uart3_modemux[5], 1393 .modemuxs = uart3_modemux[5],
1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]), 1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395 }, { 1395 }, {
1396 .name = "uart3_98_99_grp", 1396 .name = "uart3_98_99_grp",
1397 .pins = uart3_pins[6], 1397 .pins = uart3_pins[6],
1398 .npins = ARRAY_SIZE(uart3_pins[6]), 1398 .npins = ARRAY_SIZE(uart3_pins[6]),
1399 .modemuxs = uart3_modemux[6], 1399 .modemuxs = uart3_modemux[6],
1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]), 1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401 }, 1401 },
1402 }; 1402 };
1403 1403
1404 static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp", 1404 static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp", 1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406 "uart3_94_95_grp", "uart3_98_99_grp" }; 1406 "uart3_94_95_grp", "uart3_98_99_grp" };
1407 1407
1408 static struct spear_function uart3_function = { 1408 static struct spear_function uart3_function = {
1409 .name = "uart3", 1409 .name = "uart3",
1410 .groups = uart3_grps, 1410 .groups = uart3_grps,
1411 .ngroups = ARRAY_SIZE(uart3_grps), 1411 .ngroups = ARRAY_SIZE(uart3_grps),
1412 }; 1412 };
1413 1413
1414 /* Pad multiplexing for uart4 device */ 1414 /* Pad multiplexing for uart4 device */
1415 static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 }, 1415 static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416 { 71, 72 }, { 92, 93 }, { 100, 101 } }; 1416 { 71, 72 }, { 92, 93 }, { 100, 101 } };
1417 1417
1418 static struct spear_muxreg uart4_ext_6_7_muxreg[] = { 1418 static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419 { 1419 {
1420 .reg = PMX_CONFIG_REG, 1420 .reg = PMX_CONFIG_REG,
1421 .mask = PMX_SSP_MASK, 1421 .mask = PMX_SSP_MASK,
1422 .val = 0, 1422 .val = 0,
1423 }, { 1423 }, {
1424 .reg = IP_SEL_PAD_0_9_REG, 1424 .reg = IP_SEL_PAD_0_9_REG,
1425 .mask = PMX_PL_6_7_MASK, 1425 .mask = PMX_PL_6_7_MASK,
1426 .val = PMX_UART4_PL_6_7_VAL, 1426 .val = PMX_UART4_PL_6_7_VAL,
1427 }, { 1427 }, {
1428 .reg = IP_SEL_MIX_PAD_REG, 1428 .reg = IP_SEL_MIX_PAD_REG,
1429 .mask = PMX_UART4_PORT_SEL_MASK, 1429 .mask = PMX_UART4_PORT_SEL_MASK,
1430 .val = PMX_UART4_PORT_6_VAL, 1430 .val = PMX_UART4_PORT_6_VAL,
1431 }, 1431 },
1432 }; 1432 };
1433 1433
1434 static struct spear_muxreg uart4_ext_13_14_muxreg[] = { 1434 static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435 { 1435 {
1436 .reg = PMX_CONFIG_REG, 1436 .reg = PMX_CONFIG_REG,
1437 .mask = PMX_MII_MASK, 1437 .mask = PMX_MII_MASK,
1438 .val = 0, 1438 .val = 0,
1439 }, { 1439 }, {
1440 .reg = IP_SEL_PAD_10_19_REG, 1440 .reg = IP_SEL_PAD_10_19_REG,
1441 .mask = PMX_PL_13_14_MASK, 1441 .mask = PMX_PL_13_14_MASK,
1442 .val = PMX_UART4_PL_13_14_VAL, 1442 .val = PMX_UART4_PL_13_14_VAL,
1443 }, { 1443 }, {
1444 .reg = IP_SEL_MIX_PAD_REG, 1444 .reg = IP_SEL_MIX_PAD_REG,
1445 .mask = PMX_UART4_PORT_SEL_MASK, 1445 .mask = PMX_UART4_PORT_SEL_MASK,
1446 .val = PMX_UART4_PORT_13_VAL, 1446 .val = PMX_UART4_PORT_13_VAL,
1447 }, 1447 },
1448 }; 1448 };
1449 1449
1450 static struct spear_muxreg uart4_ext_39_40_muxreg[] = { 1450 static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451 { 1451 {
1452 .reg = PMX_CONFIG_REG, 1452 .reg = PMX_CONFIG_REG,
1453 .mask = PMX_UART0_MODEM_MASK, 1453 .mask = PMX_UART0_MODEM_MASK,
1454 .val = 0, 1454 .val = 0,
1455 }, { 1455 }, {
1456 .reg = IP_SEL_PAD_30_39_REG, 1456 .reg = IP_SEL_PAD_30_39_REG,
1457 .mask = PMX_PL_39_MASK, 1457 .mask = PMX_PL_39_MASK,
1458 .val = PMX_UART4_PL_39_VAL, 1458 .val = PMX_UART4_PL_39_VAL,
1459 }, { 1459 }, {
1460 .reg = IP_SEL_PAD_40_49_REG, 1460 .reg = IP_SEL_PAD_40_49_REG,
1461 .mask = PMX_PL_40_MASK, 1461 .mask = PMX_PL_40_MASK,
1462 .val = PMX_UART4_PL_40_VAL, 1462 .val = PMX_UART4_PL_40_VAL,
1463 }, { 1463 }, {
1464 .reg = IP_SEL_MIX_PAD_REG, 1464 .reg = IP_SEL_MIX_PAD_REG,
1465 .mask = PMX_UART4_PORT_SEL_MASK, 1465 .mask = PMX_UART4_PORT_SEL_MASK,
1466 .val = PMX_UART4_PORT_39_VAL, 1466 .val = PMX_UART4_PORT_39_VAL,
1467 }, 1467 },
1468 }; 1468 };
1469 1469
1470 static struct spear_muxreg uart4_ext_71_72_muxreg[] = { 1470 static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471 { 1471 {
1472 .reg = IP_SEL_PAD_70_79_REG, 1472 .reg = IP_SEL_PAD_70_79_REG,
1473 .mask = PMX_PL_71_72_MASK, 1473 .mask = PMX_PL_71_72_MASK,
1474 .val = PMX_UART4_PL_71_72_VAL, 1474 .val = PMX_UART4_PL_71_72_VAL,
1475 }, { 1475 }, {
1476 .reg = IP_SEL_MIX_PAD_REG, 1476 .reg = IP_SEL_MIX_PAD_REG,
1477 .mask = PMX_UART4_PORT_SEL_MASK, 1477 .mask = PMX_UART4_PORT_SEL_MASK,
1478 .val = PMX_UART4_PORT_71_VAL, 1478 .val = PMX_UART4_PORT_71_VAL,
1479 }, 1479 },
1480 }; 1480 };
1481 1481
1482 static struct spear_muxreg uart4_ext_92_93_muxreg[] = { 1482 static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483 { 1483 {
1484 .reg = IP_SEL_PAD_90_99_REG, 1484 .reg = IP_SEL_PAD_90_99_REG,
1485 .mask = PMX_PL_92_93_MASK, 1485 .mask = PMX_PL_92_93_MASK,
1486 .val = PMX_UART4_PL_92_93_VAL, 1486 .val = PMX_UART4_PL_92_93_VAL,
1487 }, { 1487 }, {
1488 .reg = IP_SEL_MIX_PAD_REG, 1488 .reg = IP_SEL_MIX_PAD_REG,
1489 .mask = PMX_UART4_PORT_SEL_MASK, 1489 .mask = PMX_UART4_PORT_SEL_MASK,
1490 .val = PMX_UART4_PORT_92_VAL, 1490 .val = PMX_UART4_PORT_92_VAL,
1491 }, 1491 },
1492 }; 1492 };
1493 1493
1494 static struct spear_muxreg uart4_ext_100_101_muxreg[] = { 1494 static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495 { 1495 {
1496 .reg = IP_SEL_MIX_PAD_REG, 1496 .reg = IP_SEL_MIX_PAD_REG,
1497 .mask = PMX_PL_100_101_MASK | 1497 .mask = PMX_PL_100_101_MASK |
1498 PMX_UART4_PORT_SEL_MASK, 1498 PMX_UART4_PORT_SEL_MASK,
1499 .val = PMX_UART4_PL_100_101_VAL | 1499 .val = PMX_UART4_PL_100_101_VAL |
1500 PMX_UART4_PORT_101_VAL, 1500 PMX_UART4_PORT_101_VAL,
1501 }, 1501 },
1502 }; 1502 };
1503 1503
1504 static struct spear_modemux uart4_modemux[][1] = { 1504 static struct spear_modemux uart4_modemux[][1] = {
1505 { 1505 {
1506 /* Select signals on pins 6_7 */ 1506 /* Select signals on pins 6_7 */
1507 { 1507 {
1508 .modes = EXTENDED_MODE, 1508 .modes = EXTENDED_MODE,
1509 .muxregs = uart4_ext_6_7_muxreg, 1509 .muxregs = uart4_ext_6_7_muxreg,
1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg), 1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511 }, 1511 },
1512 }, { 1512 }, {
1513 /* Select signals on pins 13_14 */ 1513 /* Select signals on pins 13_14 */
1514 { 1514 {
1515 .modes = EXTENDED_MODE, 1515 .modes = EXTENDED_MODE,
1516 .muxregs = uart4_ext_13_14_muxreg, 1516 .muxregs = uart4_ext_13_14_muxreg,
1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg), 1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518 }, 1518 },
1519 }, { 1519 }, {
1520 /* Select signals on pins 39_40 */ 1520 /* Select signals on pins 39_40 */
1521 { 1521 {
1522 .modes = EXTENDED_MODE, 1522 .modes = EXTENDED_MODE,
1523 .muxregs = uart4_ext_39_40_muxreg, 1523 .muxregs = uart4_ext_39_40_muxreg,
1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg), 1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525 }, 1525 },
1526 }, { 1526 }, {
1527 /* Select signals on pins 71_72 */ 1527 /* Select signals on pins 71_72 */
1528 { 1528 {
1529 .modes = EXTENDED_MODE, 1529 .modes = EXTENDED_MODE,
1530 .muxregs = uart4_ext_71_72_muxreg, 1530 .muxregs = uart4_ext_71_72_muxreg,
1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg), 1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532 }, 1532 },
1533 }, { 1533 }, {
1534 /* Select signals on pins 92_93 */ 1534 /* Select signals on pins 92_93 */
1535 { 1535 {
1536 .modes = EXTENDED_MODE, 1536 .modes = EXTENDED_MODE,
1537 .muxregs = uart4_ext_92_93_muxreg, 1537 .muxregs = uart4_ext_92_93_muxreg,
1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg), 1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539 }, 1539 },
1540 }, { 1540 }, {
1541 /* Select signals on pins 100_101_ */ 1541 /* Select signals on pins 100_101_ */
1542 { 1542 {
1543 .modes = EXTENDED_MODE, 1543 .modes = EXTENDED_MODE,
1544 .muxregs = uart4_ext_100_101_muxreg, 1544 .muxregs = uart4_ext_100_101_muxreg,
1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg), 1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546 }, 1546 },
1547 }, 1547 },
1548 }; 1548 };
1549 1549
1550 static struct spear_pingroup uart4_pingroup[] = { 1550 static struct spear_pingroup uart4_pingroup[] = {
1551 { 1551 {
1552 .name = "uart4_6_7_grp", 1552 .name = "uart4_6_7_grp",
1553 .pins = uart4_pins[0], 1553 .pins = uart4_pins[0],
1554 .npins = ARRAY_SIZE(uart4_pins[0]), 1554 .npins = ARRAY_SIZE(uart4_pins[0]),
1555 .modemuxs = uart4_modemux[0], 1555 .modemuxs = uart4_modemux[0],
1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]), 1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557 }, { 1557 }, {
1558 .name = "uart4_13_14_grp", 1558 .name = "uart4_13_14_grp",
1559 .pins = uart4_pins[1], 1559 .pins = uart4_pins[1],
1560 .npins = ARRAY_SIZE(uart4_pins[1]), 1560 .npins = ARRAY_SIZE(uart4_pins[1]),
1561 .modemuxs = uart4_modemux[1], 1561 .modemuxs = uart4_modemux[1],
1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]), 1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563 }, { 1563 }, {
1564 .name = "uart4_39_40_grp", 1564 .name = "uart4_39_40_grp",
1565 .pins = uart4_pins[2], 1565 .pins = uart4_pins[2],
1566 .npins = ARRAY_SIZE(uart4_pins[2]), 1566 .npins = ARRAY_SIZE(uart4_pins[2]),
1567 .modemuxs = uart4_modemux[2], 1567 .modemuxs = uart4_modemux[2],
1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]), 1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569 }, { 1569 }, {
1570 .name = "uart4_71_72_grp", 1570 .name = "uart4_71_72_grp",
1571 .pins = uart4_pins[3], 1571 .pins = uart4_pins[3],
1572 .npins = ARRAY_SIZE(uart4_pins[3]), 1572 .npins = ARRAY_SIZE(uart4_pins[3]),
1573 .modemuxs = uart4_modemux[3], 1573 .modemuxs = uart4_modemux[3],
1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]), 1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575 }, { 1575 }, {
1576 .name = "uart4_92_93_grp", 1576 .name = "uart4_92_93_grp",
1577 .pins = uart4_pins[4], 1577 .pins = uart4_pins[4],
1578 .npins = ARRAY_SIZE(uart4_pins[4]), 1578 .npins = ARRAY_SIZE(uart4_pins[4]),
1579 .modemuxs = uart4_modemux[4], 1579 .modemuxs = uart4_modemux[4],
1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]), 1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581 }, { 1581 }, {
1582 .name = "uart4_100_101_grp", 1582 .name = "uart4_100_101_grp",
1583 .pins = uart4_pins[5], 1583 .pins = uart4_pins[5],
1584 .npins = ARRAY_SIZE(uart4_pins[5]), 1584 .npins = ARRAY_SIZE(uart4_pins[5]),
1585 .modemuxs = uart4_modemux[5], 1585 .modemuxs = uart4_modemux[5],
1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]), 1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587 }, 1587 },
1588 }; 1588 };
1589 1589
1590 static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp", 1590 static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", 1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592 "uart4_100_101_grp" }; 1592 "uart4_100_101_grp" };
1593 1593
1594 static struct spear_function uart4_function = { 1594 static struct spear_function uart4_function = {
1595 .name = "uart4", 1595 .name = "uart4",
1596 .groups = uart4_grps, 1596 .groups = uart4_grps,
1597 .ngroups = ARRAY_SIZE(uart4_grps), 1597 .ngroups = ARRAY_SIZE(uart4_grps),
1598 }; 1598 };
1599 1599
1600 /* Pad multiplexing for uart5 device */ 1600 /* Pad multiplexing for uart5 device */
1601 static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 }, 1601 static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602 { 90, 91 } }; 1602 { 90, 91 } };
1603 1603
1604 static struct spear_muxreg uart5_ext_4_5_muxreg[] = { 1604 static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605 { 1605 {
1606 .reg = PMX_CONFIG_REG, 1606 .reg = PMX_CONFIG_REG,
1607 .mask = PMX_I2C_MASK, 1607 .mask = PMX_I2C_MASK,
1608 .val = 0, 1608 .val = 0,
1609 }, { 1609 }, {
1610 .reg = IP_SEL_PAD_0_9_REG, 1610 .reg = IP_SEL_PAD_0_9_REG,
1611 .mask = PMX_PL_4_5_MASK, 1611 .mask = PMX_PL_4_5_MASK,
1612 .val = PMX_UART5_PL_4_5_VAL, 1612 .val = PMX_UART5_PL_4_5_VAL,
1613 }, { 1613 }, {
1614 .reg = IP_SEL_MIX_PAD_REG, 1614 .reg = IP_SEL_MIX_PAD_REG,
1615 .mask = PMX_UART5_PORT_SEL_MASK, 1615 .mask = PMX_UART5_PORT_SEL_MASK,
1616 .val = PMX_UART5_PORT_4_VAL, 1616 .val = PMX_UART5_PORT_4_VAL,
1617 }, 1617 },
1618 }; 1618 };
1619 1619
1620 static struct spear_muxreg uart5_ext_37_38_muxreg[] = { 1620 static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621 { 1621 {
1622 .reg = PMX_CONFIG_REG, 1622 .reg = PMX_CONFIG_REG,
1623 .mask = PMX_UART0_MODEM_MASK, 1623 .mask = PMX_UART0_MODEM_MASK,
1624 .val = 0, 1624 .val = 0,
1625 }, { 1625 }, {
1626 .reg = IP_SEL_PAD_30_39_REG, 1626 .reg = IP_SEL_PAD_30_39_REG,
1627 .mask = PMX_PL_37_38_MASK, 1627 .mask = PMX_PL_37_38_MASK,
1628 .val = PMX_UART5_PL_37_38_VAL, 1628 .val = PMX_UART5_PL_37_38_VAL,
1629 }, { 1629 }, {
1630 .reg = IP_SEL_MIX_PAD_REG, 1630 .reg = IP_SEL_MIX_PAD_REG,
1631 .mask = PMX_UART5_PORT_SEL_MASK, 1631 .mask = PMX_UART5_PORT_SEL_MASK,
1632 .val = PMX_UART5_PORT_37_VAL, 1632 .val = PMX_UART5_PORT_37_VAL,
1633 }, 1633 },
1634 }; 1634 };
1635 1635
1636 static struct spear_muxreg uart5_ext_69_70_muxreg[] = { 1636 static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637 { 1637 {
1638 .reg = IP_SEL_PAD_60_69_REG, 1638 .reg = IP_SEL_PAD_60_69_REG,
1639 .mask = PMX_PL_69_MASK, 1639 .mask = PMX_PL_69_MASK,
1640 .val = PMX_UART5_PL_69_VAL, 1640 .val = PMX_UART5_PL_69_VAL,
1641 }, { 1641 }, {
1642 .reg = IP_SEL_PAD_70_79_REG, 1642 .reg = IP_SEL_PAD_70_79_REG,
1643 .mask = PMX_PL_70_MASK, 1643 .mask = PMX_PL_70_MASK,
1644 .val = PMX_UART5_PL_70_VAL, 1644 .val = PMX_UART5_PL_70_VAL,
1645 }, { 1645 }, {
1646 .reg = IP_SEL_MIX_PAD_REG, 1646 .reg = IP_SEL_MIX_PAD_REG,
1647 .mask = PMX_UART5_PORT_SEL_MASK, 1647 .mask = PMX_UART5_PORT_SEL_MASK,
1648 .val = PMX_UART5_PORT_69_VAL, 1648 .val = PMX_UART5_PORT_69_VAL,
1649 }, 1649 },
1650 }; 1650 };
1651 1651
1652 static struct spear_muxreg uart5_ext_90_91_muxreg[] = { 1652 static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653 { 1653 {
1654 .reg = IP_SEL_PAD_90_99_REG, 1654 .reg = IP_SEL_PAD_90_99_REG,
1655 .mask = PMX_PL_90_91_MASK, 1655 .mask = PMX_PL_90_91_MASK,
1656 .val = PMX_UART5_PL_90_91_VAL, 1656 .val = PMX_UART5_PL_90_91_VAL,
1657 }, { 1657 }, {
1658 .reg = IP_SEL_MIX_PAD_REG, 1658 .reg = IP_SEL_MIX_PAD_REG,
1659 .mask = PMX_UART5_PORT_SEL_MASK, 1659 .mask = PMX_UART5_PORT_SEL_MASK,
1660 .val = PMX_UART5_PORT_90_VAL, 1660 .val = PMX_UART5_PORT_90_VAL,
1661 }, 1661 },
1662 }; 1662 };
1663 1663
1664 static struct spear_modemux uart5_modemux[][1] = { 1664 static struct spear_modemux uart5_modemux[][1] = {
1665 { 1665 {
1666 /* Select signals on pins 4_5 */ 1666 /* Select signals on pins 4_5 */
1667 { 1667 {
1668 .modes = EXTENDED_MODE, 1668 .modes = EXTENDED_MODE,
1669 .muxregs = uart5_ext_4_5_muxreg, 1669 .muxregs = uart5_ext_4_5_muxreg,
1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg), 1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671 }, 1671 },
1672 }, { 1672 }, {
1673 /* Select signals on pins 37_38 */ 1673 /* Select signals on pins 37_38 */
1674 { 1674 {
1675 .modes = EXTENDED_MODE, 1675 .modes = EXTENDED_MODE,
1676 .muxregs = uart5_ext_37_38_muxreg, 1676 .muxregs = uart5_ext_37_38_muxreg,
1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg), 1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678 }, 1678 },
1679 }, { 1679 }, {
1680 /* Select signals on pins 69_70 */ 1680 /* Select signals on pins 69_70 */
1681 { 1681 {
1682 .modes = EXTENDED_MODE, 1682 .modes = EXTENDED_MODE,
1683 .muxregs = uart5_ext_69_70_muxreg, 1683 .muxregs = uart5_ext_69_70_muxreg,
1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg), 1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685 }, 1685 },
1686 }, { 1686 }, {
1687 /* Select signals on pins 90_91 */ 1687 /* Select signals on pins 90_91 */
1688 { 1688 {
1689 .modes = EXTENDED_MODE, 1689 .modes = EXTENDED_MODE,
1690 .muxregs = uart5_ext_90_91_muxreg, 1690 .muxregs = uart5_ext_90_91_muxreg,
1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg), 1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692 }, 1692 },
1693 }, 1693 },
1694 }; 1694 };
1695 1695
1696 static struct spear_pingroup uart5_pingroup[] = { 1696 static struct spear_pingroup uart5_pingroup[] = {
1697 { 1697 {
1698 .name = "uart5_4_5_grp", 1698 .name = "uart5_4_5_grp",
1699 .pins = uart5_pins[0], 1699 .pins = uart5_pins[0],
1700 .npins = ARRAY_SIZE(uart5_pins[0]), 1700 .npins = ARRAY_SIZE(uart5_pins[0]),
1701 .modemuxs = uart5_modemux[0], 1701 .modemuxs = uart5_modemux[0],
1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]), 1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703 }, { 1703 }, {
1704 .name = "uart5_37_38_grp", 1704 .name = "uart5_37_38_grp",
1705 .pins = uart5_pins[1], 1705 .pins = uart5_pins[1],
1706 .npins = ARRAY_SIZE(uart5_pins[1]), 1706 .npins = ARRAY_SIZE(uart5_pins[1]),
1707 .modemuxs = uart5_modemux[1], 1707 .modemuxs = uart5_modemux[1],
1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]), 1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709 }, { 1709 }, {
1710 .name = "uart5_69_70_grp", 1710 .name = "uart5_69_70_grp",
1711 .pins = uart5_pins[2], 1711 .pins = uart5_pins[2],
1712 .npins = ARRAY_SIZE(uart5_pins[2]), 1712 .npins = ARRAY_SIZE(uart5_pins[2]),
1713 .modemuxs = uart5_modemux[2], 1713 .modemuxs = uart5_modemux[2],
1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]), 1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715 }, { 1715 }, {
1716 .name = "uart5_90_91_grp", 1716 .name = "uart5_90_91_grp",
1717 .pins = uart5_pins[3], 1717 .pins = uart5_pins[3],
1718 .npins = ARRAY_SIZE(uart5_pins[3]), 1718 .npins = ARRAY_SIZE(uart5_pins[3]),
1719 .modemuxs = uart5_modemux[3], 1719 .modemuxs = uart5_modemux[3],
1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]), 1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721 }, 1721 },
1722 }; 1722 };
1723 1723
1724 static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp", 1724 static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725 "uart5_69_70_grp", "uart5_90_91_grp" }; 1725 "uart5_69_70_grp", "uart5_90_91_grp" };
1726 static struct spear_function uart5_function = { 1726 static struct spear_function uart5_function = {
1727 .name = "uart5", 1727 .name = "uart5",
1728 .groups = uart5_grps, 1728 .groups = uart5_grps,
1729 .ngroups = ARRAY_SIZE(uart5_grps), 1729 .ngroups = ARRAY_SIZE(uart5_grps),
1730 }; 1730 };
1731 1731
1732 /* Pad multiplexing for uart6 device */ 1732 /* Pad multiplexing for uart6 device */
1733 static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } }; 1733 static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734 static struct spear_muxreg uart6_ext_2_3_muxreg[] = { 1734 static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735 { 1735 {
1736 .reg = PMX_CONFIG_REG, 1736 .reg = PMX_CONFIG_REG,
1737 .mask = PMX_UART0_MASK, 1737 .mask = PMX_UART0_MASK,
1738 .val = 0, 1738 .val = 0,
1739 }, { 1739 }, {
1740 .reg = IP_SEL_PAD_0_9_REG, 1740 .reg = IP_SEL_PAD_0_9_REG,
1741 .mask = PMX_PL_2_3_MASK, 1741 .mask = PMX_PL_2_3_MASK,
1742 .val = PMX_UART6_PL_2_3_VAL, 1742 .val = PMX_UART6_PL_2_3_VAL,
1743 }, { 1743 }, {
1744 .reg = IP_SEL_MIX_PAD_REG, 1744 .reg = IP_SEL_MIX_PAD_REG,
1745 .mask = PMX_UART6_PORT_SEL_MASK, 1745 .mask = PMX_UART6_PORT_SEL_MASK,
1746 .val = PMX_UART6_PORT_2_VAL, 1746 .val = PMX_UART6_PORT_2_VAL,
1747 }, 1747 },
1748 }; 1748 };
1749 1749
1750 static struct spear_muxreg uart6_ext_88_89_muxreg[] = { 1750 static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751 { 1751 {
1752 .reg = IP_SEL_PAD_80_89_REG, 1752 .reg = IP_SEL_PAD_80_89_REG,
1753 .mask = PMX_PL_88_89_MASK, 1753 .mask = PMX_PL_88_89_MASK,
1754 .val = PMX_UART6_PL_88_89_VAL, 1754 .val = PMX_UART6_PL_88_89_VAL,
1755 }, { 1755 }, {
1756 .reg = IP_SEL_MIX_PAD_REG, 1756 .reg = IP_SEL_MIX_PAD_REG,
1757 .mask = PMX_UART6_PORT_SEL_MASK, 1757 .mask = PMX_UART6_PORT_SEL_MASK,
1758 .val = PMX_UART6_PORT_88_VAL, 1758 .val = PMX_UART6_PORT_88_VAL,
1759 }, 1759 },
1760 }; 1760 };
1761 1761
1762 static struct spear_modemux uart6_modemux[][1] = { 1762 static struct spear_modemux uart6_modemux[][1] = {
1763 { 1763 {
1764 /* Select signals on pins 2_3 */ 1764 /* Select signals on pins 2_3 */
1765 { 1765 {
1766 .modes = EXTENDED_MODE, 1766 .modes = EXTENDED_MODE,
1767 .muxregs = uart6_ext_2_3_muxreg, 1767 .muxregs = uart6_ext_2_3_muxreg,
1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg), 1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769 }, 1769 },
1770 }, { 1770 }, {
1771 /* Select signals on pins 88_89 */ 1771 /* Select signals on pins 88_89 */
1772 { 1772 {
1773 .modes = EXTENDED_MODE, 1773 .modes = EXTENDED_MODE,
1774 .muxregs = uart6_ext_88_89_muxreg, 1774 .muxregs = uart6_ext_88_89_muxreg,
1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg), 1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776 }, 1776 },
1777 }, 1777 },
1778 }; 1778 };
1779 1779
1780 static struct spear_pingroup uart6_pingroup[] = { 1780 static struct spear_pingroup uart6_pingroup[] = {
1781 { 1781 {
1782 .name = "uart6_2_3_grp", 1782 .name = "uart6_2_3_grp",
1783 .pins = uart6_pins[0], 1783 .pins = uart6_pins[0],
1784 .npins = ARRAY_SIZE(uart6_pins[0]), 1784 .npins = ARRAY_SIZE(uart6_pins[0]),
1785 .modemuxs = uart6_modemux[0], 1785 .modemuxs = uart6_modemux[0],
1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]), 1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787 }, { 1787 }, {
1788 .name = "uart6_88_89_grp", 1788 .name = "uart6_88_89_grp",
1789 .pins = uart6_pins[1], 1789 .pins = uart6_pins[1],
1790 .npins = ARRAY_SIZE(uart6_pins[1]), 1790 .npins = ARRAY_SIZE(uart6_pins[1]),
1791 .modemuxs = uart6_modemux[1], 1791 .modemuxs = uart6_modemux[1],
1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]), 1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793 }, 1793 },
1794 }; 1794 };
1795 1795
1796 static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" }; 1796 static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797 static struct spear_function uart6_function = { 1797 static struct spear_function uart6_function = {
1798 .name = "uart6", 1798 .name = "uart6",
1799 .groups = uart6_grps, 1799 .groups = uart6_grps,
1800 .ngroups = ARRAY_SIZE(uart6_grps), 1800 .ngroups = ARRAY_SIZE(uart6_grps),
1801 }; 1801 };
1802 1802
1803 /* UART - RS485 pmx */ 1803 /* UART - RS485 pmx */
1804 static const unsigned rs485_pins[] = { 77, 78, 79 }; 1804 static const unsigned rs485_pins[] = { 77, 78, 79 };
1805 static struct spear_muxreg rs485_muxreg[] = { 1805 static struct spear_muxreg rs485_muxreg[] = {
1806 { 1806 {
1807 .reg = IP_SEL_PAD_70_79_REG, 1807 .reg = IP_SEL_PAD_70_79_REG,
1808 .mask = PMX_PL_77_78_79_MASK, 1808 .mask = PMX_PL_77_78_79_MASK,
1809 .val = PMX_RS485_PL_77_78_79_VAL, 1809 .val = PMX_RS485_PL_77_78_79_VAL,
1810 }, 1810 },
1811 }; 1811 };
1812 1812
1813 static struct spear_modemux rs485_modemux[] = { 1813 static struct spear_modemux rs485_modemux[] = {
1814 { 1814 {
1815 .modes = EXTENDED_MODE, 1815 .modes = EXTENDED_MODE,
1816 .muxregs = rs485_muxreg, 1816 .muxregs = rs485_muxreg,
1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg), 1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818 }, 1818 },
1819 }; 1819 };
1820 1820
1821 static struct spear_pingroup rs485_pingroup = { 1821 static struct spear_pingroup rs485_pingroup = {
1822 .name = "rs485_grp", 1822 .name = "rs485_grp",
1823 .pins = rs485_pins, 1823 .pins = rs485_pins,
1824 .npins = ARRAY_SIZE(rs485_pins), 1824 .npins = ARRAY_SIZE(rs485_pins),
1825 .modemuxs = rs485_modemux, 1825 .modemuxs = rs485_modemux,
1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux), 1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827 }; 1827 };
1828 1828
1829 static const char *const rs485_grps[] = { "rs485_grp" }; 1829 static const char *const rs485_grps[] = { "rs485_grp" };
1830 static struct spear_function rs485_function = { 1830 static struct spear_function rs485_function = {
1831 .name = "rs485", 1831 .name = "rs485",
1832 .groups = rs485_grps, 1832 .groups = rs485_grps,
1833 .ngroups = ARRAY_SIZE(rs485_grps), 1833 .ngroups = ARRAY_SIZE(rs485_grps),
1834 }; 1834 };
1835 1835
1836 /* Pad multiplexing for Touchscreen device */ 1836 /* Pad multiplexing for Touchscreen device */
1837 static const unsigned touchscreen_pins[] = { 5, 36 }; 1837 static const unsigned touchscreen_pins[] = { 5, 36 };
1838 static struct spear_muxreg touchscreen_muxreg[] = { 1838 static struct spear_muxreg touchscreen_muxreg[] = {
1839 { 1839 {
1840 .reg = PMX_CONFIG_REG, 1840 .reg = PMX_CONFIG_REG,
1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, 1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842 .val = 0, 1842 .val = 0,
1843 }, 1843 },
1844 }; 1844 };
1845 1845
1846 static struct spear_muxreg touchscreen_ext_muxreg[] = { 1846 static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847 { 1847 {
1848 .reg = IP_SEL_PAD_0_9_REG, 1848 .reg = IP_SEL_PAD_0_9_REG,
1849 .mask = PMX_PL_5_MASK, 1849 .mask = PMX_PL_5_MASK,
1850 .val = PMX_TOUCH_Y_PL_5_VAL, 1850 .val = PMX_TOUCH_Y_PL_5_VAL,
1851 }, { 1851 }, {
1852 .reg = IP_SEL_PAD_30_39_REG, 1852 .reg = IP_SEL_PAD_30_39_REG,
1853 .mask = PMX_PL_36_MASK, 1853 .mask = PMX_PL_36_MASK,
1854 .val = PMX_TOUCH_X_PL_36_VAL, 1854 .val = PMX_TOUCH_X_PL_36_VAL,
1855 }, 1855 },
1856 }; 1856 };
1857 1857
1858 static struct spear_modemux touchscreen_modemux[] = { 1858 static struct spear_modemux touchscreen_modemux[] = {
1859 { 1859 {
1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, 1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861 .muxregs = touchscreen_muxreg, 1861 .muxregs = touchscreen_muxreg,
1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg), 1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863 }, { 1863 }, {
1864 .modes = EXTENDED_MODE, 1864 .modes = EXTENDED_MODE,
1865 .muxregs = touchscreen_ext_muxreg, 1865 .muxregs = touchscreen_ext_muxreg,
1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg), 1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867 }, 1867 },
1868 }; 1868 };
1869 1869
1870 static struct spear_pingroup touchscreen_pingroup = { 1870 static struct spear_pingroup touchscreen_pingroup = {
1871 .name = "touchscreen_grp", 1871 .name = "touchscreen_grp",
1872 .pins = touchscreen_pins, 1872 .pins = touchscreen_pins,
1873 .npins = ARRAY_SIZE(touchscreen_pins), 1873 .npins = ARRAY_SIZE(touchscreen_pins),
1874 .modemuxs = touchscreen_modemux, 1874 .modemuxs = touchscreen_modemux,
1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux), 1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876 }; 1876 };
1877 1877
1878 static const char *const touchscreen_grps[] = { "touchscreen_grp" }; 1878 static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879 static struct spear_function touchscreen_function = { 1879 static struct spear_function touchscreen_function = {
1880 .name = "touchscreen", 1880 .name = "touchscreen",
1881 .groups = touchscreen_grps, 1881 .groups = touchscreen_grps,
1882 .ngroups = ARRAY_SIZE(touchscreen_grps), 1882 .ngroups = ARRAY_SIZE(touchscreen_grps),
1883 }; 1883 };
1884 1884
1885 /* Pad multiplexing for CAN device */ 1885 /* Pad multiplexing for CAN device */
1886 static const unsigned can0_pins[] = { 32, 33 }; 1886 static const unsigned can0_pins[] = { 32, 33 };
1887 static struct spear_muxreg can0_muxreg[] = { 1887 static struct spear_muxreg can0_muxreg[] = {
1888 { 1888 {
1889 .reg = PMX_CONFIG_REG, 1889 .reg = PMX_CONFIG_REG,
1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, 1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891 .val = 0, 1891 .val = 0,
1892 }, 1892 },
1893 }; 1893 };
1894 1894
1895 static struct spear_muxreg can0_ext_muxreg[] = { 1895 static struct spear_muxreg can0_ext_muxreg[] = {
1896 { 1896 {
1897 .reg = IP_SEL_PAD_30_39_REG, 1897 .reg = IP_SEL_PAD_30_39_REG,
1898 .mask = PMX_PL_32_33_MASK, 1898 .mask = PMX_PL_32_33_MASK,
1899 .val = PMX_CAN0_PL_32_33_VAL, 1899 .val = PMX_CAN0_PL_32_33_VAL,
1900 }, 1900 },
1901 }; 1901 };
1902 1902
1903 static struct spear_modemux can0_modemux[] = { 1903 static struct spear_modemux can0_modemux[] = {
1904 { 1904 {
1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906 | EXTENDED_MODE, 1906 | EXTENDED_MODE,
1907 .muxregs = can0_muxreg, 1907 .muxregs = can0_muxreg,
1908 .nmuxregs = ARRAY_SIZE(can0_muxreg), 1908 .nmuxregs = ARRAY_SIZE(can0_muxreg),
1909 }, { 1909 }, {
1910 .modes = EXTENDED_MODE, 1910 .modes = EXTENDED_MODE,
1911 .muxregs = can0_ext_muxreg, 1911 .muxregs = can0_ext_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg), 1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913 }, 1913 },
1914 }; 1914 };
1915 1915
1916 static struct spear_pingroup can0_pingroup = { 1916 static struct spear_pingroup can0_pingroup = {
1917 .name = "can0_grp", 1917 .name = "can0_grp",
1918 .pins = can0_pins, 1918 .pins = can0_pins,
1919 .npins = ARRAY_SIZE(can0_pins), 1919 .npins = ARRAY_SIZE(can0_pins),
1920 .modemuxs = can0_modemux, 1920 .modemuxs = can0_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_modemux), 1921 .nmodemuxs = ARRAY_SIZE(can0_modemux),
1922 }; 1922 };
1923 1923
1924 static const char *const can0_grps[] = { "can0_grp" }; 1924 static const char *const can0_grps[] = { "can0_grp" };
1925 static struct spear_function can0_function = { 1925 static struct spear_function can0_function = {
1926 .name = "can0", 1926 .name = "can0",
1927 .groups = can0_grps, 1927 .groups = can0_grps,
1928 .ngroups = ARRAY_SIZE(can0_grps), 1928 .ngroups = ARRAY_SIZE(can0_grps),
1929 }; 1929 };
1930 1930
1931 static const unsigned can1_pins[] = { 30, 31 }; 1931 static const unsigned can1_pins[] = { 30, 31 };
1932 static struct spear_muxreg can1_muxreg[] = { 1932 static struct spear_muxreg can1_muxreg[] = {
1933 { 1933 {
1934 .reg = PMX_CONFIG_REG, 1934 .reg = PMX_CONFIG_REG,
1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, 1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936 .val = 0, 1936 .val = 0,
1937 }, 1937 },
1938 }; 1938 };
1939 1939
1940 static struct spear_muxreg can1_ext_muxreg[] = { 1940 static struct spear_muxreg can1_ext_muxreg[] = {
1941 { 1941 {
1942 .reg = IP_SEL_PAD_30_39_REG, 1942 .reg = IP_SEL_PAD_30_39_REG,
1943 .mask = PMX_PL_30_31_MASK, 1943 .mask = PMX_PL_30_31_MASK,
1944 .val = PMX_CAN1_PL_30_31_VAL, 1944 .val = PMX_CAN1_PL_30_31_VAL,
1945 }, 1945 },
1946 }; 1946 };
1947 1947
1948 static struct spear_modemux can1_modemux[] = { 1948 static struct spear_modemux can1_modemux[] = {
1949 { 1949 {
1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE 1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951 | EXTENDED_MODE, 1951 | EXTENDED_MODE,
1952 .muxregs = can1_muxreg, 1952 .muxregs = can1_muxreg,
1953 .nmuxregs = ARRAY_SIZE(can1_muxreg), 1953 .nmuxregs = ARRAY_SIZE(can1_muxreg),
1954 }, { 1954 }, {
1955 .modes = EXTENDED_MODE, 1955 .modes = EXTENDED_MODE,
1956 .muxregs = can1_ext_muxreg, 1956 .muxregs = can1_ext_muxreg,
1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg), 1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958 }, 1958 },
1959 }; 1959 };
1960 1960
1961 static struct spear_pingroup can1_pingroup = { 1961 static struct spear_pingroup can1_pingroup = {
1962 .name = "can1_grp", 1962 .name = "can1_grp",
1963 .pins = can1_pins, 1963 .pins = can1_pins,
1964 .npins = ARRAY_SIZE(can1_pins), 1964 .npins = ARRAY_SIZE(can1_pins),
1965 .modemuxs = can1_modemux, 1965 .modemuxs = can1_modemux,
1966 .nmodemuxs = ARRAY_SIZE(can1_modemux), 1966 .nmodemuxs = ARRAY_SIZE(can1_modemux),
1967 }; 1967 };
1968 1968
1969 static const char *const can1_grps[] = { "can1_grp" }; 1969 static const char *const can1_grps[] = { "can1_grp" };
1970 static struct spear_function can1_function = { 1970 static struct spear_function can1_function = {
1971 .name = "can1", 1971 .name = "can1",
1972 .groups = can1_grps, 1972 .groups = can1_grps,
1973 .ngroups = ARRAY_SIZE(can1_grps), 1973 .ngroups = ARRAY_SIZE(can1_grps),
1974 }; 1974 };
1975 1975
1976 /* Pad multiplexing for PWM0_1 device */ 1976 /* Pad multiplexing for PWM0_1 device */
1977 static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 }, 1977 static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } }; 1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979 1979
1980 static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = { 1980 static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981 { 1981 {
1982 .reg = PMX_CONFIG_REG, 1982 .reg = PMX_CONFIG_REG,
1983 .mask = PMX_SSP_MASK, 1983 .mask = PMX_SSP_MASK,
1984 .val = 0, 1984 .val = 0,
1985 }, { 1985 }, {
1986 .reg = IP_SEL_PAD_0_9_REG, 1986 .reg = IP_SEL_PAD_0_9_REG,
1987 .mask = PMX_PL_8_9_MASK, 1987 .mask = PMX_PL_8_9_MASK,
1988 .val = PMX_PWM_0_1_PL_8_9_VAL, 1988 .val = PMX_PWM_0_1_PL_8_9_VAL,
1989 }, 1989 },
1990 }; 1990 };
1991 1991
1992 static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = { 1992 static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993 { 1993 {
1994 .reg = PMX_CONFIG_REG, 1994 .reg = PMX_CONFIG_REG,
1995 .mask = PMX_MII_MASK, 1995 .mask = PMX_MII_MASK,
1996 .val = 0, 1996 .val = 0,
1997 }, 1997 },
1998 }; 1998 };
1999 1999
2000 static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = { 2000 static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001 { 2001 {
2002 .reg = IP_SEL_PAD_10_19_REG, 2002 .reg = IP_SEL_PAD_10_19_REG,
2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, 2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, 2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005 }, 2005 },
2006 }; 2006 };
2007 2007
2008 static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = { 2008 static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009 { 2009 {
2010 .reg = PMX_CONFIG_REG, 2010 .reg = PMX_CONFIG_REG,
2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, 2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012 .val = 0, 2012 .val = 0,
2013 }, { 2013 }, {
2014 .reg = IP_SEL_PAD_30_39_REG, 2014 .reg = IP_SEL_PAD_30_39_REG,
2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, 2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, 2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017 }, 2017 },
2018 }; 2018 };
2019 2019
2020 static struct spear_muxreg pwm0_1_net_muxreg[] = { 2020 static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021 { 2021 {
2022 .reg = PMX_CONFIG_REG, 2022 .reg = PMX_CONFIG_REG,
2023 .mask = PMX_UART0_MODEM_MASK, 2023 .mask = PMX_UART0_MODEM_MASK,
2024 .val = 0, 2024 .val = 0,
2025 }, 2025 },
2026 }; 2026 };
2027 2027
2028 static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = { 2028 static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029 { 2029 {
2030 .reg = IP_SEL_PAD_30_39_REG, 2030 .reg = IP_SEL_PAD_30_39_REG,
2031 .mask = PMX_PL_37_38_MASK, 2031 .mask = PMX_PL_37_38_MASK,
2032 .val = PMX_PWM0_1_PL_37_38_VAL, 2032 .val = PMX_PWM0_1_PL_37_38_VAL,
2033 }, 2033 },
2034 }; 2034 };
2035 2035
2036 static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = { 2036 static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037 { 2037 {
2038 .reg = PMX_CONFIG_REG, 2038 .reg = PMX_CONFIG_REG,
2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , 2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040 .val = 0, 2040 .val = 0,
2041 }, { 2041 }, {
2042 .reg = IP_SEL_PAD_40_49_REG, 2042 .reg = IP_SEL_PAD_40_49_REG,
2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, 2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044 .val = PMX_PWM1_PL_42_VAL | 2044 .val = PMX_PWM1_PL_42_VAL |
2045 PMX_PWM0_PL_43_VAL, 2045 PMX_PWM0_PL_43_VAL,
2046 }, 2046 },
2047 }; 2047 };
2048 2048
2049 static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = { 2049 static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050 { 2050 {
2051 .reg = IP_SEL_PAD_50_59_REG, 2051 .reg = IP_SEL_PAD_50_59_REG,
2052 .mask = PMX_PL_59_MASK, 2052 .mask = PMX_PL_59_MASK,
2053 .val = PMX_PWM1_PL_59_VAL, 2053 .val = PMX_PWM1_PL_59_VAL,
2054 }, { 2054 }, {
2055 .reg = IP_SEL_PAD_60_69_REG, 2055 .reg = IP_SEL_PAD_60_69_REG,
2056 .mask = PMX_PL_60_MASK, 2056 .mask = PMX_PL_60_MASK,
2057 .val = PMX_PWM0_PL_60_VAL, 2057 .val = PMX_PWM0_PL_60_VAL,
2058 }, 2058 },
2059 }; 2059 };
2060 2060
2061 static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = { 2061 static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062 { 2062 {
2063 .reg = IP_SEL_PAD_80_89_REG, 2063 .reg = IP_SEL_PAD_80_89_REG,
2064 .mask = PMX_PL_88_89_MASK, 2064 .mask = PMX_PL_88_89_MASK,
2065 .val = PMX_PWM0_1_PL_88_89_VAL, 2065 .val = PMX_PWM0_1_PL_88_89_VAL,
2066 }, 2066 },
2067 }; 2067 };
2068 2068
2069 static struct spear_modemux pwm0_1_pin_8_9_modemux[] = { 2069 static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070 { 2070 {
2071 .modes = EXTENDED_MODE, 2071 .modes = EXTENDED_MODE,
2072 .muxregs = pwm0_1_pin_8_9_muxreg, 2072 .muxregs = pwm0_1_pin_8_9_muxreg,
2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg), 2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074 }, 2074 },
2075 }; 2075 };
2076 2076
2077 static struct spear_modemux pwm0_1_pin_14_15_modemux[] = { 2077 static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078 { 2078 {
2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, 2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg, 2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg), 2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082 }, { 2082 }, {
2083 .modes = EXTENDED_MODE, 2083 .modes = EXTENDED_MODE,
2084 .muxregs = pwm0_1_pin_14_15_muxreg, 2084 .muxregs = pwm0_1_pin_14_15_muxreg,
2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg), 2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086 }, 2086 },
2087 }; 2087 };
2088 2088
2089 static struct spear_modemux pwm0_1_pin_30_31_modemux[] = { 2089 static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090 { 2090 {
2091 .modes = EXTENDED_MODE, 2091 .modes = EXTENDED_MODE,
2092 .muxregs = pwm0_1_pin_30_31_muxreg, 2092 .muxregs = pwm0_1_pin_30_31_muxreg,
2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg), 2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094 }, 2094 },
2095 }; 2095 };
2096 2096
2097 static struct spear_modemux pwm0_1_pin_37_38_modemux[] = { 2097 static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098 { 2098 {
2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100 .muxregs = pwm0_1_net_muxreg, 2100 .muxregs = pwm0_1_net_muxreg,
2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg), 2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102 }, { 2102 }, {
2103 .modes = EXTENDED_MODE, 2103 .modes = EXTENDED_MODE,
2104 .muxregs = pwm0_1_pin_37_38_muxreg, 2104 .muxregs = pwm0_1_pin_37_38_muxreg,
2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg), 2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106 }, 2106 },
2107 }; 2107 };
2108 2108
2109 static struct spear_modemux pwm0_1_pin_42_43_modemux[] = { 2109 static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110 { 2110 {
2111 .modes = EXTENDED_MODE, 2111 .modes = EXTENDED_MODE,
2112 .muxregs = pwm0_1_pin_42_43_muxreg, 2112 .muxregs = pwm0_1_pin_42_43_muxreg,
2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg), 2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114 }, 2114 },
2115 }; 2115 };
2116 2116
2117 static struct spear_modemux pwm0_1_pin_59_60_modemux[] = { 2117 static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118 { 2118 {
2119 .modes = EXTENDED_MODE, 2119 .modes = EXTENDED_MODE,
2120 .muxregs = pwm0_1_pin_59_60_muxreg, 2120 .muxregs = pwm0_1_pin_59_60_muxreg,
2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg), 2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122 }, 2122 },
2123 }; 2123 };
2124 2124
2125 static struct spear_modemux pwm0_1_pin_88_89_modemux[] = { 2125 static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126 { 2126 {
2127 .modes = EXTENDED_MODE, 2127 .modes = EXTENDED_MODE,
2128 .muxregs = pwm0_1_pin_88_89_muxreg, 2128 .muxregs = pwm0_1_pin_88_89_muxreg,
2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg), 2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130 }, 2130 },
2131 }; 2131 };
2132 2132
2133 static struct spear_pingroup pwm0_1_pingroup[] = { 2133 static struct spear_pingroup pwm0_1_pingroup[] = {
2134 { 2134 {
2135 .name = "pwm0_1_pin_8_9_grp", 2135 .name = "pwm0_1_pin_8_9_grp",
2136 .pins = pwm0_1_pins[0], 2136 .pins = pwm0_1_pins[0],
2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]), 2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138 .modemuxs = pwm0_1_pin_8_9_modemux, 2138 .modemuxs = pwm0_1_pin_8_9_modemux,
2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux), 2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140 }, { 2140 }, {
2141 .name = "pwm0_1_pin_14_15_grp", 2141 .name = "pwm0_1_pin_14_15_grp",
2142 .pins = pwm0_1_pins[1], 2142 .pins = pwm0_1_pins[1],
2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]), 2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144 .modemuxs = pwm0_1_pin_14_15_modemux, 2144 .modemuxs = pwm0_1_pin_14_15_modemux,
2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux), 2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146 }, { 2146 }, {
2147 .name = "pwm0_1_pin_30_31_grp", 2147 .name = "pwm0_1_pin_30_31_grp",
2148 .pins = pwm0_1_pins[2], 2148 .pins = pwm0_1_pins[2],
2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]), 2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150 .modemuxs = pwm0_1_pin_30_31_modemux, 2150 .modemuxs = pwm0_1_pin_30_31_modemux,
2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux), 2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152 }, { 2152 }, {
2153 .name = "pwm0_1_pin_37_38_grp", 2153 .name = "pwm0_1_pin_37_38_grp",
2154 .pins = pwm0_1_pins[3], 2154 .pins = pwm0_1_pins[3],
2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]), 2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156 .modemuxs = pwm0_1_pin_37_38_modemux, 2156 .modemuxs = pwm0_1_pin_37_38_modemux,
2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux), 2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158 }, { 2158 }, {
2159 .name = "pwm0_1_pin_42_43_grp", 2159 .name = "pwm0_1_pin_42_43_grp",
2160 .pins = pwm0_1_pins[4], 2160 .pins = pwm0_1_pins[4],
2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]), 2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162 .modemuxs = pwm0_1_pin_42_43_modemux, 2162 .modemuxs = pwm0_1_pin_42_43_modemux,
2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux), 2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164 }, { 2164 }, {
2165 .name = "pwm0_1_pin_59_60_grp", 2165 .name = "pwm0_1_pin_59_60_grp",
2166 .pins = pwm0_1_pins[5], 2166 .pins = pwm0_1_pins[5],
2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]), 2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168 .modemuxs = pwm0_1_pin_59_60_modemux, 2168 .modemuxs = pwm0_1_pin_59_60_modemux,
2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux), 2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170 }, { 2170 }, {
2171 .name = "pwm0_1_pin_88_89_grp", 2171 .name = "pwm0_1_pin_88_89_grp",
2172 .pins = pwm0_1_pins[6], 2172 .pins = pwm0_1_pins[6],
2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]), 2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174 .modemuxs = pwm0_1_pin_88_89_modemux, 2174 .modemuxs = pwm0_1_pin_88_89_modemux,
2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux), 2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176 }, 2176 },
2177 }; 2177 };
2178 2178
2179 static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp", 2179 static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", 2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp" 2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182 }; 2182 };
2183 2183
2184 static struct spear_function pwm0_1_function = { 2184 static struct spear_function pwm0_1_function = {
2185 .name = "pwm0_1", 2185 .name = "pwm0_1",
2186 .groups = pwm0_1_grps, 2186 .groups = pwm0_1_grps,
2187 .ngroups = ARRAY_SIZE(pwm0_1_grps), 2187 .ngroups = ARRAY_SIZE(pwm0_1_grps),
2188 }; 2188 };
2189 2189
2190 /* Pad multiplexing for PWM2 device */ 2190 /* Pad multiplexing for PWM2 device */
2191 static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 }, 2191 static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192 { 58 }, { 87 } }; 2192 { 58 }, { 87 } };
2193 static struct spear_muxreg pwm2_net_muxreg[] = { 2193 static struct spear_muxreg pwm2_net_muxreg[] = {
2194 { 2194 {
2195 .reg = PMX_CONFIG_REG, 2195 .reg = PMX_CONFIG_REG,
2196 .mask = PMX_SSP_CS_MASK, 2196 .mask = PMX_SSP_CS_MASK,
2197 .val = 0, 2197 .val = 0,
2198 }, 2198 },
2199 }; 2199 };
2200 2200
2201 static struct spear_muxreg pwm2_pin_7_muxreg[] = { 2201 static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202 { 2202 {
2203 .reg = IP_SEL_PAD_0_9_REG, 2203 .reg = IP_SEL_PAD_0_9_REG,
2204 .mask = PMX_PL_7_MASK, 2204 .mask = PMX_PL_7_MASK,
2205 .val = PMX_PWM_2_PL_7_VAL, 2205 .val = PMX_PWM_2_PL_7_VAL,
2206 }, 2206 },
2207 }; 2207 };
2208 2208
2209 static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = { 2209 static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210 { 2210 {
2211 .reg = PMX_CONFIG_REG, 2211 .reg = PMX_CONFIG_REG,
2212 .mask = PMX_MII_MASK, 2212 .mask = PMX_MII_MASK,
2213 .val = 0, 2213 .val = 0,
2214 }, 2214 },
2215 }; 2215 };
2216 2216
2217 static struct spear_muxreg pwm2_pin_13_muxreg[] = { 2217 static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218 { 2218 {
2219 .reg = IP_SEL_PAD_10_19_REG, 2219 .reg = IP_SEL_PAD_10_19_REG,
2220 .mask = PMX_PL_13_MASK, 2220 .mask = PMX_PL_13_MASK,
2221 .val = PMX_PWM2_PL_13_VAL, 2221 .val = PMX_PWM2_PL_13_VAL,
2222 }, 2222 },
2223 }; 2223 };
2224 2224
2225 static struct spear_muxreg pwm2_pin_29_muxreg[] = { 2225 static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226 { 2226 {
2227 .reg = PMX_CONFIG_REG, 2227 .reg = PMX_CONFIG_REG,
2228 .mask = PMX_GPIO_PIN1_MASK, 2228 .mask = PMX_GPIO_PIN1_MASK,
2229 .val = 0, 2229 .val = 0,
2230 }, { 2230 }, {
2231 .reg = IP_SEL_PAD_20_29_REG, 2231 .reg = IP_SEL_PAD_20_29_REG,
2232 .mask = PMX_PL_29_MASK, 2232 .mask = PMX_PL_29_MASK,
2233 .val = PMX_PWM_2_PL_29_VAL, 2233 .val = PMX_PWM_2_PL_29_VAL,
2234 }, 2234 },
2235 }; 2235 };
2236 2236
2237 static struct spear_muxreg pwm2_pin_34_muxreg[] = { 2237 static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238 { 2238 {
2239 .reg = PMX_CONFIG_REG, 2239 .reg = PMX_CONFIG_REG,
2240 .mask = PMX_SSP_CS_MASK, 2240 .mask = PMX_SSP_CS_MASK,
2241 .val = 0, 2241 .val = 0,
2242 }, { 2242 }, {
2243 .reg = MODE_CONFIG_REG, 2243 .reg = MODE_CONFIG_REG,
2244 .mask = PMX_PWM_MASK, 2244 .mask = PMX_PWM_MASK,
2245 .val = PMX_PWM_MASK, 2245 .val = PMX_PWM_MASK,
2246 }, { 2246 }, {
2247 .reg = IP_SEL_PAD_30_39_REG, 2247 .reg = IP_SEL_PAD_30_39_REG,
2248 .mask = PMX_PL_34_MASK, 2248 .mask = PMX_PL_34_MASK,
2249 .val = PMX_PWM2_PL_34_VAL, 2249 .val = PMX_PWM2_PL_34_VAL,
2250 }, 2250 },
2251 }; 2251 };
2252 2252
2253 static struct spear_muxreg pwm2_pin_41_muxreg[] = { 2253 static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2254 { 2254 {
2255 .reg = PMX_CONFIG_REG, 2255 .reg = PMX_CONFIG_REG,
2256 .mask = PMX_UART0_MODEM_MASK, 2256 .mask = PMX_UART0_MODEM_MASK,
2257 .val = 0, 2257 .val = 0,
2258 }, { 2258 }, {
2259 .reg = IP_SEL_PAD_40_49_REG, 2259 .reg = IP_SEL_PAD_40_49_REG,
2260 .mask = PMX_PL_41_MASK, 2260 .mask = PMX_PL_41_MASK,
2261 .val = PMX_PWM2_PL_41_VAL, 2261 .val = PMX_PWM2_PL_41_VAL,
2262 }, 2262 },
2263 }; 2263 };
2264 2264
2265 static struct spear_muxreg pwm2_pin_58_muxreg[] = { 2265 static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2266 { 2266 {
2267 .reg = IP_SEL_PAD_50_59_REG, 2267 .reg = IP_SEL_PAD_50_59_REG,
2268 .mask = PMX_PL_58_MASK, 2268 .mask = PMX_PL_58_MASK,
2269 .val = PMX_PWM2_PL_58_VAL, 2269 .val = PMX_PWM2_PL_58_VAL,
2270 }, 2270 },
2271 }; 2271 };
2272 2272
2273 static struct spear_muxreg pwm2_pin_87_muxreg[] = { 2273 static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2274 { 2274 {
2275 .reg = IP_SEL_PAD_80_89_REG, 2275 .reg = IP_SEL_PAD_80_89_REG,
2276 .mask = PMX_PL_87_MASK, 2276 .mask = PMX_PL_87_MASK,
2277 .val = PMX_PWM2_PL_87_VAL, 2277 .val = PMX_PWM2_PL_87_VAL,
2278 }, 2278 },
2279 }; 2279 };
2280 2280
2281 static struct spear_modemux pwm2_pin_7_modemux[] = { 2281 static struct spear_modemux pwm2_pin_7_modemux[] = {
2282 { 2282 {
2283 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, 2283 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2284 .muxregs = pwm2_net_muxreg, 2284 .muxregs = pwm2_net_muxreg,
2285 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg), 2285 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2286 }, { 2286 }, {
2287 .modes = EXTENDED_MODE, 2287 .modes = EXTENDED_MODE,
2288 .muxregs = pwm2_pin_7_muxreg, 2288 .muxregs = pwm2_pin_7_muxreg,
2289 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg), 2289 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2290 }, 2290 },
2291 }; 2291 };
2292 static struct spear_modemux pwm2_pin_13_modemux[] = { 2292 static struct spear_modemux pwm2_pin_13_modemux[] = {
2293 { 2293 {
2294 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, 2294 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2295 .muxregs = pwm2_autoexpsmallpri_muxreg, 2295 .muxregs = pwm2_autoexpsmallpri_muxreg,
2296 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg), 2296 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2297 }, { 2297 }, {
2298 .modes = EXTENDED_MODE, 2298 .modes = EXTENDED_MODE,
2299 .muxregs = pwm2_pin_13_muxreg, 2299 .muxregs = pwm2_pin_13_muxreg,
2300 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg), 2300 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2301 }, 2301 },
2302 }; 2302 };
2303 static struct spear_modemux pwm2_pin_29_modemux[] = { 2303 static struct spear_modemux pwm2_pin_29_modemux[] = {
2304 { 2304 {
2305 .modes = EXTENDED_MODE, 2305 .modes = EXTENDED_MODE,
2306 .muxregs = pwm2_pin_29_muxreg, 2306 .muxregs = pwm2_pin_29_muxreg,
2307 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg), 2307 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2308 }, 2308 },
2309 }; 2309 };
2310 static struct spear_modemux pwm2_pin_34_modemux[] = { 2310 static struct spear_modemux pwm2_pin_34_modemux[] = {
2311 { 2311 {
2312 .modes = EXTENDED_MODE, 2312 .modes = EXTENDED_MODE,
2313 .muxregs = pwm2_pin_34_muxreg, 2313 .muxregs = pwm2_pin_34_muxreg,
2314 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg), 2314 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2315 }, 2315 },
2316 }; 2316 };
2317 2317
2318 static struct spear_modemux pwm2_pin_41_modemux[] = { 2318 static struct spear_modemux pwm2_pin_41_modemux[] = {
2319 { 2319 {
2320 .modes = EXTENDED_MODE, 2320 .modes = EXTENDED_MODE,
2321 .muxregs = pwm2_pin_41_muxreg, 2321 .muxregs = pwm2_pin_41_muxreg,
2322 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg), 2322 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2323 }, 2323 },
2324 }; 2324 };
2325 2325
2326 static struct spear_modemux pwm2_pin_58_modemux[] = { 2326 static struct spear_modemux pwm2_pin_58_modemux[] = {
2327 { 2327 {
2328 .modes = EXTENDED_MODE, 2328 .modes = EXTENDED_MODE,
2329 .muxregs = pwm2_pin_58_muxreg, 2329 .muxregs = pwm2_pin_58_muxreg,
2330 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg), 2330 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2331 }, 2331 },
2332 }; 2332 };
2333 2333
2334 static struct spear_modemux pwm2_pin_87_modemux[] = { 2334 static struct spear_modemux pwm2_pin_87_modemux[] = {
2335 { 2335 {
2336 .modes = EXTENDED_MODE, 2336 .modes = EXTENDED_MODE,
2337 .muxregs = pwm2_pin_87_muxreg, 2337 .muxregs = pwm2_pin_87_muxreg,
2338 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg), 2338 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2339 }, 2339 },
2340 }; 2340 };
2341 2341
2342 static struct spear_pingroup pwm2_pingroup[] = { 2342 static struct spear_pingroup pwm2_pingroup[] = {
2343 { 2343 {
2344 .name = "pwm2_pin_7_grp", 2344 .name = "pwm2_pin_7_grp",
2345 .pins = pwm2_pins[0], 2345 .pins = pwm2_pins[0],
2346 .npins = ARRAY_SIZE(pwm2_pins[0]), 2346 .npins = ARRAY_SIZE(pwm2_pins[0]),
2347 .modemuxs = pwm2_pin_7_modemux, 2347 .modemuxs = pwm2_pin_7_modemux,
2348 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux), 2348 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2349 }, { 2349 }, {
2350 .name = "pwm2_pin_13_grp", 2350 .name = "pwm2_pin_13_grp",
2351 .pins = pwm2_pins[1], 2351 .pins = pwm2_pins[1],
2352 .npins = ARRAY_SIZE(pwm2_pins[1]), 2352 .npins = ARRAY_SIZE(pwm2_pins[1]),
2353 .modemuxs = pwm2_pin_13_modemux, 2353 .modemuxs = pwm2_pin_13_modemux,
2354 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux), 2354 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2355 }, { 2355 }, {
2356 .name = "pwm2_pin_29_grp", 2356 .name = "pwm2_pin_29_grp",
2357 .pins = pwm2_pins[2], 2357 .pins = pwm2_pins[2],
2358 .npins = ARRAY_SIZE(pwm2_pins[2]), 2358 .npins = ARRAY_SIZE(pwm2_pins[2]),
2359 .modemuxs = pwm2_pin_29_modemux, 2359 .modemuxs = pwm2_pin_29_modemux,
2360 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux), 2360 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2361 }, { 2361 }, {
2362 .name = "pwm2_pin_34_grp", 2362 .name = "pwm2_pin_34_grp",
2363 .pins = pwm2_pins[3], 2363 .pins = pwm2_pins[3],
2364 .npins = ARRAY_SIZE(pwm2_pins[3]), 2364 .npins = ARRAY_SIZE(pwm2_pins[3]),
2365 .modemuxs = pwm2_pin_34_modemux, 2365 .modemuxs = pwm2_pin_34_modemux,
2366 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux), 2366 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2367 }, { 2367 }, {
2368 .name = "pwm2_pin_41_grp", 2368 .name = "pwm2_pin_41_grp",
2369 .pins = pwm2_pins[4], 2369 .pins = pwm2_pins[4],
2370 .npins = ARRAY_SIZE(pwm2_pins[4]), 2370 .npins = ARRAY_SIZE(pwm2_pins[4]),
2371 .modemuxs = pwm2_pin_41_modemux, 2371 .modemuxs = pwm2_pin_41_modemux,
2372 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux), 2372 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2373 }, { 2373 }, {
2374 .name = "pwm2_pin_58_grp", 2374 .name = "pwm2_pin_58_grp",
2375 .pins = pwm2_pins[5], 2375 .pins = pwm2_pins[5],
2376 .npins = ARRAY_SIZE(pwm2_pins[5]), 2376 .npins = ARRAY_SIZE(pwm2_pins[5]),
2377 .modemuxs = pwm2_pin_58_modemux, 2377 .modemuxs = pwm2_pin_58_modemux,
2378 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux), 2378 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2379 }, { 2379 }, {
2380 .name = "pwm2_pin_87_grp", 2380 .name = "pwm2_pin_87_grp",
2381 .pins = pwm2_pins[6], 2381 .pins = pwm2_pins[6],
2382 .npins = ARRAY_SIZE(pwm2_pins[6]), 2382 .npins = ARRAY_SIZE(pwm2_pins[6]),
2383 .modemuxs = pwm2_pin_87_modemux, 2383 .modemuxs = pwm2_pin_87_modemux,
2384 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux), 2384 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2385 }, 2385 },
2386 }; 2386 };
2387 2387
2388 static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp", 2388 static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2389 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp", 2389 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2390 "pwm2_pin_58_grp", "pwm2_pin_87_grp" }; 2390 "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2391 static struct spear_function pwm2_function = { 2391 static struct spear_function pwm2_function = {
2392 .name = "pwm2", 2392 .name = "pwm2",
2393 .groups = pwm2_grps, 2393 .groups = pwm2_grps,
2394 .ngroups = ARRAY_SIZE(pwm2_grps), 2394 .ngroups = ARRAY_SIZE(pwm2_grps),
2395 }; 2395 };
2396 2396
2397 /* Pad multiplexing for PWM3 device */ 2397 /* Pad multiplexing for PWM3 device */
2398 static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 }, 2398 static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2399 { 86 } }; 2399 { 86 } };
2400 static struct spear_muxreg pwm3_pin_6_muxreg[] = { 2400 static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2401 { 2401 {
2402 .reg = PMX_CONFIG_REG, 2402 .reg = PMX_CONFIG_REG,
2403 .mask = PMX_SSP_MASK, 2403 .mask = PMX_SSP_MASK,
2404 .val = 0, 2404 .val = 0,
2405 }, { 2405 }, {
2406 .reg = IP_SEL_PAD_0_9_REG, 2406 .reg = IP_SEL_PAD_0_9_REG,
2407 .mask = PMX_PL_6_MASK, 2407 .mask = PMX_PL_6_MASK,
2408 .val = PMX_PWM_3_PL_6_VAL, 2408 .val = PMX_PWM_3_PL_6_VAL,
2409 }, 2409 },
2410 }; 2410 };
2411 2411
2412 static struct spear_muxreg pwm3_muxreg[] = { 2412 static struct spear_muxreg pwm3_muxreg[] = {
2413 { 2413 {
2414 .reg = PMX_CONFIG_REG, 2414 .reg = PMX_CONFIG_REG,
2415 .mask = PMX_MII_MASK, 2415 .mask = PMX_MII_MASK,
2416 .val = 0, 2416 .val = 0,
2417 }, 2417 },
2418 }; 2418 };
2419 2419
2420 static struct spear_muxreg pwm3_pin_12_muxreg[] = { 2420 static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2421 { 2421 {
2422 .reg = IP_SEL_PAD_10_19_REG, 2422 .reg = IP_SEL_PAD_10_19_REG,
2423 .mask = PMX_PL_12_MASK, 2423 .mask = PMX_PL_12_MASK,
2424 .val = PMX_PWM3_PL_12_VAL, 2424 .val = PMX_PWM3_PL_12_VAL,
2425 }, 2425 },
2426 }; 2426 };
2427 2427
2428 static struct spear_muxreg pwm3_pin_28_muxreg[] = { 2428 static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2429 { 2429 {
2430 .reg = PMX_CONFIG_REG, 2430 .reg = PMX_CONFIG_REG,
2431 .mask = PMX_GPIO_PIN0_MASK, 2431 .mask = PMX_GPIO_PIN0_MASK,
2432 .val = 0, 2432 .val = 0,
2433 }, { 2433 }, {
2434 .reg = IP_SEL_PAD_20_29_REG, 2434 .reg = IP_SEL_PAD_20_29_REG,
2435 .mask = PMX_PL_28_MASK, 2435 .mask = PMX_PL_28_MASK,
2436 .val = PMX_PWM_3_PL_28_VAL, 2436 .val = PMX_PWM_3_PL_28_VAL,
2437 }, 2437 },
2438 }; 2438 };
2439 2439
2440 static struct spear_muxreg pwm3_pin_40_muxreg[] = { 2440 static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2441 { 2441 {
2442 .reg = PMX_CONFIG_REG, 2442 .reg = PMX_CONFIG_REG,
2443 .mask = PMX_UART0_MODEM_MASK, 2443 .mask = PMX_UART0_MODEM_MASK,
2444 .val = 0, 2444 .val = 0,
2445 }, { 2445 }, {
2446 .reg = IP_SEL_PAD_40_49_REG, 2446 .reg = IP_SEL_PAD_40_49_REG,
2447 .mask = PMX_PL_40_MASK, 2447 .mask = PMX_PL_40_MASK,
2448 .val = PMX_PWM3_PL_40_VAL, 2448 .val = PMX_PWM3_PL_40_VAL,
2449 }, 2449 },
2450 }; 2450 };
2451 2451
2452 static struct spear_muxreg pwm3_pin_57_muxreg[] = { 2452 static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2453 { 2453 {
2454 .reg = IP_SEL_PAD_50_59_REG, 2454 .reg = IP_SEL_PAD_50_59_REG,
2455 .mask = PMX_PL_57_MASK, 2455 .mask = PMX_PL_57_MASK,
2456 .val = PMX_PWM3_PL_57_VAL, 2456 .val = PMX_PWM3_PL_57_VAL,
2457 }, 2457 },
2458 }; 2458 };
2459 2459
2460 static struct spear_muxreg pwm3_pin_86_muxreg[] = { 2460 static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2461 { 2461 {
2462 .reg = IP_SEL_PAD_80_89_REG, 2462 .reg = IP_SEL_PAD_80_89_REG,
2463 .mask = PMX_PL_86_MASK, 2463 .mask = PMX_PL_86_MASK,
2464 .val = PMX_PWM3_PL_86_VAL, 2464 .val = PMX_PWM3_PL_86_VAL,
2465 }, 2465 },
2466 }; 2466 };
2467 2467
2468 static struct spear_modemux pwm3_pin_6_modemux[] = { 2468 static struct spear_modemux pwm3_pin_6_modemux[] = {
2469 { 2469 {
2470 .modes = EXTENDED_MODE, 2470 .modes = EXTENDED_MODE,
2471 .muxregs = pwm3_pin_6_muxreg, 2471 .muxregs = pwm3_pin_6_muxreg,
2472 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg), 2472 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2473 }, 2473 },
2474 }; 2474 };
2475 2475
2476 static struct spear_modemux pwm3_pin_12_modemux[] = { 2476 static struct spear_modemux pwm3_pin_12_modemux[] = {
2477 { 2477 {
2478 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | 2478 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2479 AUTO_NET_SMII_MODE | EXTENDED_MODE, 2479 AUTO_NET_SMII_MODE | EXTENDED_MODE,
2480 .muxregs = pwm3_muxreg, 2480 .muxregs = pwm3_muxreg,
2481 .nmuxregs = ARRAY_SIZE(pwm3_muxreg), 2481 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2482 }, { 2482 }, {
2483 .modes = EXTENDED_MODE, 2483 .modes = EXTENDED_MODE,
2484 .muxregs = pwm3_pin_12_muxreg, 2484 .muxregs = pwm3_pin_12_muxreg,
2485 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg), 2485 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2486 }, 2486 },
2487 }; 2487 };
2488 2488
2489 static struct spear_modemux pwm3_pin_28_modemux[] = { 2489 static struct spear_modemux pwm3_pin_28_modemux[] = {
2490 { 2490 {
2491 .modes = EXTENDED_MODE, 2491 .modes = EXTENDED_MODE,
2492 .muxregs = pwm3_pin_28_muxreg, 2492 .muxregs = pwm3_pin_28_muxreg,
2493 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg), 2493 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2494 }, 2494 },
2495 }; 2495 };
2496 2496
2497 static struct spear_modemux pwm3_pin_40_modemux[] = { 2497 static struct spear_modemux pwm3_pin_40_modemux[] = {
2498 { 2498 {
2499 .modes = EXTENDED_MODE, 2499 .modes = EXTENDED_MODE,
2500 .muxregs = pwm3_pin_40_muxreg, 2500 .muxregs = pwm3_pin_40_muxreg,
2501 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg), 2501 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2502 }, 2502 },
2503 }; 2503 };
2504 2504
2505 static struct spear_modemux pwm3_pin_57_modemux[] = { 2505 static struct spear_modemux pwm3_pin_57_modemux[] = {
2506 { 2506 {
2507 .modes = EXTENDED_MODE, 2507 .modes = EXTENDED_MODE,
2508 .muxregs = pwm3_pin_57_muxreg, 2508 .muxregs = pwm3_pin_57_muxreg,
2509 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg), 2509 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2510 }, 2510 },
2511 }; 2511 };
2512 2512
2513 static struct spear_modemux pwm3_pin_86_modemux[] = { 2513 static struct spear_modemux pwm3_pin_86_modemux[] = {
2514 { 2514 {
2515 .modes = EXTENDED_MODE, 2515 .modes = EXTENDED_MODE,
2516 .muxregs = pwm3_pin_86_muxreg, 2516 .muxregs = pwm3_pin_86_muxreg,
2517 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg), 2517 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2518 }, 2518 },
2519 }; 2519 };
2520 2520
2521 static struct spear_pingroup pwm3_pingroup[] = { 2521 static struct spear_pingroup pwm3_pingroup[] = {
2522 { 2522 {
2523 .name = "pwm3_pin_6_grp", 2523 .name = "pwm3_pin_6_grp",
2524 .pins = pwm3_pins[0], 2524 .pins = pwm3_pins[0],
2525 .npins = ARRAY_SIZE(pwm3_pins[0]), 2525 .npins = ARRAY_SIZE(pwm3_pins[0]),
2526 .modemuxs = pwm3_pin_6_modemux, 2526 .modemuxs = pwm3_pin_6_modemux,
2527 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux), 2527 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2528 }, { 2528 }, {
2529 .name = "pwm3_pin_12_grp", 2529 .name = "pwm3_pin_12_grp",
2530 .pins = pwm3_pins[1], 2530 .pins = pwm3_pins[1],
2531 .npins = ARRAY_SIZE(pwm3_pins[1]), 2531 .npins = ARRAY_SIZE(pwm3_pins[1]),
2532 .modemuxs = pwm3_pin_12_modemux, 2532 .modemuxs = pwm3_pin_12_modemux,
2533 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux), 2533 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2534 }, { 2534 }, {
2535 .name = "pwm3_pin_28_grp", 2535 .name = "pwm3_pin_28_grp",
2536 .pins = pwm3_pins[2], 2536 .pins = pwm3_pins[2],
2537 .npins = ARRAY_SIZE(pwm3_pins[2]), 2537 .npins = ARRAY_SIZE(pwm3_pins[2]),
2538 .modemuxs = pwm3_pin_28_modemux, 2538 .modemuxs = pwm3_pin_28_modemux,
2539 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux), 2539 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2540 }, { 2540 }, {
2541 .name = "pwm3_pin_40_grp", 2541 .name = "pwm3_pin_40_grp",
2542 .pins = pwm3_pins[3], 2542 .pins = pwm3_pins[3],
2543 .npins = ARRAY_SIZE(pwm3_pins[3]), 2543 .npins = ARRAY_SIZE(pwm3_pins[3]),
2544 .modemuxs = pwm3_pin_40_modemux, 2544 .modemuxs = pwm3_pin_40_modemux,
2545 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux), 2545 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2546 }, { 2546 }, {
2547 .name = "pwm3_pin_57_grp", 2547 .name = "pwm3_pin_57_grp",
2548 .pins = pwm3_pins[4], 2548 .pins = pwm3_pins[4],
2549 .npins = ARRAY_SIZE(pwm3_pins[4]), 2549 .npins = ARRAY_SIZE(pwm3_pins[4]),
2550 .modemuxs = pwm3_pin_57_modemux, 2550 .modemuxs = pwm3_pin_57_modemux,
2551 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux), 2551 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2552 }, { 2552 }, {
2553 .name = "pwm3_pin_86_grp", 2553 .name = "pwm3_pin_86_grp",
2554 .pins = pwm3_pins[5], 2554 .pins = pwm3_pins[5],
2555 .npins = ARRAY_SIZE(pwm3_pins[5]), 2555 .npins = ARRAY_SIZE(pwm3_pins[5]),
2556 .modemuxs = pwm3_pin_86_modemux, 2556 .modemuxs = pwm3_pin_86_modemux,
2557 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux), 2557 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2558 }, 2558 },
2559 }; 2559 };
2560 2560
2561 static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp", 2561 static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2562 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp", 2562 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2563 "pwm3_pin_86_grp" }; 2563 "pwm3_pin_86_grp" };
2564 static struct spear_function pwm3_function = { 2564 static struct spear_function pwm3_function = {
2565 .name = "pwm3", 2565 .name = "pwm3",
2566 .groups = pwm3_grps, 2566 .groups = pwm3_grps,
2567 .ngroups = ARRAY_SIZE(pwm3_grps), 2567 .ngroups = ARRAY_SIZE(pwm3_grps),
2568 }; 2568 };
2569 2569
2570 /* Pad multiplexing for SSP1 device */ 2570 /* Pad multiplexing for SSP1 device */
2571 static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 }, 2571 static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2572 { 65, 68 }, { 94, 97 } }; 2572 { 65, 68 }, { 94, 97 } };
2573 static struct spear_muxreg ssp1_muxreg[] = { 2573 static struct spear_muxreg ssp1_muxreg[] = {
2574 { 2574 {
2575 .reg = PMX_CONFIG_REG, 2575 .reg = PMX_CONFIG_REG,
2576 .mask = PMX_MII_MASK, 2576 .mask = PMX_MII_MASK,
2577 .val = 0, 2577 .val = 0,
2578 }, 2578 },
2579 }; 2579 };
2580 2580
2581 static struct spear_muxreg ssp1_ext_17_20_muxreg[] = { 2581 static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2582 { 2582 {
2583 .reg = IP_SEL_PAD_10_19_REG, 2583 .reg = IP_SEL_PAD_10_19_REG,
2584 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, 2584 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2585 .val = PMX_SSP1_PL_17_18_19_20_VAL, 2585 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2586 }, { 2586 }, {
2587 .reg = IP_SEL_PAD_20_29_REG, 2587 .reg = IP_SEL_PAD_20_29_REG,
2588 .mask = PMX_PL_20_MASK, 2588 .mask = PMX_PL_20_MASK,
2589 .val = PMX_SSP1_PL_17_18_19_20_VAL, 2589 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2590 }, { 2590 }, {
2591 .reg = IP_SEL_MIX_PAD_REG, 2591 .reg = IP_SEL_MIX_PAD_REG,
2592 .mask = PMX_SSP1_PORT_SEL_MASK, 2592 .mask = PMX_SSP1_PORT_SEL_MASK,
2593 .val = PMX_SSP1_PORT_17_TO_20_VAL, 2593 .val = PMX_SSP1_PORT_17_TO_20_VAL,
2594 }, 2594 },
2595 }; 2595 };
2596 2596
2597 static struct spear_muxreg ssp1_ext_36_39_muxreg[] = { 2597 static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2598 { 2598 {
2599 .reg = PMX_CONFIG_REG, 2599 .reg = PMX_CONFIG_REG,
2600 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, 2600 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2601 .val = 0, 2601 .val = 0,
2602 }, { 2602 }, {
2603 .reg = IP_SEL_PAD_30_39_REG, 2603 .reg = IP_SEL_PAD_30_39_REG,
2604 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, 2604 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2605 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | 2605 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2606 PMX_SSP1_PL_39_VAL, 2606 PMX_SSP1_PL_39_VAL,
2607 }, { 2607 }, {
2608 .reg = IP_SEL_MIX_PAD_REG, 2608 .reg = IP_SEL_MIX_PAD_REG,
2609 .mask = PMX_SSP1_PORT_SEL_MASK, 2609 .mask = PMX_SSP1_PORT_SEL_MASK,
2610 .val = PMX_SSP1_PORT_36_TO_39_VAL, 2610 .val = PMX_SSP1_PORT_36_TO_39_VAL,
2611 }, 2611 },
2612 }; 2612 };
2613 2613
2614 static struct spear_muxreg ssp1_ext_48_51_muxreg[] = { 2614 static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2615 { 2615 {
2616 .reg = PMX_CONFIG_REG, 2616 .reg = PMX_CONFIG_REG,
2617 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 2617 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2618 .val = 0, 2618 .val = 0,
2619 }, { 2619 }, {
2620 .reg = IP_SEL_PAD_40_49_REG, 2620 .reg = IP_SEL_PAD_40_49_REG,
2621 .mask = PMX_PL_48_49_MASK, 2621 .mask = PMX_PL_48_49_MASK,
2622 .val = PMX_SSP1_PL_48_49_VAL, 2622 .val = PMX_SSP1_PL_48_49_VAL,
2623 }, { 2623 }, {
2624 .reg = IP_SEL_PAD_50_59_REG, 2624 .reg = IP_SEL_PAD_50_59_REG,
2625 .mask = PMX_PL_50_51_MASK, 2625 .mask = PMX_PL_50_51_MASK,
2626 .val = PMX_SSP1_PL_50_51_VAL, 2626 .val = PMX_SSP1_PL_50_51_VAL,
2627 }, { 2627 }, {
2628 .reg = IP_SEL_MIX_PAD_REG, 2628 .reg = IP_SEL_MIX_PAD_REG,
2629 .mask = PMX_SSP1_PORT_SEL_MASK, 2629 .mask = PMX_SSP1_PORT_SEL_MASK,
2630 .val = PMX_SSP1_PORT_48_TO_51_VAL, 2630 .val = PMX_SSP1_PORT_48_TO_51_VAL,
2631 }, 2631 },
2632 }; 2632 };
2633 2633
2634 static struct spear_muxreg ssp1_ext_65_68_muxreg[] = { 2634 static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2635 { 2635 {
2636 .reg = IP_SEL_PAD_60_69_REG, 2636 .reg = IP_SEL_PAD_60_69_REG,
2637 .mask = PMX_PL_65_TO_68_MASK, 2637 .mask = PMX_PL_65_TO_68_MASK,
2638 .val = PMX_SSP1_PL_65_TO_68_VAL, 2638 .val = PMX_SSP1_PL_65_TO_68_VAL,
2639 }, { 2639 }, {
2640 .reg = IP_SEL_MIX_PAD_REG, 2640 .reg = IP_SEL_MIX_PAD_REG,
2641 .mask = PMX_SSP1_PORT_SEL_MASK, 2641 .mask = PMX_SSP1_PORT_SEL_MASK,
2642 .val = PMX_SSP1_PORT_65_TO_68_VAL, 2642 .val = PMX_SSP1_PORT_65_TO_68_VAL,
2643 }, 2643 },
2644 }; 2644 };
2645 2645
2646 static struct spear_muxreg ssp1_ext_94_97_muxreg[] = { 2646 static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2647 { 2647 {
2648 .reg = IP_SEL_PAD_90_99_REG, 2648 .reg = IP_SEL_PAD_90_99_REG,
2649 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, 2649 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2650 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, 2650 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2651 }, { 2651 }, {
2652 .reg = IP_SEL_MIX_PAD_REG, 2652 .reg = IP_SEL_MIX_PAD_REG,
2653 .mask = PMX_SSP1_PORT_SEL_MASK, 2653 .mask = PMX_SSP1_PORT_SEL_MASK,
2654 .val = PMX_SSP1_PORT_94_TO_97_VAL, 2654 .val = PMX_SSP1_PORT_94_TO_97_VAL,
2655 }, 2655 },
2656 }; 2656 };
2657 2657
2658 static struct spear_modemux ssp1_17_20_modemux[] = { 2658 static struct spear_modemux ssp1_17_20_modemux[] = {
2659 { 2659 {
2660 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE | 2660 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2661 EXTENDED_MODE, 2661 EXTENDED_MODE,
2662 .muxregs = ssp1_muxreg, 2662 .muxregs = ssp1_muxreg,
2663 .nmuxregs = ARRAY_SIZE(ssp1_muxreg), 2663 .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2664 }, { 2664 }, {
2665 .modes = EXTENDED_MODE, 2665 .modes = EXTENDED_MODE,
2666 .muxregs = ssp1_ext_17_20_muxreg, 2666 .muxregs = ssp1_ext_17_20_muxreg,
2667 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg), 2667 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2668 }, 2668 },
2669 }; 2669 };
2670 2670
2671 static struct spear_modemux ssp1_36_39_modemux[] = { 2671 static struct spear_modemux ssp1_36_39_modemux[] = {
2672 { 2672 {
2673 .modes = EXTENDED_MODE, 2673 .modes = EXTENDED_MODE,
2674 .muxregs = ssp1_ext_36_39_muxreg, 2674 .muxregs = ssp1_ext_36_39_muxreg,
2675 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg), 2675 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2676 }, 2676 },
2677 }; 2677 };
2678 2678
2679 static struct spear_modemux ssp1_48_51_modemux[] = { 2679 static struct spear_modemux ssp1_48_51_modemux[] = {
2680 { 2680 {
2681 .modes = EXTENDED_MODE, 2681 .modes = EXTENDED_MODE,
2682 .muxregs = ssp1_ext_48_51_muxreg, 2682 .muxregs = ssp1_ext_48_51_muxreg,
2683 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg), 2683 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2684 }, 2684 },
2685 }; 2685 };
2686 static struct spear_modemux ssp1_65_68_modemux[] = { 2686 static struct spear_modemux ssp1_65_68_modemux[] = {
2687 { 2687 {
2688 .modes = EXTENDED_MODE, 2688 .modes = EXTENDED_MODE,
2689 .muxregs = ssp1_ext_65_68_muxreg, 2689 .muxregs = ssp1_ext_65_68_muxreg,
2690 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg), 2690 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2691 }, 2691 },
2692 }; 2692 };
2693 2693
2694 static struct spear_modemux ssp1_94_97_modemux[] = { 2694 static struct spear_modemux ssp1_94_97_modemux[] = {
2695 { 2695 {
2696 .modes = EXTENDED_MODE, 2696 .modes = EXTENDED_MODE,
2697 .muxregs = ssp1_ext_94_97_muxreg, 2697 .muxregs = ssp1_ext_94_97_muxreg,
2698 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg), 2698 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2699 }, 2699 },
2700 }; 2700 };
2701 2701
2702 static struct spear_pingroup ssp1_pingroup[] = { 2702 static struct spear_pingroup ssp1_pingroup[] = {
2703 { 2703 {
2704 .name = "ssp1_17_20_grp", 2704 .name = "ssp1_17_20_grp",
2705 .pins = ssp1_pins[0], 2705 .pins = ssp1_pins[0],
2706 .npins = ARRAY_SIZE(ssp1_pins[0]), 2706 .npins = ARRAY_SIZE(ssp1_pins[0]),
2707 .modemuxs = ssp1_17_20_modemux, 2707 .modemuxs = ssp1_17_20_modemux,
2708 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux), 2708 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2709 }, { 2709 }, {
2710 .name = "ssp1_36_39_grp", 2710 .name = "ssp1_36_39_grp",
2711 .pins = ssp1_pins[1], 2711 .pins = ssp1_pins[1],
2712 .npins = ARRAY_SIZE(ssp1_pins[1]), 2712 .npins = ARRAY_SIZE(ssp1_pins[1]),
2713 .modemuxs = ssp1_36_39_modemux, 2713 .modemuxs = ssp1_36_39_modemux,
2714 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux), 2714 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2715 }, { 2715 }, {
2716 .name = "ssp1_48_51_grp", 2716 .name = "ssp1_48_51_grp",
2717 .pins = ssp1_pins[2], 2717 .pins = ssp1_pins[2],
2718 .npins = ARRAY_SIZE(ssp1_pins[2]), 2718 .npins = ARRAY_SIZE(ssp1_pins[2]),
2719 .modemuxs = ssp1_48_51_modemux, 2719 .modemuxs = ssp1_48_51_modemux,
2720 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux), 2720 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2721 }, { 2721 }, {
2722 .name = "ssp1_65_68_grp", 2722 .name = "ssp1_65_68_grp",
2723 .pins = ssp1_pins[3], 2723 .pins = ssp1_pins[3],
2724 .npins = ARRAY_SIZE(ssp1_pins[3]), 2724 .npins = ARRAY_SIZE(ssp1_pins[3]),
2725 .modemuxs = ssp1_65_68_modemux, 2725 .modemuxs = ssp1_65_68_modemux,
2726 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux), 2726 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2727 }, { 2727 }, {
2728 .name = "ssp1_94_97_grp", 2728 .name = "ssp1_94_97_grp",
2729 .pins = ssp1_pins[4], 2729 .pins = ssp1_pins[4],
2730 .npins = ARRAY_SIZE(ssp1_pins[4]), 2730 .npins = ARRAY_SIZE(ssp1_pins[4]),
2731 .modemuxs = ssp1_94_97_modemux, 2731 .modemuxs = ssp1_94_97_modemux,
2732 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux), 2732 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2733 }, 2733 },
2734 }; 2734 };
2735 2735
2736 static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp", 2736 static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2737 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp" 2737 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2738 }; 2738 };
2739 static struct spear_function ssp1_function = { 2739 static struct spear_function ssp1_function = {
2740 .name = "ssp1", 2740 .name = "ssp1",
2741 .groups = ssp1_grps, 2741 .groups = ssp1_grps,
2742 .ngroups = ARRAY_SIZE(ssp1_grps), 2742 .ngroups = ARRAY_SIZE(ssp1_grps),
2743 }; 2743 };
2744 2744
2745 /* Pad multiplexing for SSP2 device */ 2745 /* Pad multiplexing for SSP2 device */
2746 static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 }, 2746 static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2747 { 61, 64 }, { 90, 93 } }; 2747 { 61, 64 }, { 90, 93 } };
2748 static struct spear_muxreg ssp2_muxreg[] = { 2748 static struct spear_muxreg ssp2_muxreg[] = {
2749 { 2749 {
2750 .reg = PMX_CONFIG_REG, 2750 .reg = PMX_CONFIG_REG,
2751 .mask = PMX_MII_MASK, 2751 .mask = PMX_MII_MASK,
2752 .val = 0, 2752 .val = 0,
2753 }, 2753 },
2754 }; 2754 };
2755 2755
2756 static struct spear_muxreg ssp2_ext_13_16_muxreg[] = { 2756 static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2757 { 2757 {
2758 .reg = IP_SEL_PAD_10_19_REG, 2758 .reg = IP_SEL_PAD_10_19_REG,
2759 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, 2759 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2760 .val = PMX_SSP2_PL_13_14_15_16_VAL, 2760 .val = PMX_SSP2_PL_13_14_15_16_VAL,
2761 }, { 2761 }, {
2762 .reg = IP_SEL_MIX_PAD_REG, 2762 .reg = IP_SEL_MIX_PAD_REG,
2763 .mask = PMX_SSP2_PORT_SEL_MASK, 2763 .mask = PMX_SSP2_PORT_SEL_MASK,
2764 .val = PMX_SSP2_PORT_13_TO_16_VAL, 2764 .val = PMX_SSP2_PORT_13_TO_16_VAL,
2765 }, 2765 },
2766 }; 2766 };
2767 2767
2768 static struct spear_muxreg ssp2_ext_32_35_muxreg[] = { 2768 static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2769 { 2769 {
2770 .reg = PMX_CONFIG_REG, 2770 .reg = PMX_CONFIG_REG,
2771 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | 2771 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2772 PMX_GPIO_PIN5_MASK, 2772 PMX_GPIO_PIN5_MASK,
2773 .val = 0, 2773 .val = 0,
2774 }, { 2774 }, {
2775 .reg = IP_SEL_PAD_30_39_REG, 2775 .reg = IP_SEL_PAD_30_39_REG,
2776 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, 2776 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2777 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | 2777 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2778 PMX_SSP2_PL_35_VAL, 2778 PMX_SSP2_PL_35_VAL,
2779 }, { 2779 }, {
2780 .reg = IP_SEL_MIX_PAD_REG, 2780 .reg = IP_SEL_MIX_PAD_REG,
2781 .mask = PMX_SSP2_PORT_SEL_MASK, 2781 .mask = PMX_SSP2_PORT_SEL_MASK,
2782 .val = PMX_SSP2_PORT_32_TO_35_VAL, 2782 .val = PMX_SSP2_PORT_32_TO_35_VAL,
2783 }, 2783 },
2784 }; 2784 };
2785 2785
2786 static struct spear_muxreg ssp2_ext_44_47_muxreg[] = { 2786 static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2787 { 2787 {
2788 .reg = PMX_CONFIG_REG, 2788 .reg = PMX_CONFIG_REG,
2789 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 2789 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2790 .val = 0, 2790 .val = 0,
2791 }, { 2791 }, {
2792 .reg = IP_SEL_PAD_40_49_REG, 2792 .reg = IP_SEL_PAD_40_49_REG,
2793 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, 2793 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2794 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, 2794 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2795 }, { 2795 }, {
2796 .reg = IP_SEL_MIX_PAD_REG, 2796 .reg = IP_SEL_MIX_PAD_REG,
2797 .mask = PMX_SSP2_PORT_SEL_MASK, 2797 .mask = PMX_SSP2_PORT_SEL_MASK,
2798 .val = PMX_SSP2_PORT_44_TO_47_VAL, 2798 .val = PMX_SSP2_PORT_44_TO_47_VAL,
2799 }, 2799 },
2800 }; 2800 };
2801 2801
2802 static struct spear_muxreg ssp2_ext_61_64_muxreg[] = { 2802 static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2803 { 2803 {
2804 .reg = IP_SEL_PAD_60_69_REG, 2804 .reg = IP_SEL_PAD_60_69_REG,
2805 .mask = PMX_PL_61_TO_64_MASK, 2805 .mask = PMX_PL_61_TO_64_MASK,
2806 .val = PMX_SSP2_PL_61_TO_64_VAL, 2806 .val = PMX_SSP2_PL_61_TO_64_VAL,
2807 }, { 2807 }, {
2808 .reg = IP_SEL_MIX_PAD_REG, 2808 .reg = IP_SEL_MIX_PAD_REG,
2809 .mask = PMX_SSP2_PORT_SEL_MASK, 2809 .mask = PMX_SSP2_PORT_SEL_MASK,
2810 .val = PMX_SSP2_PORT_61_TO_64_VAL, 2810 .val = PMX_SSP2_PORT_61_TO_64_VAL,
2811 }, 2811 },
2812 }; 2812 };
2813 2813
2814 static struct spear_muxreg ssp2_ext_90_93_muxreg[] = { 2814 static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2815 { 2815 {
2816 .reg = IP_SEL_PAD_90_99_REG, 2816 .reg = IP_SEL_PAD_90_99_REG,
2817 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, 2817 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2818 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, 2818 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2819 }, { 2819 }, {
2820 .reg = IP_SEL_MIX_PAD_REG, 2820 .reg = IP_SEL_MIX_PAD_REG,
2821 .mask = PMX_SSP2_PORT_SEL_MASK, 2821 .mask = PMX_SSP2_PORT_SEL_MASK,
2822 .val = PMX_SSP2_PORT_90_TO_93_VAL, 2822 .val = PMX_SSP2_PORT_90_TO_93_VAL,
2823 }, 2823 },
2824 }; 2824 };
2825 2825
2826 static struct spear_modemux ssp2_13_16_modemux[] = { 2826 static struct spear_modemux ssp2_13_16_modemux[] = {
2827 { 2827 {
2828 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, 2828 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2829 .muxregs = ssp2_muxreg, 2829 .muxregs = ssp2_muxreg,
2830 .nmuxregs = ARRAY_SIZE(ssp2_muxreg), 2830 .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2831 }, { 2831 }, {
2832 .modes = EXTENDED_MODE, 2832 .modes = EXTENDED_MODE,
2833 .muxregs = ssp2_ext_13_16_muxreg, 2833 .muxregs = ssp2_ext_13_16_muxreg,
2834 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg), 2834 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2835 }, 2835 },
2836 }; 2836 };
2837 2837
2838 static struct spear_modemux ssp2_32_35_modemux[] = { 2838 static struct spear_modemux ssp2_32_35_modemux[] = {
2839 { 2839 {
2840 .modes = EXTENDED_MODE, 2840 .modes = EXTENDED_MODE,
2841 .muxregs = ssp2_ext_32_35_muxreg, 2841 .muxregs = ssp2_ext_32_35_muxreg,
2842 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg), 2842 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2843 }, 2843 },
2844 }; 2844 };
2845 2845
2846 static struct spear_modemux ssp2_44_47_modemux[] = { 2846 static struct spear_modemux ssp2_44_47_modemux[] = {
2847 { 2847 {
2848 .modes = EXTENDED_MODE, 2848 .modes = EXTENDED_MODE,
2849 .muxregs = ssp2_ext_44_47_muxreg, 2849 .muxregs = ssp2_ext_44_47_muxreg,
2850 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg), 2850 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2851 }, 2851 },
2852 }; 2852 };
2853 2853
2854 static struct spear_modemux ssp2_61_64_modemux[] = { 2854 static struct spear_modemux ssp2_61_64_modemux[] = {
2855 { 2855 {
2856 .modes = EXTENDED_MODE, 2856 .modes = EXTENDED_MODE,
2857 .muxregs = ssp2_ext_61_64_muxreg, 2857 .muxregs = ssp2_ext_61_64_muxreg,
2858 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg), 2858 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2859 }, 2859 },
2860 }; 2860 };
2861 2861
2862 static struct spear_modemux ssp2_90_93_modemux[] = { 2862 static struct spear_modemux ssp2_90_93_modemux[] = {
2863 { 2863 {
2864 .modes = EXTENDED_MODE, 2864 .modes = EXTENDED_MODE,
2865 .muxregs = ssp2_ext_90_93_muxreg, 2865 .muxregs = ssp2_ext_90_93_muxreg,
2866 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg), 2866 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2867 }, 2867 },
2868 }; 2868 };
2869 2869
2870 static struct spear_pingroup ssp2_pingroup[] = { 2870 static struct spear_pingroup ssp2_pingroup[] = {
2871 { 2871 {
2872 .name = "ssp2_13_16_grp", 2872 .name = "ssp2_13_16_grp",
2873 .pins = ssp2_pins[0], 2873 .pins = ssp2_pins[0],
2874 .npins = ARRAY_SIZE(ssp2_pins[0]), 2874 .npins = ARRAY_SIZE(ssp2_pins[0]),
2875 .modemuxs = ssp2_13_16_modemux, 2875 .modemuxs = ssp2_13_16_modemux,
2876 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux), 2876 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2877 }, { 2877 }, {
2878 .name = "ssp2_32_35_grp", 2878 .name = "ssp2_32_35_grp",
2879 .pins = ssp2_pins[1], 2879 .pins = ssp2_pins[1],
2880 .npins = ARRAY_SIZE(ssp2_pins[1]), 2880 .npins = ARRAY_SIZE(ssp2_pins[1]),
2881 .modemuxs = ssp2_32_35_modemux, 2881 .modemuxs = ssp2_32_35_modemux,
2882 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux), 2882 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2883 }, { 2883 }, {
2884 .name = "ssp2_44_47_grp", 2884 .name = "ssp2_44_47_grp",
2885 .pins = ssp2_pins[2], 2885 .pins = ssp2_pins[2],
2886 .npins = ARRAY_SIZE(ssp2_pins[2]), 2886 .npins = ARRAY_SIZE(ssp2_pins[2]),
2887 .modemuxs = ssp2_44_47_modemux, 2887 .modemuxs = ssp2_44_47_modemux,
2888 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux), 2888 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2889 }, { 2889 }, {
2890 .name = "ssp2_61_64_grp", 2890 .name = "ssp2_61_64_grp",
2891 .pins = ssp2_pins[3], 2891 .pins = ssp2_pins[3],
2892 .npins = ARRAY_SIZE(ssp2_pins[3]), 2892 .npins = ARRAY_SIZE(ssp2_pins[3]),
2893 .modemuxs = ssp2_61_64_modemux, 2893 .modemuxs = ssp2_61_64_modemux,
2894 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux), 2894 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2895 }, { 2895 }, {
2896 .name = "ssp2_90_93_grp", 2896 .name = "ssp2_90_93_grp",
2897 .pins = ssp2_pins[4], 2897 .pins = ssp2_pins[4],
2898 .npins = ARRAY_SIZE(ssp2_pins[4]), 2898 .npins = ARRAY_SIZE(ssp2_pins[4]),
2899 .modemuxs = ssp2_90_93_modemux, 2899 .modemuxs = ssp2_90_93_modemux,
2900 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux), 2900 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2901 }, 2901 },
2902 }; 2902 };
2903 2903
2904 static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp", 2904 static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2905 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" }; 2905 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2906 static struct spear_function ssp2_function = { 2906 static struct spear_function ssp2_function = {
2907 .name = "ssp2", 2907 .name = "ssp2",
2908 .groups = ssp2_grps, 2908 .groups = ssp2_grps,
2909 .ngroups = ARRAY_SIZE(ssp2_grps), 2909 .ngroups = ARRAY_SIZE(ssp2_grps),
2910 }; 2910 };
2911 2911
2912 /* Pad multiplexing for cadence mii2 as mii device */ 2912 /* Pad multiplexing for cadence mii2 as mii device */
2913 static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 2913 static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2914 90, 91, 92, 93, 94, 95, 96, 97 }; 2914 90, 91, 92, 93, 94, 95, 96, 97 };
2915 static struct spear_muxreg mii2_muxreg[] = { 2915 static struct spear_muxreg mii2_muxreg[] = {
2916 { 2916 {
2917 .reg = IP_SEL_PAD_80_89_REG, 2917 .reg = IP_SEL_PAD_80_89_REG,
2918 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | 2918 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2919 PMX_PL_88_89_MASK, 2919 PMX_PL_88_89_MASK,
2920 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | 2920 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2921 PMX_MII2_PL_88_89_VAL, 2921 PMX_MII2_PL_88_89_VAL,
2922 }, { 2922 }, {
2923 .reg = IP_SEL_PAD_90_99_REG, 2923 .reg = IP_SEL_PAD_90_99_REG,
2924 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | 2924 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2925 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, 2925 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2926 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | 2926 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2927 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL, 2927 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2928 }, { 2928 }, {
2929 .reg = EXT_CTRL_REG, 2929 .reg = EXT_CTRL_REG,
2930 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | 2930 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2931 (MAC_MODE_MASK << MAC1_MODE_SHIFT) | 2931 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2932 MII_MDIO_MASK, 2932 MII_MDIO_MASK,
2933 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | 2933 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2934 (MAC_MODE_MII << MAC1_MODE_SHIFT) | 2934 (MAC_MODE_MII << MAC1_MODE_SHIFT) |
2935 MII_MDIO_81_VAL, 2935 MII_MDIO_81_VAL,
2936 }, 2936 },
2937 }; 2937 };
2938 2938
2939 static struct spear_modemux mii2_modemux[] = { 2939 static struct spear_modemux mii2_modemux[] = {
2940 { 2940 {
2941 .modes = EXTENDED_MODE, 2941 .modes = EXTENDED_MODE,
2942 .muxregs = mii2_muxreg, 2942 .muxregs = mii2_muxreg,
2943 .nmuxregs = ARRAY_SIZE(mii2_muxreg), 2943 .nmuxregs = ARRAY_SIZE(mii2_muxreg),
2944 }, 2944 },
2945 }; 2945 };
2946 2946
2947 static struct spear_pingroup mii2_pingroup = { 2947 static struct spear_pingroup mii2_pingroup = {
2948 .name = "mii2_grp", 2948 .name = "mii2_grp",
2949 .pins = mii2_pins, 2949 .pins = mii2_pins,
2950 .npins = ARRAY_SIZE(mii2_pins), 2950 .npins = ARRAY_SIZE(mii2_pins),
2951 .modemuxs = mii2_modemux, 2951 .modemuxs = mii2_modemux,
2952 .nmodemuxs = ARRAY_SIZE(mii2_modemux), 2952 .nmodemuxs = ARRAY_SIZE(mii2_modemux),
2953 }; 2953 };
2954 2954
2955 static const char *const mii2_grps[] = { "mii2_grp" }; 2955 static const char *const mii2_grps[] = { "mii2_grp" };
2956 static struct spear_function mii2_function = { 2956 static struct spear_function mii2_function = {
2957 .name = "mii2", 2957 .name = "mii2",
2958 .groups = mii2_grps, 2958 .groups = mii2_grps,
2959 .ngroups = ARRAY_SIZE(mii2_grps), 2959 .ngroups = ARRAY_SIZE(mii2_grps),
2960 }; 2960 };
2961 2961
2962 /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ 2962 /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2963 static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 2963 static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2964 21, 22, 23, 24, 25, 26, 27 }; 2964 21, 22, 23, 24, 25, 26, 27 };
2965 static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; 2965 static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2966 static struct spear_muxreg mii0_1_muxreg[] = { 2966 static struct spear_muxreg mii0_1_muxreg[] = {
2967 { 2967 {
2968 .reg = PMX_CONFIG_REG, 2968 .reg = PMX_CONFIG_REG,
2969 .mask = PMX_MII_MASK, 2969 .mask = PMX_MII_MASK,
2970 .val = 0, 2970 .val = 0,
2971 }, 2971 },
2972 }; 2972 };
2973 2973
2974 static struct spear_muxreg smii0_1_ext_muxreg[] = { 2974 static struct spear_muxreg smii0_1_ext_muxreg[] = {
2975 { 2975 {
2976 .reg = IP_SEL_PAD_10_19_REG, 2976 .reg = IP_SEL_PAD_10_19_REG,
2977 .mask = PMX_PL_10_11_MASK, 2977 .mask = PMX_PL_10_11_MASK,
2978 .val = PMX_SMII_PL_10_11_VAL, 2978 .val = PMX_SMII_PL_10_11_VAL,
2979 }, { 2979 }, {
2980 .reg = IP_SEL_PAD_20_29_REG, 2980 .reg = IP_SEL_PAD_20_29_REG,
2981 .mask = PMX_PL_21_TO_27_MASK, 2981 .mask = PMX_PL_21_TO_27_MASK,
2982 .val = PMX_SMII_PL_21_TO_27_VAL, 2982 .val = PMX_SMII_PL_21_TO_27_VAL,
2983 }, { 2983 }, {
2984 .reg = EXT_CTRL_REG, 2984 .reg = EXT_CTRL_REG,
2985 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | 2985 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2986 (MAC_MODE_MASK << MAC1_MODE_SHIFT) | 2986 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2987 MII_MDIO_MASK, 2987 MII_MDIO_MASK,
2988 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) 2988 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2989 | (MAC_MODE_SMII << MAC1_MODE_SHIFT) 2989 | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2990 | MII_MDIO_10_11_VAL, 2990 | MII_MDIO_10_11_VAL,
2991 }, 2991 },
2992 }; 2992 };
2993 2993
2994 static struct spear_muxreg rmii0_1_ext_muxreg[] = { 2994 static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2995 { 2995 {
2996 .reg = IP_SEL_PAD_10_19_REG, 2996 .reg = IP_SEL_PAD_10_19_REG,
2997 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | 2997 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2998 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK, 2998 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2999 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | 2999 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
3000 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL | 3000 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
3001 PMX_RMII_PL_19_VAL, 3001 PMX_RMII_PL_19_VAL,
3002 }, { 3002 }, {
3003 .reg = IP_SEL_PAD_20_29_REG, 3003 .reg = IP_SEL_PAD_20_29_REG,
3004 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, 3004 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3005 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, 3005 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3006 }, { 3006 }, {
3007 .reg = EXT_CTRL_REG, 3007 .reg = EXT_CTRL_REG,
3008 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | 3008 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3009 (MAC_MODE_MASK << MAC1_MODE_SHIFT) | 3009 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3010 MII_MDIO_MASK, 3010 MII_MDIO_MASK,
3011 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) 3011 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3012 | (MAC_MODE_RMII << MAC1_MODE_SHIFT) 3012 | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3013 | MII_MDIO_10_11_VAL, 3013 | MII_MDIO_10_11_VAL,
3014 }, 3014 },
3015 }; 3015 };
3016 3016
3017 static struct spear_modemux mii0_1_modemux[][2] = { 3017 static struct spear_modemux mii0_1_modemux[][2] = {
3018 { 3018 {
3019 /* configure as smii */ 3019 /* configure as smii */
3020 { 3020 {
3021 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | 3021 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3022 SMALL_PRINTERS_MODE | EXTENDED_MODE, 3022 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3023 .muxregs = mii0_1_muxreg, 3023 .muxregs = mii0_1_muxreg,
3024 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), 3024 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3025 }, { 3025 }, {
3026 .modes = EXTENDED_MODE, 3026 .modes = EXTENDED_MODE,
3027 .muxregs = smii0_1_ext_muxreg, 3027 .muxregs = smii0_1_ext_muxreg,
3028 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg), 3028 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3029 }, 3029 },
3030 }, { 3030 }, {
3031 /* configure as rmii */ 3031 /* configure as rmii */
3032 { 3032 {
3033 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | 3033 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3034 SMALL_PRINTERS_MODE | EXTENDED_MODE, 3034 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3035 .muxregs = mii0_1_muxreg, 3035 .muxregs = mii0_1_muxreg,
3036 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), 3036 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3037 }, { 3037 }, {
3038 .modes = EXTENDED_MODE, 3038 .modes = EXTENDED_MODE,
3039 .muxregs = rmii0_1_ext_muxreg, 3039 .muxregs = rmii0_1_ext_muxreg,
3040 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg), 3040 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3041 }, 3041 },
3042 }, 3042 },
3043 }; 3043 };
3044 3044
3045 static struct spear_pingroup mii0_1_pingroup[] = { 3045 static struct spear_pingroup mii0_1_pingroup[] = {
3046 { 3046 {
3047 .name = "smii0_1_grp", 3047 .name = "smii0_1_grp",
3048 .pins = smii0_1_pins, 3048 .pins = smii0_1_pins,
3049 .npins = ARRAY_SIZE(smii0_1_pins), 3049 .npins = ARRAY_SIZE(smii0_1_pins),
3050 .modemuxs = mii0_1_modemux[0], 3050 .modemuxs = mii0_1_modemux[0],
3051 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]), 3051 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3052 }, { 3052 }, {
3053 .name = "rmii0_1_grp", 3053 .name = "rmii0_1_grp",
3054 .pins = rmii0_1_pins, 3054 .pins = rmii0_1_pins,
3055 .npins = ARRAY_SIZE(rmii0_1_pins), 3055 .npins = ARRAY_SIZE(rmii0_1_pins),
3056 .modemuxs = mii0_1_modemux[1], 3056 .modemuxs = mii0_1_modemux[1],
3057 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]), 3057 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3058 }, 3058 },
3059 }; 3059 };
3060 3060
3061 static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" }; 3061 static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3062 static struct spear_function mii0_1_function = { 3062 static struct spear_function mii0_1_function = {
3063 .name = "mii0_1", 3063 .name = "mii0_1",
3064 .groups = mii0_1_grps, 3064 .groups = mii0_1_grps,
3065 .ngroups = ARRAY_SIZE(mii0_1_grps), 3065 .ngroups = ARRAY_SIZE(mii0_1_grps),
3066 }; 3066 };
3067 3067
3068 /* Pad multiplexing for i2c1 device */ 3068 /* Pad multiplexing for i2c1 device */
3069 static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } }; 3069 static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3070 static struct spear_muxreg i2c1_ext_8_9_muxreg[] = { 3070 static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3071 { 3071 {
3072 .reg = PMX_CONFIG_REG, 3072 .reg = PMX_CONFIG_REG,
3073 .mask = PMX_SSP_CS_MASK, 3073 .mask = PMX_SSP_CS_MASK,
3074 .val = 0, 3074 .val = 0,
3075 }, { 3075 }, {
3076 .reg = IP_SEL_PAD_0_9_REG, 3076 .reg = IP_SEL_PAD_0_9_REG,
3077 .mask = PMX_PL_8_9_MASK, 3077 .mask = PMX_PL_8_9_MASK,
3078 .val = PMX_I2C1_PL_8_9_VAL, 3078 .val = PMX_I2C1_PL_8_9_VAL,
3079 }, { 3079 }, {
3080 .reg = IP_SEL_MIX_PAD_REG, 3080 .reg = IP_SEL_MIX_PAD_REG,
3081 .mask = PMX_I2C1_PORT_SEL_MASK, 3081 .mask = PMX_I2C1_PORT_SEL_MASK,
3082 .val = PMX_I2C1_PORT_8_9_VAL, 3082 .val = PMX_I2C1_PORT_8_9_VAL,
3083 }, 3083 },
3084 }; 3084 };
3085 3085
3086 static struct spear_muxreg i2c1_ext_98_99_muxreg[] = { 3086 static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3087 { 3087 {
3088 .reg = IP_SEL_PAD_90_99_REG, 3088 .reg = IP_SEL_PAD_90_99_REG,
3089 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, 3089 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3090 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, 3090 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3091 }, { 3091 }, {
3092 .reg = IP_SEL_MIX_PAD_REG, 3092 .reg = IP_SEL_MIX_PAD_REG,
3093 .mask = PMX_I2C1_PORT_SEL_MASK, 3093 .mask = PMX_I2C1_PORT_SEL_MASK,
3094 .val = PMX_I2C1_PORT_98_99_VAL, 3094 .val = PMX_I2C1_PORT_98_99_VAL,
3095 }, 3095 },
3096 }; 3096 };
3097 3097
3098 static struct spear_modemux i2c1_modemux[][1] = { 3098 static struct spear_modemux i2c1_modemux[][1] = {
3099 { 3099 {
3100 /* Select signals on pins 8-9 */ 3100 /* Select signals on pins 8-9 */
3101 { 3101 {
3102 .modes = EXTENDED_MODE, 3102 .modes = EXTENDED_MODE,
3103 .muxregs = i2c1_ext_8_9_muxreg, 3103 .muxregs = i2c1_ext_8_9_muxreg,
3104 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg), 3104 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3105 }, 3105 },
3106 }, { 3106 }, {
3107 /* Select signals on pins 98-99 */ 3107 /* Select signals on pins 98-99 */
3108 { 3108 {
3109 .modes = EXTENDED_MODE, 3109 .modes = EXTENDED_MODE,
3110 .muxregs = i2c1_ext_98_99_muxreg, 3110 .muxregs = i2c1_ext_98_99_muxreg,
3111 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg), 3111 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3112 }, 3112 },
3113 }, 3113 },
3114 }; 3114 };
3115 3115
3116 static struct spear_pingroup i2c1_pingroup[] = { 3116 static struct spear_pingroup i2c1_pingroup[] = {
3117 { 3117 {
3118 .name = "i2c1_8_9_grp", 3118 .name = "i2c1_8_9_grp",
3119 .pins = i2c1_pins[0], 3119 .pins = i2c1_pins[0],
3120 .npins = ARRAY_SIZE(i2c1_pins[0]), 3120 .npins = ARRAY_SIZE(i2c1_pins[0]),
3121 .modemuxs = i2c1_modemux[0], 3121 .modemuxs = i2c1_modemux[0],
3122 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]), 3122 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3123 }, { 3123 }, {
3124 .name = "i2c1_98_99_grp", 3124 .name = "i2c1_98_99_grp",
3125 .pins = i2c1_pins[1], 3125 .pins = i2c1_pins[1],
3126 .npins = ARRAY_SIZE(i2c1_pins[1]), 3126 .npins = ARRAY_SIZE(i2c1_pins[1]),
3127 .modemuxs = i2c1_modemux[1], 3127 .modemuxs = i2c1_modemux[1],
3128 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]), 3128 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3129 }, 3129 },
3130 }; 3130 };
3131 3131
3132 static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" }; 3132 static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3133 static struct spear_function i2c1_function = { 3133 static struct spear_function i2c1_function = {
3134 .name = "i2c1", 3134 .name = "i2c1",
3135 .groups = i2c1_grps, 3135 .groups = i2c1_grps,
3136 .ngroups = ARRAY_SIZE(i2c1_grps), 3136 .ngroups = ARRAY_SIZE(i2c1_grps),
3137 }; 3137 };
3138 3138
3139 /* Pad multiplexing for i2c2 device */ 3139 /* Pad multiplexing for i2c2 device */
3140 static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 }, 3140 static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3141 { 75, 76 }, { 96, 97 } }; 3141 { 75, 76 }, { 96, 97 } };
3142 static struct spear_muxreg i2c2_ext_0_1_muxreg[] = { 3142 static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3143 { 3143 {
3144 .reg = PMX_CONFIG_REG, 3144 .reg = PMX_CONFIG_REG,
3145 .mask = PMX_FIRDA_MASK, 3145 .mask = PMX_FIRDA_MASK,
3146 .val = 0, 3146 .val = 0,
3147 }, { 3147 }, {
3148 .reg = IP_SEL_PAD_0_9_REG, 3148 .reg = IP_SEL_PAD_0_9_REG,
3149 .mask = PMX_PL_0_1_MASK, 3149 .mask = PMX_PL_0_1_MASK,
3150 .val = PMX_I2C2_PL_0_1_VAL, 3150 .val = PMX_I2C2_PL_0_1_VAL,
3151 }, { 3151 }, {
3152 .reg = IP_SEL_MIX_PAD_REG, 3152 .reg = IP_SEL_MIX_PAD_REG,
3153 .mask = PMX_I2C2_PORT_SEL_MASK, 3153 .mask = PMX_I2C2_PORT_SEL_MASK,
3154 .val = PMX_I2C2_PORT_0_1_VAL, 3154 .val = PMX_I2C2_PORT_0_1_VAL,
3155 }, 3155 },
3156 }; 3156 };
3157 3157
3158 static struct spear_muxreg i2c2_ext_2_3_muxreg[] = { 3158 static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3159 { 3159 {
3160 .reg = PMX_CONFIG_REG, 3160 .reg = PMX_CONFIG_REG,
3161 .mask = PMX_UART0_MASK, 3161 .mask = PMX_UART0_MASK,
3162 .val = 0, 3162 .val = 0,
3163 }, { 3163 }, {
3164 .reg = IP_SEL_PAD_0_9_REG, 3164 .reg = IP_SEL_PAD_0_9_REG,
3165 .mask = PMX_PL_2_3_MASK, 3165 .mask = PMX_PL_2_3_MASK,
3166 .val = PMX_I2C2_PL_2_3_VAL, 3166 .val = PMX_I2C2_PL_2_3_VAL,
3167 }, { 3167 }, {
3168 .reg = IP_SEL_MIX_PAD_REG, 3168 .reg = IP_SEL_MIX_PAD_REG,
3169 .mask = PMX_I2C2_PORT_SEL_MASK, 3169 .mask = PMX_I2C2_PORT_SEL_MASK,
3170 .val = PMX_I2C2_PORT_2_3_VAL, 3170 .val = PMX_I2C2_PORT_2_3_VAL,
3171 }, 3171 },
3172 }; 3172 };
3173 3173
3174 static struct spear_muxreg i2c2_ext_19_20_muxreg[] = { 3174 static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3175 { 3175 {
3176 .reg = PMX_CONFIG_REG, 3176 .reg = PMX_CONFIG_REG,
3177 .mask = PMX_MII_MASK, 3177 .mask = PMX_MII_MASK,
3178 .val = 0, 3178 .val = 0,
3179 }, { 3179 }, {
3180 .reg = IP_SEL_PAD_10_19_REG, 3180 .reg = IP_SEL_PAD_10_19_REG,
3181 .mask = PMX_PL_19_MASK, 3181 .mask = PMX_PL_19_MASK,
3182 .val = PMX_I2C2_PL_19_VAL, 3182 .val = PMX_I2C2_PL_19_VAL,
3183 }, { 3183 }, {
3184 .reg = IP_SEL_PAD_20_29_REG, 3184 .reg = IP_SEL_PAD_20_29_REG,
3185 .mask = PMX_PL_20_MASK, 3185 .mask = PMX_PL_20_MASK,
3186 .val = PMX_I2C2_PL_20_VAL, 3186 .val = PMX_I2C2_PL_20_VAL,
3187 }, { 3187 }, {
3188 .reg = IP_SEL_MIX_PAD_REG, 3188 .reg = IP_SEL_MIX_PAD_REG,
3189 .mask = PMX_I2C2_PORT_SEL_MASK, 3189 .mask = PMX_I2C2_PORT_SEL_MASK,
3190 .val = PMX_I2C2_PORT_19_20_VAL, 3190 .val = PMX_I2C2_PORT_19_20_VAL,
3191 }, 3191 },
3192 }; 3192 };
3193 3193
3194 static struct spear_muxreg i2c2_ext_75_76_muxreg[] = { 3194 static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3195 { 3195 {
3196 .reg = IP_SEL_PAD_70_79_REG, 3196 .reg = IP_SEL_PAD_70_79_REG,
3197 .mask = PMX_PL_75_76_MASK, 3197 .mask = PMX_PL_75_76_MASK,
3198 .val = PMX_I2C2_PL_75_76_VAL, 3198 .val = PMX_I2C2_PL_75_76_VAL,
3199 }, { 3199 }, {
3200 .reg = IP_SEL_MIX_PAD_REG, 3200 .reg = IP_SEL_MIX_PAD_REG,
3201 .mask = PMX_I2C2_PORT_SEL_MASK, 3201 .mask = PMX_I2C2_PORT_SEL_MASK,
3202 .val = PMX_I2C2_PORT_75_76_VAL, 3202 .val = PMX_I2C2_PORT_75_76_VAL,
3203 }, 3203 },
3204 }; 3204 };
3205 3205
3206 static struct spear_muxreg i2c2_ext_96_97_muxreg[] = { 3206 static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3207 { 3207 {
3208 .reg = IP_SEL_PAD_90_99_REG, 3208 .reg = IP_SEL_PAD_90_99_REG,
3209 .mask = PMX_PL_96_97_MASK, 3209 .mask = PMX_PL_96_97_MASK,
3210 .val = PMX_I2C2_PL_96_97_VAL, 3210 .val = PMX_I2C2_PL_96_97_VAL,
3211 }, { 3211 }, {
3212 .reg = IP_SEL_MIX_PAD_REG, 3212 .reg = IP_SEL_MIX_PAD_REG,
3213 .mask = PMX_I2C2_PORT_SEL_MASK, 3213 .mask = PMX_I2C2_PORT_SEL_MASK,
3214 .val = PMX_I2C2_PORT_96_97_VAL, 3214 .val = PMX_I2C2_PORT_96_97_VAL,
3215 }, 3215 },
3216 }; 3216 };
3217 3217
3218 static struct spear_modemux i2c2_modemux[][1] = { 3218 static struct spear_modemux i2c2_modemux[][1] = {
3219 { 3219 {
3220 /* Select signals on pins 0_1 */ 3220 /* Select signals on pins 0_1 */
3221 { 3221 {
3222 .modes = EXTENDED_MODE, 3222 .modes = EXTENDED_MODE,
3223 .muxregs = i2c2_ext_0_1_muxreg, 3223 .muxregs = i2c2_ext_0_1_muxreg,
3224 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg), 3224 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3225 }, 3225 },
3226 }, { 3226 }, {
3227 /* Select signals on pins 2_3 */ 3227 /* Select signals on pins 2_3 */
3228 { 3228 {
3229 .modes = EXTENDED_MODE, 3229 .modes = EXTENDED_MODE,
3230 .muxregs = i2c2_ext_2_3_muxreg, 3230 .muxregs = i2c2_ext_2_3_muxreg,
3231 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg), 3231 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3232 }, 3232 },
3233 }, { 3233 }, {
3234 /* Select signals on pins 19_20 */ 3234 /* Select signals on pins 19_20 */
3235 { 3235 {
3236 .modes = EXTENDED_MODE, 3236 .modes = EXTENDED_MODE,
3237 .muxregs = i2c2_ext_19_20_muxreg, 3237 .muxregs = i2c2_ext_19_20_muxreg,
3238 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg), 3238 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3239 }, 3239 },
3240 }, { 3240 }, {
3241 /* Select signals on pins 75_76 */ 3241 /* Select signals on pins 75_76 */
3242 { 3242 {
3243 .modes = EXTENDED_MODE, 3243 .modes = EXTENDED_MODE,
3244 .muxregs = i2c2_ext_75_76_muxreg, 3244 .muxregs = i2c2_ext_75_76_muxreg,
3245 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg), 3245 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3246 }, 3246 },
3247 }, { 3247 }, {
3248 /* Select signals on pins 96_97 */ 3248 /* Select signals on pins 96_97 */
3249 { 3249 {
3250 .modes = EXTENDED_MODE, 3250 .modes = EXTENDED_MODE,
3251 .muxregs = i2c2_ext_96_97_muxreg, 3251 .muxregs = i2c2_ext_96_97_muxreg,
3252 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg), 3252 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3253 }, 3253 },
3254 }, 3254 },
3255 }; 3255 };
3256 3256
3257 static struct spear_pingroup i2c2_pingroup[] = { 3257 static struct spear_pingroup i2c2_pingroup[] = {
3258 { 3258 {
3259 .name = "i2c2_0_1_grp", 3259 .name = "i2c2_0_1_grp",
3260 .pins = i2c2_pins[0], 3260 .pins = i2c2_pins[0],
3261 .npins = ARRAY_SIZE(i2c2_pins[0]), 3261 .npins = ARRAY_SIZE(i2c2_pins[0]),
3262 .modemuxs = i2c2_modemux[0], 3262 .modemuxs = i2c2_modemux[0],
3263 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]), 3263 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3264 }, { 3264 }, {
3265 .name = "i2c2_2_3_grp", 3265 .name = "i2c2_2_3_grp",
3266 .pins = i2c2_pins[1], 3266 .pins = i2c2_pins[1],
3267 .npins = ARRAY_SIZE(i2c2_pins[1]), 3267 .npins = ARRAY_SIZE(i2c2_pins[1]),
3268 .modemuxs = i2c2_modemux[1], 3268 .modemuxs = i2c2_modemux[1],
3269 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]), 3269 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3270 }, { 3270 }, {
3271 .name = "i2c2_19_20_grp", 3271 .name = "i2c2_19_20_grp",
3272 .pins = i2c2_pins[2], 3272 .pins = i2c2_pins[2],
3273 .npins = ARRAY_SIZE(i2c2_pins[2]), 3273 .npins = ARRAY_SIZE(i2c2_pins[2]),
3274 .modemuxs = i2c2_modemux[2], 3274 .modemuxs = i2c2_modemux[2],
3275 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]), 3275 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3276 }, { 3276 }, {
3277 .name = "i2c2_75_76_grp", 3277 .name = "i2c2_75_76_grp",
3278 .pins = i2c2_pins[3], 3278 .pins = i2c2_pins[3],
3279 .npins = ARRAY_SIZE(i2c2_pins[3]), 3279 .npins = ARRAY_SIZE(i2c2_pins[3]),
3280 .modemuxs = i2c2_modemux[3], 3280 .modemuxs = i2c2_modemux[3],
3281 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]), 3281 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3282 }, { 3282 }, {
3283 .name = "i2c2_96_97_grp", 3283 .name = "i2c2_96_97_grp",
3284 .pins = i2c2_pins[4], 3284 .pins = i2c2_pins[4],
3285 .npins = ARRAY_SIZE(i2c2_pins[4]), 3285 .npins = ARRAY_SIZE(i2c2_pins[4]),
3286 .modemuxs = i2c2_modemux[4], 3286 .modemuxs = i2c2_modemux[4],
3287 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]), 3287 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3288 }, 3288 },
3289 }; 3289 };
3290 3290
3291 static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp", 3291 static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3292 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" }; 3292 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3293 static struct spear_function i2c2_function = { 3293 static struct spear_function i2c2_function = {
3294 .name = "i2c2", 3294 .name = "i2c2",
3295 .groups = i2c2_grps, 3295 .groups = i2c2_grps,
3296 .ngroups = ARRAY_SIZE(i2c2_grps), 3296 .ngroups = ARRAY_SIZE(i2c2_grps),
3297 }; 3297 };
3298 3298
3299 /* pingroups */ 3299 /* pingroups */
3300 static struct spear_pingroup *spear320_pingroups[] = { 3300 static struct spear_pingroup *spear320_pingroups[] = {
3301 SPEAR3XX_COMMON_PINGROUPS, 3301 SPEAR3XX_COMMON_PINGROUPS,
3302 &clcd_pingroup, 3302 &clcd_pingroup,
3303 &emi_pingroup, 3303 &emi_pingroup,
3304 &fsmc_8bit_pingroup, 3304 &fsmc_8bit_pingroup,
3305 &fsmc_16bit_pingroup, 3305 &fsmc_16bit_pingroup,
3306 &spp_pingroup, 3306 &spp_pingroup,
3307 &sdhci_led_pingroup, 3307 &sdhci_led_pingroup,
3308 &sdhci_pingroup[0], 3308 &sdhci_pingroup[0],
3309 &sdhci_pingroup[1], 3309 &sdhci_pingroup[1],
3310 &i2s_pingroup, 3310 &i2s_pingroup,
3311 &uart1_pingroup, 3311 &uart1_pingroup,
3312 &uart1_modem_pingroup[0], 3312 &uart1_modem_pingroup[0],
3313 &uart1_modem_pingroup[1], 3313 &uart1_modem_pingroup[1],
3314 &uart1_modem_pingroup[2], 3314 &uart1_modem_pingroup[2],
3315 &uart1_modem_pingroup[3], 3315 &uart1_modem_pingroup[3],
3316 &uart2_pingroup, 3316 &uart2_pingroup,
3317 &uart3_pingroup[0], 3317 &uart3_pingroup[0],
3318 &uart3_pingroup[1], 3318 &uart3_pingroup[1],
3319 &uart3_pingroup[2], 3319 &uart3_pingroup[2],
3320 &uart3_pingroup[3], 3320 &uart3_pingroup[3],
3321 &uart3_pingroup[4], 3321 &uart3_pingroup[4],
3322 &uart3_pingroup[5], 3322 &uart3_pingroup[5],
3323 &uart3_pingroup[6], 3323 &uart3_pingroup[6],
3324 &uart4_pingroup[0], 3324 &uart4_pingroup[0],
3325 &uart4_pingroup[1], 3325 &uart4_pingroup[1],
3326 &uart4_pingroup[2], 3326 &uart4_pingroup[2],
3327 &uart4_pingroup[3], 3327 &uart4_pingroup[3],
3328 &uart4_pingroup[4], 3328 &uart4_pingroup[4],
3329 &uart4_pingroup[5], 3329 &uart4_pingroup[5],
3330 &uart5_pingroup[0], 3330 &uart5_pingroup[0],
3331 &uart5_pingroup[1], 3331 &uart5_pingroup[1],
3332 &uart5_pingroup[2], 3332 &uart5_pingroup[2],
3333 &uart5_pingroup[3], 3333 &uart5_pingroup[3],
3334 &uart6_pingroup[0], 3334 &uart6_pingroup[0],
3335 &uart6_pingroup[1], 3335 &uart6_pingroup[1],
3336 &rs485_pingroup, 3336 &rs485_pingroup,
3337 &touchscreen_pingroup, 3337 &touchscreen_pingroup,
3338 &can0_pingroup, 3338 &can0_pingroup,
3339 &can1_pingroup, 3339 &can1_pingroup,
3340 &pwm0_1_pingroup[0], 3340 &pwm0_1_pingroup[0],
3341 &pwm0_1_pingroup[1], 3341 &pwm0_1_pingroup[1],
3342 &pwm0_1_pingroup[2], 3342 &pwm0_1_pingroup[2],
3343 &pwm0_1_pingroup[3], 3343 &pwm0_1_pingroup[3],
3344 &pwm0_1_pingroup[4], 3344 &pwm0_1_pingroup[4],
3345 &pwm0_1_pingroup[5], 3345 &pwm0_1_pingroup[5],
3346 &pwm0_1_pingroup[6], 3346 &pwm0_1_pingroup[6],
3347 &pwm2_pingroup[0], 3347 &pwm2_pingroup[0],
3348 &pwm2_pingroup[1], 3348 &pwm2_pingroup[1],
3349 &pwm2_pingroup[2], 3349 &pwm2_pingroup[2],
3350 &pwm2_pingroup[3], 3350 &pwm2_pingroup[3],
3351 &pwm2_pingroup[4], 3351 &pwm2_pingroup[4],
3352 &pwm2_pingroup[5], 3352 &pwm2_pingroup[5],
3353 &pwm2_pingroup[6], 3353 &pwm2_pingroup[6],
3354 &pwm3_pingroup[0], 3354 &pwm3_pingroup[0],
3355 &pwm3_pingroup[1], 3355 &pwm3_pingroup[1],
3356 &pwm3_pingroup[2], 3356 &pwm3_pingroup[2],
3357 &pwm3_pingroup[3], 3357 &pwm3_pingroup[3],
3358 &pwm3_pingroup[4], 3358 &pwm3_pingroup[4],
3359 &pwm3_pingroup[5], 3359 &pwm3_pingroup[5],
3360 &ssp1_pingroup[0], 3360 &ssp1_pingroup[0],
3361 &ssp1_pingroup[1], 3361 &ssp1_pingroup[1],
3362 &ssp1_pingroup[2], 3362 &ssp1_pingroup[2],
3363 &ssp1_pingroup[3], 3363 &ssp1_pingroup[3],
3364 &ssp1_pingroup[4], 3364 &ssp1_pingroup[4],
3365 &ssp2_pingroup[0], 3365 &ssp2_pingroup[0],
3366 &ssp2_pingroup[1], 3366 &ssp2_pingroup[1],
3367 &ssp2_pingroup[2], 3367 &ssp2_pingroup[2],
3368 &ssp2_pingroup[3], 3368 &ssp2_pingroup[3],
3369 &ssp2_pingroup[4], 3369 &ssp2_pingroup[4],
3370 &mii2_pingroup, 3370 &mii2_pingroup,
3371 &mii0_1_pingroup[0], 3371 &mii0_1_pingroup[0],
3372 &mii0_1_pingroup[1], 3372 &mii0_1_pingroup[1],
3373 &i2c1_pingroup[0], 3373 &i2c1_pingroup[0],
3374 &i2c1_pingroup[1], 3374 &i2c1_pingroup[1],
3375 &i2c2_pingroup[0], 3375 &i2c2_pingroup[0],
3376 &i2c2_pingroup[1], 3376 &i2c2_pingroup[1],
3377 &i2c2_pingroup[2], 3377 &i2c2_pingroup[2],
3378 &i2c2_pingroup[3], 3378 &i2c2_pingroup[3],
3379 &i2c2_pingroup[4], 3379 &i2c2_pingroup[4],
3380 }; 3380 };
3381 3381
3382 /* functions */ 3382 /* functions */
3383 static struct spear_function *spear320_functions[] = { 3383 static struct spear_function *spear320_functions[] = {
3384 SPEAR3XX_COMMON_FUNCTIONS, 3384 SPEAR3XX_COMMON_FUNCTIONS,
3385 &clcd_function, 3385 &clcd_function,
3386 &emi_function, 3386 &emi_function,
3387 &fsmc_function, 3387 &fsmc_function,
3388 &spp_function, 3388 &spp_function,
3389 &sdhci_function, 3389 &sdhci_function,
3390 &i2s_function, 3390 &i2s_function,
3391 &uart1_function, 3391 &uart1_function,
3392 &uart1_modem_function, 3392 &uart1_modem_function,
3393 &uart2_function, 3393 &uart2_function,
3394 &uart3_function, 3394 &uart3_function,
3395 &uart4_function, 3395 &uart4_function,
3396 &uart5_function, 3396 &uart5_function,
3397 &uart6_function, 3397 &uart6_function,
3398 &rs485_function, 3398 &rs485_function,
3399 &touchscreen_function, 3399 &touchscreen_function,
3400 &can0_function, 3400 &can0_function,
3401 &can1_function, 3401 &can1_function,
3402 &pwm0_1_function, 3402 &pwm0_1_function,
3403 &pwm2_function, 3403 &pwm2_function,
3404 &pwm3_function, 3404 &pwm3_function,
3405 &ssp1_function, 3405 &ssp1_function,
3406 &ssp2_function, 3406 &ssp2_function,
3407 &mii2_function, 3407 &mii2_function,
3408 &mii0_1_function, 3408 &mii0_1_function,
3409 &i2c1_function, 3409 &i2c1_function,
3410 &i2c2_function, 3410 &i2c2_function,
3411 }; 3411 };
3412 3412
3413 static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = { 3413 static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
3414 { 3414 {
3415 .compatible = "st,spear320-pinmux", 3415 .compatible = "st,spear320-pinmux",
3416 }, 3416 },
3417 {}, 3417 {},
3418 }; 3418 };
3419 3419
3420 static int __devinit spear320_pinctrl_probe(struct platform_device *pdev) 3420 static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
3421 { 3421 {
3422 int ret; 3422 int ret;
3423 3423
3424 spear3xx_machdata.groups = spear320_pingroups; 3424 spear3xx_machdata.groups = spear320_pingroups;
3425 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); 3425 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3426 spear3xx_machdata.functions = spear320_functions; 3426 spear3xx_machdata.functions = spear320_functions;
3427 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions); 3427 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3428 3428
3429 spear3xx_machdata.modes_supported = true; 3429 spear3xx_machdata.modes_supported = true;
3430 spear3xx_machdata.pmx_modes = spear320_pmx_modes; 3430 spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3431 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes); 3431 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3432 3432
3433 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); 3433 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3434 pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
3435 spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
3434 3436
3435 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); 3437 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3436 if (ret) 3438 if (ret)
3437 return ret; 3439 return ret;
3438 3440
3439 return 0; 3441 return 0;
3440 } 3442 }
3441 3443
3442 static int __devexit spear320_pinctrl_remove(struct platform_device *pdev) 3444 static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
3443 { 3445 {
3444 return spear_pinctrl_remove(pdev); 3446 return spear_pinctrl_remove(pdev);
3445 } 3447 }
3446 3448
3447 static struct platform_driver spear320_pinctrl_driver = { 3449 static struct platform_driver spear320_pinctrl_driver = {
3448 .driver = { 3450 .driver = {
3449 .name = DRIVER_NAME, 3451 .name = DRIVER_NAME,
3450 .owner = THIS_MODULE, 3452 .owner = THIS_MODULE,
3451 .of_match_table = spear320_pinctrl_of_match, 3453 .of_match_table = spear320_pinctrl_of_match,
3452 }, 3454 },
3453 .probe = spear320_pinctrl_probe, 3455 .probe = spear320_pinctrl_probe,
3454 .remove = __devexit_p(spear320_pinctrl_remove), 3456 .remove = __devexit_p(spear320_pinctrl_remove),
3455 }; 3457 };
3456 3458
3457 static int __init spear320_pinctrl_init(void) 3459 static int __init spear320_pinctrl_init(void)
3458 { 3460 {
3459 return platform_driver_register(&spear320_pinctrl_driver); 3461 return platform_driver_register(&spear320_pinctrl_driver);
3460 } 3462 }
3461 arch_initcall(spear320_pinctrl_init); 3463 arch_initcall(spear320_pinctrl_init);
3462 3464
3463 static void __exit spear320_pinctrl_exit(void) 3465 static void __exit spear320_pinctrl_exit(void)
3464 { 3466 {
3465 platform_driver_unregister(&spear320_pinctrl_driver); 3467 platform_driver_unregister(&spear320_pinctrl_driver);
3466 } 3468 }
3467 module_exit(spear320_pinctrl_exit); 3469 module_exit(spear320_pinctrl_exit);
3468 3470
3469 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); 3471 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
3470 MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver"); 3472 MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3471 MODULE_LICENSE("GPL v2"); 3473 MODULE_LICENSE("GPL v2");
3472 MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match); 3474 MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
3473 3475
drivers/pinctrl/spear/pinctrl-spear3xx.c
Diff comments   View file @ f4f8e56
1 /* 1 /*
2 * Driver for the ST Microelectronics SPEAr3xx pinmux 2 * Driver for the ST Microelectronics SPEAr3xx pinmux
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinctrl.h>
13 13
14 #include "pinctrl-spear3xx.h" 14 #include "pinctrl-spear3xx.h"
15 15
16 /* pins */ 16 /* pins */
17 static const struct pinctrl_pin_desc spear3xx_pins[] = { 17 static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 SPEAR_PIN_0_TO_101, 18 SPEAR_PIN_0_TO_101,
19 }; 19 };
20 20
21 /* firda_pins */ 21 /* firda_pins */
22 static const unsigned firda_pins[] = { 0, 1 }; 22 static const unsigned firda_pins[] = { 0, 1 };
23 static struct spear_muxreg firda_muxreg[] = { 23 static struct spear_muxreg firda_muxreg[] = {
24 { 24 {
25 .reg = -1, 25 .reg = -1,
26 .mask = PMX_FIRDA_MASK, 26 .mask = PMX_FIRDA_MASK,
27 .val = PMX_FIRDA_MASK, 27 .val = PMX_FIRDA_MASK,
28 }, 28 },
29 }; 29 };
30 30
31 static struct spear_modemux firda_modemux[] = { 31 static struct spear_modemux firda_modemux[] = {
32 { 32 {
33 .modes = ~0, 33 .modes = ~0,
34 .muxregs = firda_muxreg, 34 .muxregs = firda_muxreg,
35 .nmuxregs = ARRAY_SIZE(firda_muxreg), 35 .nmuxregs = ARRAY_SIZE(firda_muxreg),
36 }, 36 },
37 }; 37 };
38 38
39 struct spear_pingroup spear3xx_firda_pingroup = { 39 struct spear_pingroup spear3xx_firda_pingroup = {
40 .name = "firda_grp", 40 .name = "firda_grp",
41 .pins = firda_pins, 41 .pins = firda_pins,
42 .npins = ARRAY_SIZE(firda_pins), 42 .npins = ARRAY_SIZE(firda_pins),
43 .modemuxs = firda_modemux, 43 .modemuxs = firda_modemux,
44 .nmodemuxs = ARRAY_SIZE(firda_modemux), 44 .nmodemuxs = ARRAY_SIZE(firda_modemux),
45 }; 45 };
46 46
47 static const char *const firda_grps[] = { "firda_grp" }; 47 static const char *const firda_grps[] = { "firda_grp" };
48 struct spear_function spear3xx_firda_function = { 48 struct spear_function spear3xx_firda_function = {
49 .name = "firda", 49 .name = "firda",
50 .groups = firda_grps, 50 .groups = firda_grps,
51 .ngroups = ARRAY_SIZE(firda_grps), 51 .ngroups = ARRAY_SIZE(firda_grps),
52 }; 52 };
53 53
54 /* i2c_pins */ 54 /* i2c_pins */
55 static const unsigned i2c_pins[] = { 4, 5 }; 55 static const unsigned i2c_pins[] = { 4, 5 };
56 static struct spear_muxreg i2c_muxreg[] = { 56 static struct spear_muxreg i2c_muxreg[] = {
57 { 57 {
58 .reg = -1, 58 .reg = -1,
59 .mask = PMX_I2C_MASK, 59 .mask = PMX_I2C_MASK,
60 .val = PMX_I2C_MASK, 60 .val = PMX_I2C_MASK,
61 }, 61 },
62 }; 62 };
63 63
64 static struct spear_modemux i2c_modemux[] = { 64 static struct spear_modemux i2c_modemux[] = {
65 { 65 {
66 .modes = ~0, 66 .modes = ~0,
67 .muxregs = i2c_muxreg, 67 .muxregs = i2c_muxreg,
68 .nmuxregs = ARRAY_SIZE(i2c_muxreg), 68 .nmuxregs = ARRAY_SIZE(i2c_muxreg),
69 }, 69 },
70 }; 70 };
71 71
72 struct spear_pingroup spear3xx_i2c_pingroup = { 72 struct spear_pingroup spear3xx_i2c_pingroup = {
73 .name = "i2c0_grp", 73 .name = "i2c0_grp",
74 .pins = i2c_pins, 74 .pins = i2c_pins,
75 .npins = ARRAY_SIZE(i2c_pins), 75 .npins = ARRAY_SIZE(i2c_pins),
76 .modemuxs = i2c_modemux, 76 .modemuxs = i2c_modemux,
77 .nmodemuxs = ARRAY_SIZE(i2c_modemux), 77 .nmodemuxs = ARRAY_SIZE(i2c_modemux),
78 }; 78 };
79 79
80 static const char *const i2c_grps[] = { "i2c0_grp" }; 80 static const char *const i2c_grps[] = { "i2c0_grp" };
81 struct spear_function spear3xx_i2c_function = { 81 struct spear_function spear3xx_i2c_function = {
82 .name = "i2c0", 82 .name = "i2c0",
83 .groups = i2c_grps, 83 .groups = i2c_grps,
84 .ngroups = ARRAY_SIZE(i2c_grps), 84 .ngroups = ARRAY_SIZE(i2c_grps),
85 }; 85 };
86 86
87 /* ssp_cs_pins */ 87 /* ssp_cs_pins */
88 static const unsigned ssp_cs_pins[] = { 34, 35, 36 }; 88 static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
89 static struct spear_muxreg ssp_cs_muxreg[] = { 89 static struct spear_muxreg ssp_cs_muxreg[] = {
90 { 90 {
91 .reg = -1, 91 .reg = -1,
92 .mask = PMX_SSP_CS_MASK, 92 .mask = PMX_SSP_CS_MASK,
93 .val = PMX_SSP_CS_MASK, 93 .val = PMX_SSP_CS_MASK,
94 }, 94 },
95 }; 95 };
96 96
97 static struct spear_modemux ssp_cs_modemux[] = { 97 static struct spear_modemux ssp_cs_modemux[] = {
98 { 98 {
99 .modes = ~0, 99 .modes = ~0,
100 .muxregs = ssp_cs_muxreg, 100 .muxregs = ssp_cs_muxreg,
101 .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg), 101 .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
102 }, 102 },
103 }; 103 };
104 104
105 struct spear_pingroup spear3xx_ssp_cs_pingroup = { 105 struct spear_pingroup spear3xx_ssp_cs_pingroup = {
106 .name = "ssp_cs_grp", 106 .name = "ssp_cs_grp",
107 .pins = ssp_cs_pins, 107 .pins = ssp_cs_pins,
108 .npins = ARRAY_SIZE(ssp_cs_pins), 108 .npins = ARRAY_SIZE(ssp_cs_pins),
109 .modemuxs = ssp_cs_modemux, 109 .modemuxs = ssp_cs_modemux,
110 .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux), 110 .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
111 }; 111 };
112 112
113 static const char *const ssp_cs_grps[] = { "ssp_cs_grp" }; 113 static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
114 struct spear_function spear3xx_ssp_cs_function = { 114 struct spear_function spear3xx_ssp_cs_function = {
115 .name = "ssp_cs", 115 .name = "ssp_cs",
116 .groups = ssp_cs_grps, 116 .groups = ssp_cs_grps,
117 .ngroups = ARRAY_SIZE(ssp_cs_grps), 117 .ngroups = ARRAY_SIZE(ssp_cs_grps),
118 }; 118 };
119 119
120 /* ssp_pins */ 120 /* ssp_pins */
121 static const unsigned ssp_pins[] = { 6, 7, 8, 9 }; 121 static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
122 static struct spear_muxreg ssp_muxreg[] = { 122 static struct spear_muxreg ssp_muxreg[] = {
123 { 123 {
124 .reg = -1, 124 .reg = -1,
125 .mask = PMX_SSP_MASK, 125 .mask = PMX_SSP_MASK,
126 .val = PMX_SSP_MASK, 126 .val = PMX_SSP_MASK,
127 }, 127 },
128 }; 128 };
129 129
130 static struct spear_modemux ssp_modemux[] = { 130 static struct spear_modemux ssp_modemux[] = {
131 { 131 {
132 .modes = ~0, 132 .modes = ~0,
133 .muxregs = ssp_muxreg, 133 .muxregs = ssp_muxreg,
134 .nmuxregs = ARRAY_SIZE(ssp_muxreg), 134 .nmuxregs = ARRAY_SIZE(ssp_muxreg),
135 }, 135 },
136 }; 136 };
137 137
138 struct spear_pingroup spear3xx_ssp_pingroup = { 138 struct spear_pingroup spear3xx_ssp_pingroup = {
139 .name = "ssp0_grp", 139 .name = "ssp0_grp",
140 .pins = ssp_pins, 140 .pins = ssp_pins,
141 .npins = ARRAY_SIZE(ssp_pins), 141 .npins = ARRAY_SIZE(ssp_pins),
142 .modemuxs = ssp_modemux, 142 .modemuxs = ssp_modemux,
143 .nmodemuxs = ARRAY_SIZE(ssp_modemux), 143 .nmodemuxs = ARRAY_SIZE(ssp_modemux),
144 }; 144 };
145 145
146 static const char *const ssp_grps[] = { "ssp0_grp" }; 146 static const char *const ssp_grps[] = { "ssp0_grp" };
147 struct spear_function spear3xx_ssp_function = { 147 struct spear_function spear3xx_ssp_function = {
148 .name = "ssp0", 148 .name = "ssp0",
149 .groups = ssp_grps, 149 .groups = ssp_grps,
150 .ngroups = ARRAY_SIZE(ssp_grps), 150 .ngroups = ARRAY_SIZE(ssp_grps),
151 }; 151 };
152 152
153 /* mii_pins */ 153 /* mii_pins */
154 static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 154 static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
155 21, 22, 23, 24, 25, 26, 27 }; 155 21, 22, 23, 24, 25, 26, 27 };
156 static struct spear_muxreg mii_muxreg[] = { 156 static struct spear_muxreg mii_muxreg[] = {
157 { 157 {
158 .reg = -1, 158 .reg = -1,
159 .mask = PMX_MII_MASK, 159 .mask = PMX_MII_MASK,
160 .val = PMX_MII_MASK, 160 .val = PMX_MII_MASK,
161 }, 161 },
162 }; 162 };
163 163
164 static struct spear_modemux mii_modemux[] = { 164 static struct spear_modemux mii_modemux[] = {
165 { 165 {
166 .modes = ~0, 166 .modes = ~0,
167 .muxregs = mii_muxreg, 167 .muxregs = mii_muxreg,
168 .nmuxregs = ARRAY_SIZE(mii_muxreg), 168 .nmuxregs = ARRAY_SIZE(mii_muxreg),
169 }, 169 },
170 }; 170 };
171 171
172 struct spear_pingroup spear3xx_mii_pingroup = { 172 struct spear_pingroup spear3xx_mii_pingroup = {
173 .name = "mii0_grp", 173 .name = "mii0_grp",
174 .pins = mii_pins, 174 .pins = mii_pins,
175 .npins = ARRAY_SIZE(mii_pins), 175 .npins = ARRAY_SIZE(mii_pins),
176 .modemuxs = mii_modemux, 176 .modemuxs = mii_modemux,
177 .nmodemuxs = ARRAY_SIZE(mii_modemux), 177 .nmodemuxs = ARRAY_SIZE(mii_modemux),
178 }; 178 };
179 179
180 static const char *const mii_grps[] = { "mii0_grp" }; 180 static const char *const mii_grps[] = { "mii0_grp" };
181 struct spear_function spear3xx_mii_function = { 181 struct spear_function spear3xx_mii_function = {
182 .name = "mii0", 182 .name = "mii0",
183 .groups = mii_grps, 183 .groups = mii_grps,
184 .ngroups = ARRAY_SIZE(mii_grps), 184 .ngroups = ARRAY_SIZE(mii_grps),
185 }; 185 };
186 186
187 /* gpio0_pin0_pins */ 187 /* gpio0_pin0_pins */
188 static const unsigned gpio0_pin0_pins[] = { 28 }; 188 static const unsigned gpio0_pin0_pins[] = { 28 };
189 static struct spear_muxreg gpio0_pin0_muxreg[] = { 189 static struct spear_muxreg gpio0_pin0_muxreg[] = {
190 { 190 {
191 .reg = -1, 191 .reg = -1,
192 .mask = PMX_GPIO_PIN0_MASK, 192 .mask = PMX_GPIO_PIN0_MASK,
193 .val = PMX_GPIO_PIN0_MASK, 193 .val = PMX_GPIO_PIN0_MASK,
194 }, 194 },
195 }; 195 };
196 196
197 static struct spear_modemux gpio0_pin0_modemux[] = { 197 static struct spear_modemux gpio0_pin0_modemux[] = {
198 { 198 {
199 .modes = ~0, 199 .modes = ~0,
200 .muxregs = gpio0_pin0_muxreg, 200 .muxregs = gpio0_pin0_muxreg,
201 .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg), 201 .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
202 }, 202 },
203 }; 203 };
204 204
205 struct spear_pingroup spear3xx_gpio0_pin0_pingroup = { 205 struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
206 .name = "gpio0_pin0_grp", 206 .name = "gpio0_pin0_grp",
207 .pins = gpio0_pin0_pins, 207 .pins = gpio0_pin0_pins,
208 .npins = ARRAY_SIZE(gpio0_pin0_pins), 208 .npins = ARRAY_SIZE(gpio0_pin0_pins),
209 .modemuxs = gpio0_pin0_modemux, 209 .modemuxs = gpio0_pin0_modemux,
210 .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux), 210 .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
211 }; 211 };
212 212
213 /* gpio0_pin1_pins */ 213 /* gpio0_pin1_pins */
214 static const unsigned gpio0_pin1_pins[] = { 29 }; 214 static const unsigned gpio0_pin1_pins[] = { 29 };
215 static struct spear_muxreg gpio0_pin1_muxreg[] = { 215 static struct spear_muxreg gpio0_pin1_muxreg[] = {
216 { 216 {
217 .reg = -1, 217 .reg = -1,
218 .mask = PMX_GPIO_PIN1_MASK, 218 .mask = PMX_GPIO_PIN1_MASK,
219 .val = PMX_GPIO_PIN1_MASK, 219 .val = PMX_GPIO_PIN1_MASK,
220 }, 220 },
221 }; 221 };
222 222
223 static struct spear_modemux gpio0_pin1_modemux[] = { 223 static struct spear_modemux gpio0_pin1_modemux[] = {
224 { 224 {
225 .modes = ~0, 225 .modes = ~0,
226 .muxregs = gpio0_pin1_muxreg, 226 .muxregs = gpio0_pin1_muxreg,
227 .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg), 227 .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
228 }, 228 },
229 }; 229 };
230 230
231 struct spear_pingroup spear3xx_gpio0_pin1_pingroup = { 231 struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
232 .name = "gpio0_pin1_grp", 232 .name = "gpio0_pin1_grp",
233 .pins = gpio0_pin1_pins, 233 .pins = gpio0_pin1_pins,
234 .npins = ARRAY_SIZE(gpio0_pin1_pins), 234 .npins = ARRAY_SIZE(gpio0_pin1_pins),
235 .modemuxs = gpio0_pin1_modemux, 235 .modemuxs = gpio0_pin1_modemux,
236 .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux), 236 .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
237 }; 237 };
238 238
239 /* gpio0_pin2_pins */ 239 /* gpio0_pin2_pins */
240 static const unsigned gpio0_pin2_pins[] = { 30 }; 240 static const unsigned gpio0_pin2_pins[] = { 30 };
241 static struct spear_muxreg gpio0_pin2_muxreg[] = { 241 static struct spear_muxreg gpio0_pin2_muxreg[] = {
242 { 242 {
243 .reg = -1, 243 .reg = -1,
244 .mask = PMX_GPIO_PIN2_MASK, 244 .mask = PMX_GPIO_PIN2_MASK,
245 .val = PMX_GPIO_PIN2_MASK, 245 .val = PMX_GPIO_PIN2_MASK,
246 }, 246 },
247 }; 247 };
248 248
249 static struct spear_modemux gpio0_pin2_modemux[] = { 249 static struct spear_modemux gpio0_pin2_modemux[] = {
250 { 250 {
251 .modes = ~0, 251 .modes = ~0,
252 .muxregs = gpio0_pin2_muxreg, 252 .muxregs = gpio0_pin2_muxreg,
253 .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg), 253 .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
254 }, 254 },
255 }; 255 };
256 256
257 struct spear_pingroup spear3xx_gpio0_pin2_pingroup = { 257 struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
258 .name = "gpio0_pin2_grp", 258 .name = "gpio0_pin2_grp",
259 .pins = gpio0_pin2_pins, 259 .pins = gpio0_pin2_pins,
260 .npins = ARRAY_SIZE(gpio0_pin2_pins), 260 .npins = ARRAY_SIZE(gpio0_pin2_pins),
261 .modemuxs = gpio0_pin2_modemux, 261 .modemuxs = gpio0_pin2_modemux,
262 .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux), 262 .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
263 }; 263 };
264 264
265 /* gpio0_pin3_pins */ 265 /* gpio0_pin3_pins */
266 static const unsigned gpio0_pin3_pins[] = { 31 }; 266 static const unsigned gpio0_pin3_pins[] = { 31 };
267 static struct spear_muxreg gpio0_pin3_muxreg[] = { 267 static struct spear_muxreg gpio0_pin3_muxreg[] = {
268 { 268 {
269 .reg = -1, 269 .reg = -1,
270 .mask = PMX_GPIO_PIN3_MASK, 270 .mask = PMX_GPIO_PIN3_MASK,
271 .val = PMX_GPIO_PIN3_MASK, 271 .val = PMX_GPIO_PIN3_MASK,
272 }, 272 },
273 }; 273 };
274 274
275 static struct spear_modemux gpio0_pin3_modemux[] = { 275 static struct spear_modemux gpio0_pin3_modemux[] = {
276 { 276 {
277 .modes = ~0, 277 .modes = ~0,
278 .muxregs = gpio0_pin3_muxreg, 278 .muxregs = gpio0_pin3_muxreg,
279 .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg), 279 .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
280 }, 280 },
281 }; 281 };
282 282
283 struct spear_pingroup spear3xx_gpio0_pin3_pingroup = { 283 struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
284 .name = "gpio0_pin3_grp", 284 .name = "gpio0_pin3_grp",
285 .pins = gpio0_pin3_pins, 285 .pins = gpio0_pin3_pins,
286 .npins = ARRAY_SIZE(gpio0_pin3_pins), 286 .npins = ARRAY_SIZE(gpio0_pin3_pins),
287 .modemuxs = gpio0_pin3_modemux, 287 .modemuxs = gpio0_pin3_modemux,
288 .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux), 288 .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
289 }; 289 };
290 290
291 /* gpio0_pin4_pins */ 291 /* gpio0_pin4_pins */
292 static const unsigned gpio0_pin4_pins[] = { 32 }; 292 static const unsigned gpio0_pin4_pins[] = { 32 };
293 static struct spear_muxreg gpio0_pin4_muxreg[] = { 293 static struct spear_muxreg gpio0_pin4_muxreg[] = {
294 { 294 {
295 .reg = -1, 295 .reg = -1,
296 .mask = PMX_GPIO_PIN4_MASK, 296 .mask = PMX_GPIO_PIN4_MASK,
297 .val = PMX_GPIO_PIN4_MASK, 297 .val = PMX_GPIO_PIN4_MASK,
298 }, 298 },
299 }; 299 };
300 300
301 static struct spear_modemux gpio0_pin4_modemux[] = { 301 static struct spear_modemux gpio0_pin4_modemux[] = {
302 { 302 {
303 .modes = ~0, 303 .modes = ~0,
304 .muxregs = gpio0_pin4_muxreg, 304 .muxregs = gpio0_pin4_muxreg,
305 .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg), 305 .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
306 }, 306 },
307 }; 307 };
308 308
309 struct spear_pingroup spear3xx_gpio0_pin4_pingroup = { 309 struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
310 .name = "gpio0_pin4_grp", 310 .name = "gpio0_pin4_grp",
311 .pins = gpio0_pin4_pins, 311 .pins = gpio0_pin4_pins,
312 .npins = ARRAY_SIZE(gpio0_pin4_pins), 312 .npins = ARRAY_SIZE(gpio0_pin4_pins),
313 .modemuxs = gpio0_pin4_modemux, 313 .modemuxs = gpio0_pin4_modemux,
314 .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux), 314 .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
315 }; 315 };
316 316
317 /* gpio0_pin5_pins */ 317 /* gpio0_pin5_pins */
318 static const unsigned gpio0_pin5_pins[] = { 33 }; 318 static const unsigned gpio0_pin5_pins[] = { 33 };
319 static struct spear_muxreg gpio0_pin5_muxreg[] = { 319 static struct spear_muxreg gpio0_pin5_muxreg[] = {
320 { 320 {
321 .reg = -1, 321 .reg = -1,
322 .mask = PMX_GPIO_PIN5_MASK, 322 .mask = PMX_GPIO_PIN5_MASK,
323 .val = PMX_GPIO_PIN5_MASK, 323 .val = PMX_GPIO_PIN5_MASK,
324 }, 324 },
325 }; 325 };
326 326
327 static struct spear_modemux gpio0_pin5_modemux[] = { 327 static struct spear_modemux gpio0_pin5_modemux[] = {
328 { 328 {
329 .modes = ~0, 329 .modes = ~0,
330 .muxregs = gpio0_pin5_muxreg, 330 .muxregs = gpio0_pin5_muxreg,
331 .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg), 331 .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
332 }, 332 },
333 }; 333 };
334 334
335 struct spear_pingroup spear3xx_gpio0_pin5_pingroup = { 335 struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
336 .name = "gpio0_pin5_grp", 336 .name = "gpio0_pin5_grp",
337 .pins = gpio0_pin5_pins, 337 .pins = gpio0_pin5_pins,
338 .npins = ARRAY_SIZE(gpio0_pin5_pins), 338 .npins = ARRAY_SIZE(gpio0_pin5_pins),
339 .modemuxs = gpio0_pin5_modemux, 339 .modemuxs = gpio0_pin5_modemux,
340 .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux), 340 .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
341 }; 341 };
342 342
343 static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp", 343 static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
344 "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp", 344 "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
345 }; 345 };
346 struct spear_function spear3xx_gpio0_function = { 346 struct spear_function spear3xx_gpio0_function = {
347 .name = "gpio0", 347 .name = "gpio0",
348 .groups = gpio0_grps, 348 .groups = gpio0_grps,
349 .ngroups = ARRAY_SIZE(gpio0_grps), 349 .ngroups = ARRAY_SIZE(gpio0_grps),
350 }; 350 };
351 351
352 /* uart0_ext_pins */ 352 /* uart0_ext_pins */
353 static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 }; 353 static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
354 static struct spear_muxreg uart0_ext_muxreg[] = { 354 static struct spear_muxreg uart0_ext_muxreg[] = {
355 { 355 {
356 .reg = -1, 356 .reg = -1,
357 .mask = PMX_UART0_MODEM_MASK, 357 .mask = PMX_UART0_MODEM_MASK,
358 .val = PMX_UART0_MODEM_MASK, 358 .val = PMX_UART0_MODEM_MASK,
359 }, 359 },
360 }; 360 };
361 361
362 static struct spear_modemux uart0_ext_modemux[] = { 362 static struct spear_modemux uart0_ext_modemux[] = {
363 { 363 {
364 .modes = ~0, 364 .modes = ~0,
365 .muxregs = uart0_ext_muxreg, 365 .muxregs = uart0_ext_muxreg,
366 .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg), 366 .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
367 }, 367 },
368 }; 368 };
369 369
370 struct spear_pingroup spear3xx_uart0_ext_pingroup = { 370 struct spear_pingroup spear3xx_uart0_ext_pingroup = {
371 .name = "uart0_ext_grp", 371 .name = "uart0_ext_grp",
372 .pins = uart0_ext_pins, 372 .pins = uart0_ext_pins,
373 .npins = ARRAY_SIZE(uart0_ext_pins), 373 .npins = ARRAY_SIZE(uart0_ext_pins),
374 .modemuxs = uart0_ext_modemux, 374 .modemuxs = uart0_ext_modemux,
375 .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux), 375 .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
376 }; 376 };
377 377
378 static const char *const uart0_ext_grps[] = { "uart0_ext_grp" }; 378 static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
379 struct spear_function spear3xx_uart0_ext_function = { 379 struct spear_function spear3xx_uart0_ext_function = {
380 .name = "uart0_ext", 380 .name = "uart0_ext",
381 .groups = uart0_ext_grps, 381 .groups = uart0_ext_grps,
382 .ngroups = ARRAY_SIZE(uart0_ext_grps), 382 .ngroups = ARRAY_SIZE(uart0_ext_grps),
383 }; 383 };
384 384
385 /* uart0_pins */ 385 /* uart0_pins */
386 static const unsigned uart0_pins[] = { 2, 3 }; 386 static const unsigned uart0_pins[] = { 2, 3 };
387 static struct spear_muxreg uart0_muxreg[] = { 387 static struct spear_muxreg uart0_muxreg[] = {
388 { 388 {
389 .reg = -1, 389 .reg = -1,
390 .mask = PMX_UART0_MASK, 390 .mask = PMX_UART0_MASK,
391 .val = PMX_UART0_MASK, 391 .val = PMX_UART0_MASK,
392 }, 392 },
393 }; 393 };
394 394
395 static struct spear_modemux uart0_modemux[] = { 395 static struct spear_modemux uart0_modemux[] = {
396 { 396 {
397 .modes = ~0, 397 .modes = ~0,
398 .muxregs = uart0_muxreg, 398 .muxregs = uart0_muxreg,
399 .nmuxregs = ARRAY_SIZE(uart0_muxreg), 399 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
400 }, 400 },
401 }; 401 };
402 402
403 struct spear_pingroup spear3xx_uart0_pingroup = { 403 struct spear_pingroup spear3xx_uart0_pingroup = {
404 .name = "uart0_grp", 404 .name = "uart0_grp",
405 .pins = uart0_pins, 405 .pins = uart0_pins,
406 .npins = ARRAY_SIZE(uart0_pins), 406 .npins = ARRAY_SIZE(uart0_pins),
407 .modemuxs = uart0_modemux, 407 .modemuxs = uart0_modemux,
408 .nmodemuxs = ARRAY_SIZE(uart0_modemux), 408 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
409 }; 409 };
410 410
411 static const char *const uart0_grps[] = { "uart0_grp" }; 411 static const char *const uart0_grps[] = { "uart0_grp" };
412 struct spear_function spear3xx_uart0_function = { 412 struct spear_function spear3xx_uart0_function = {
413 .name = "uart0", 413 .name = "uart0",
414 .groups = uart0_grps, 414 .groups = uart0_grps,
415 .ngroups = ARRAY_SIZE(uart0_grps), 415 .ngroups = ARRAY_SIZE(uart0_grps),
416 }; 416 };
417 417
418 /* timer_0_1_pins */ 418 /* timer_0_1_pins */
419 static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 }; 419 static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
420 static struct spear_muxreg timer_0_1_muxreg[] = { 420 static struct spear_muxreg timer_0_1_muxreg[] = {
421 { 421 {
422 .reg = -1, 422 .reg = -1,
423 .mask = PMX_TIMER_0_1_MASK, 423 .mask = PMX_TIMER_0_1_MASK,
424 .val = PMX_TIMER_0_1_MASK, 424 .val = PMX_TIMER_0_1_MASK,
425 }, 425 },
426 }; 426 };
427 427
428 static struct spear_modemux timer_0_1_modemux[] = { 428 static struct spear_modemux timer_0_1_modemux[] = {
429 { 429 {
430 .modes = ~0, 430 .modes = ~0,
431 .muxregs = timer_0_1_muxreg, 431 .muxregs = timer_0_1_muxreg,
432 .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg), 432 .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
433 }, 433 },
434 }; 434 };
435 435
436 struct spear_pingroup spear3xx_timer_0_1_pingroup = { 436 struct spear_pingroup spear3xx_timer_0_1_pingroup = {
437 .name = "timer_0_1_grp", 437 .name = "timer_0_1_grp",
438 .pins = timer_0_1_pins, 438 .pins = timer_0_1_pins,
439 .npins = ARRAY_SIZE(timer_0_1_pins), 439 .npins = ARRAY_SIZE(timer_0_1_pins),
440 .modemuxs = timer_0_1_modemux, 440 .modemuxs = timer_0_1_modemux,
441 .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux), 441 .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
442 }; 442 };
443 443
444 static const char *const timer_0_1_grps[] = { "timer_0_1_grp" }; 444 static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
445 struct spear_function spear3xx_timer_0_1_function = { 445 struct spear_function spear3xx_timer_0_1_function = {
446 .name = "timer_0_1", 446 .name = "timer_0_1",
447 .groups = timer_0_1_grps, 447 .groups = timer_0_1_grps,
448 .ngroups = ARRAY_SIZE(timer_0_1_grps), 448 .ngroups = ARRAY_SIZE(timer_0_1_grps),
449 }; 449 };
450 450
451 /* timer_2_3_pins */ 451 /* timer_2_3_pins */
452 static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 }; 452 static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
453 static struct spear_muxreg timer_2_3_muxreg[] = { 453 static struct spear_muxreg timer_2_3_muxreg[] = {
454 { 454 {
455 .reg = -1, 455 .reg = -1,
456 .mask = PMX_TIMER_2_3_MASK, 456 .mask = PMX_TIMER_2_3_MASK,
457 .val = PMX_TIMER_2_3_MASK, 457 .val = PMX_TIMER_2_3_MASK,
458 }, 458 },
459 }; 459 };
460 460
461 static struct spear_modemux timer_2_3_modemux[] = { 461 static struct spear_modemux timer_2_3_modemux[] = {
462 { 462 {
463 .modes = ~0, 463 .modes = ~0,
464 .muxregs = timer_2_3_muxreg, 464 .muxregs = timer_2_3_muxreg,
465 .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg), 465 .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
466 }, 466 },
467 }; 467 };
468 468
469 struct spear_pingroup spear3xx_timer_2_3_pingroup = { 469 struct spear_pingroup spear3xx_timer_2_3_pingroup = {
470 .name = "timer_2_3_grp", 470 .name = "timer_2_3_grp",
471 .pins = timer_2_3_pins, 471 .pins = timer_2_3_pins,
472 .npins = ARRAY_SIZE(timer_2_3_pins), 472 .npins = ARRAY_SIZE(timer_2_3_pins),
473 .modemuxs = timer_2_3_modemux, 473 .modemuxs = timer_2_3_modemux,
474 .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux), 474 .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
475 }; 475 };
476 476
477 static const char *const timer_2_3_grps[] = { "timer_2_3_grp" }; 477 static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
478 struct spear_function spear3xx_timer_2_3_function = { 478 struct spear_function spear3xx_timer_2_3_function = {
479 .name = "timer_2_3", 479 .name = "timer_2_3",
480 .groups = timer_2_3_grps, 480 .groups = timer_2_3_grps,
481 .ngroups = ARRAY_SIZE(timer_2_3_grps), 481 .ngroups = ARRAY_SIZE(timer_2_3_grps),
482 }; 482 };
483 483
484 /* Define muxreg arrays */
485 DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
486 DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
487 DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
488 DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
489 DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
490 DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
491 DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
492 DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
493 DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
494 DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
495 DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
496 DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
497 DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
498 DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
499 DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
500
501 static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
502 GPIO_PINGROUP(firda_pins),
503 GPIO_PINGROUP(i2c_pins),
504 GPIO_PINGROUP(ssp_cs_pins),
505 GPIO_PINGROUP(ssp_pins),
506 GPIO_PINGROUP(mii_pins),
507 GPIO_PINGROUP(gpio0_pin0_pins),
508 GPIO_PINGROUP(gpio0_pin1_pins),
509 GPIO_PINGROUP(gpio0_pin2_pins),
510 GPIO_PINGROUP(gpio0_pin3_pins),
511 GPIO_PINGROUP(gpio0_pin4_pins),
512 GPIO_PINGROUP(gpio0_pin5_pins),
513 GPIO_PINGROUP(uart0_ext_pins),
514 GPIO_PINGROUP(uart0_pins),
515 GPIO_PINGROUP(timer_0_1_pins),
516 GPIO_PINGROUP(timer_2_3_pins),
517 };
518
484 struct spear_pinctrl_machdata spear3xx_machdata = { 519 struct spear_pinctrl_machdata spear3xx_machdata = {
485 .pins = spear3xx_pins, 520 .pins = spear3xx_pins,
486 .npins = ARRAY_SIZE(spear3xx_pins), 521 .npins = ARRAY_SIZE(spear3xx_pins),
522 .gpio_pingroups = spear3xx_gpio_pingroup,
523 .ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
487 }; 524 };
488 525