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Commit f4f8e5635f398645d614dff5a07598651faf3ead

Authored by Viresh Kumar
Committed by Linus Walleij
1 parent 50309a9c2e
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

pinctrl: SPEAr: Add gpio ranges support 

Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio.
This patch gpio enable support for SPEAr pinctrl drivers.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 8 changed files with 447 additions and 17 deletions Side-by-side Diff

drivers/pinctrl/spear/Kconfig
Diff comments   View file @ f4f8e56
... ... @@ -25,21 +25,25 @@
25 25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
26 26 depends on MACH_SPEAR310
27 27 select PINCTRL_SPEAR3XX
  28 + select PINCTRL_SPEAR_PLGPIO
28 29  
29 30 config PINCTRL_SPEAR320
30 31 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
31 32 depends on MACH_SPEAR320
32 33 select PINCTRL_SPEAR3XX
  34 + select PINCTRL_SPEAR_PLGPIO
33 35  
34 36 config PINCTRL_SPEAR1310
35 37 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
36 38 depends on MACH_SPEAR1310
37 39 select PINCTRL_SPEAR
  40 + select PINCTRL_SPEAR_PLGPIO
38 41  
39 42 config PINCTRL_SPEAR1340
40 43 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
41 44 depends on MACH_SPEAR1340
42 45 select PINCTRL_SPEAR
  46 + select PINCTRL_SPEAR_PLGPIO
43 47  
44 48 config PINCTRL_SPEAR_PLGPIO
45 49 bool "SPEAr SoC PLGPIO Controller"
drivers/pinctrl/spear/pinctrl-spear.c
Diff comments   View file @ f4f8e56
... ... @@ -18,6 +18,7 @@
18 18 #include <linux/module.h>
19 19 #include <linux/of.h>
20 20 #include <linux/of_address.h>
  21 +#include <linux/of_gpio.h>
21 22 #include <linux/pinctrl/machine.h>
22 23 #include <linux/pinctrl/pinctrl.h>
23 24 #include <linux/pinctrl/pinmux.h>
... ... @@ -38,6 +39,28 @@
38 39 writel_relaxed(val, pmx->vbase + reg);
39 40 }
40 41  
  42 +static void muxregs_endisable(struct spear_pmx *pmx,
  43 + struct spear_muxreg *muxregs, u8 count, bool enable)
  44 +{
  45 + struct spear_muxreg *muxreg;
  46 + u32 val, temp, j;
  47 +
  48 + for (j = 0; j < count; j++) {
  49 + muxreg = &muxregs[j];
  50 +
  51 + val = pmx_readl(pmx, muxreg->reg);
  52 + val &= ~muxreg->mask;
  53 +
  54 + if (enable)
  55 + temp = muxreg->val;
  56 + else
  57 + temp = ~muxreg->val;
  58 +
  59 + val |= muxreg->mask & temp;
  60 + pmx_writel(pmx, val, muxreg->reg);
  61 + }
  62 +}
  63 +
41 64 static int set_mode(struct spear_pmx *pmx, int mode)
42 65 {
43 66 struct spear_pmx_mode *pmx_mode = NULL;
... ... @@ -70,6 +93,17 @@
70 93 return 0;
71 94 }
72 95  
  96 +void __devinit
  97 +pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
  98 + unsigned count, u16 reg)
  99 +{
  100 + int i = 0, j = 0;
  101 +
  102 + for (; i < count; i++)
  103 + for (; j < gpio_pingroup[i].nmuxregs; j++)
  104 + gpio_pingroup[i].muxregs[j].reg = reg;
  105 +}
  106 +
73 107 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
74 108 {
75 109 struct spear_pingroup *pgroup;
... ... @@ -216,9 +250,7 @@
216 250 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
217 251 const struct spear_pingroup *pgroup;
218 252 const struct spear_modemux *modemux;
219   - struct spear_muxreg *muxreg;
220   - u32 val, temp;
221   - int i, j;
  253 + int i;
222 254 bool found = false;
223 255  
224 256 pgroup = pmx->machdata->groups[group];
... ... @@ -233,20 +265,8 @@
233 265 }
234 266  
235 267 found = true;
236   - for (j = 0; j < modemux->nmuxregs; j++) {
237   - muxreg = &modemux->muxregs[j];
238   -
239   - val = pmx_readl(pmx, muxreg->reg);
240   - val &= ~muxreg->mask;
241   -
242   - if (enable)
243   - temp = muxreg->val;
244   - else
245   - temp = ~muxreg->val;
246   -
247   - val |= muxreg->mask & temp;
248   - pmx_writel(pmx, val, muxreg->reg);
249   - }
  268 + muxregs_endisable(pmx, modemux->muxregs, modemux->nmuxregs,
  269 + enable);
250 270 }
251 271  
252 272 if (!found) {
253 273  
... ... @@ -270,12 +290,65 @@
270 290 spear_pinctrl_endisable(pctldev, function, group, false);
271 291 }
272 292  
  293 +/* gpio with pinmux */
  294 +static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
  295 + unsigned pin)
  296 +{
  297 + struct spear_gpio_pingroup *gpio_pingroup;
  298 + int i = 0, j;
  299 +
  300 + if (!pmx->machdata->gpio_pingroups)
  301 + return NULL;
  302 +
  303 + for (; i < pmx->machdata->ngpio_pingroups; i++) {
  304 + gpio_pingroup = &pmx->machdata->gpio_pingroups[i];
  305 +
  306 + for (j = 0; j < gpio_pingroup->npins; j++) {
  307 + if (gpio_pingroup->pins[j] == pin)
  308 + return gpio_pingroup;
  309 + }
  310 + }
  311 +
  312 + return ERR_PTR(-EINVAL);
  313 +}
  314 +
  315 +static int gpio_request_endisable(struct pinctrl_dev *pctldev,
  316 + struct pinctrl_gpio_range *range, unsigned offset, bool enable)
  317 +{
  318 + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  319 + struct spear_gpio_pingroup *gpio_pingroup;
  320 +
  321 + gpio_pingroup = get_gpio_pingroup(pmx, offset);
  322 + if (IS_ERR(gpio_pingroup))
  323 + return PTR_ERR(gpio_pingroup);
  324 +
  325 + if (gpio_pingroup)
  326 + muxregs_endisable(pmx, gpio_pingroup->muxregs,
  327 + gpio_pingroup->nmuxregs, enable);
  328 +
  329 + return 0;
  330 +}
  331 +
  332 +static int gpio_request_enable(struct pinctrl_dev *pctldev,
  333 + struct pinctrl_gpio_range *range, unsigned offset)
  334 +{
  335 + return gpio_request_endisable(pctldev, range, offset, true);
  336 +}
  337 +
  338 +static void gpio_disable_free(struct pinctrl_dev *pctldev,
  339 + struct pinctrl_gpio_range *range, unsigned offset)
  340 +{
  341 + gpio_request_endisable(pctldev, range, offset, false);
  342 +}
  343 +
273 344 static struct pinmux_ops spear_pinmux_ops = {
274 345 .get_functions_count = spear_pinctrl_get_funcs_count,
275 346 .get_function_name = spear_pinctrl_get_func_name,
276 347 .get_function_groups = spear_pinctrl_get_func_groups,
277 348 .enable = spear_pinctrl_enable,
278 349 .disable = spear_pinctrl_disable,
  350 + .gpio_request_enable = gpio_request_enable,
  351 + .gpio_disable_free = gpio_disable_free,
279 352 };
280 353  
281 354 static struct pinctrl_desc spear_pinctrl_desc = {
drivers/pinctrl/spear/pinctrl-spear.h
Diff comments   View file @ f4f8e56
... ... @@ -12,6 +12,7 @@
12 12 #ifndef __PINMUX_SPEAR_H__
13 13 #define __PINMUX_SPEAR_H__
14 14  
  15 +#include <linux/gpio.h>
15 16 #include <linux/pinctrl/pinctrl.h>
16 17 #include <linux/types.h>
17 18  
... ... @@ -46,6 +47,44 @@
46 47 u32 val;
47 48 };
48 49  
  50 +struct spear_gpio_pingroup {
  51 + const unsigned *pins;
  52 + unsigned npins;
  53 + struct spear_muxreg *muxregs;
  54 + u8 nmuxregs;
  55 +};
  56 +
  57 +/* ste: set to enable */
  58 +#define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \
  59 +static struct spear_muxreg __pins##_muxregs[] = { \
  60 + { \
  61 + .reg = __muxreg, \
  62 + .mask = __mask, \
  63 + .val = __ste ? __mask : 0, \
  64 + }, \
  65 +}
  66 +
  67 +#define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
  68 +static struct spear_muxreg __pins##_muxregs[] = { \
  69 + { \
  70 + .reg = __muxreg1, \
  71 + .mask = __mask, \
  72 + .val = __ste1 ? __mask : 0, \
  73 + }, { \
  74 + .reg = __muxreg2, \
  75 + .mask = __mask, \
  76 + .val = __ste2 ? __mask : 0, \
  77 + }, \
  78 +}
  79 +
  80 +#define GPIO_PINGROUP(__pins) \
  81 + { \
  82 + .pins = __pins, \
  83 + .npins = ARRAY_SIZE(__pins), \
  84 + .muxregs = __pins##_muxregs, \
  85 + .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \
  86 + }
  87 +
49 88 /**
50 89 * struct spear_modemux - SPEAr mode mux configuration
51 90 * @modes: mode ids supported by this group of muxregs
... ... @@ -100,6 +139,8 @@
100 139 * @nfunctions: The numbmer of entries in @functions.
101 140 * @groups: An array describing all pin groups the pin SoC supports.
102 141 * @ngroups: The numbmer of entries in @groups.
  142 + * @gpio_pingroups: gpio pingroups
  143 + * @ngpio_pingroups: gpio pingroups count
103 144 *
104 145 * @modes_supported: Does SoC support modes
105 146 * @mode: mode configured from probe
... ... @@ -113,6 +154,8 @@
113 154 unsigned nfunctions;
114 155 struct spear_pingroup **groups;
115 156 unsigned ngroups;
  157 + struct spear_gpio_pingroup *gpio_pingroups;
  158 + unsigned ngpio_pingroups;
116 159  
117 160 bool modes_supported;
118 161 u16 mode;
... ... @@ -136,6 +179,9 @@
136 179  
137 180 /* exported routines */
138 181 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
  182 +void __devinit
  183 +pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
  184 + unsigned count, u16 reg);
139 185 int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 186 struct spear_pinctrl_machdata *machdata);
141 187 int __devexit spear_pinctrl_remove(struct platform_device *pdev);
drivers/pinctrl/spear/pinctrl-spear1310.c
Diff comments   View file @ f4f8e56
... ... @@ -2418,6 +2418,268 @@
2418 2418 &gpt64_function,
2419 2419 };
2420 2420  
  2421 +static const unsigned pin18[] = { 18, };
  2422 +static const unsigned pin19[] = { 19, };
  2423 +static const unsigned pin20[] = { 20, };
  2424 +static const unsigned pin21[] = { 21, };
  2425 +static const unsigned pin22[] = { 22, };
  2426 +static const unsigned pin23[] = { 23, };
  2427 +static const unsigned pin54[] = { 54, };
  2428 +static const unsigned pin55[] = { 55, };
  2429 +static const unsigned pin56[] = { 56, };
  2430 +static const unsigned pin57[] = { 57, };
  2431 +static const unsigned pin58[] = { 58, };
  2432 +static const unsigned pin59[] = { 59, };
  2433 +static const unsigned pin60[] = { 60, };
  2434 +static const unsigned pin61[] = { 61, };
  2435 +static const unsigned pin62[] = { 62, };
  2436 +static const unsigned pin63[] = { 63, };
  2437 +static const unsigned pin143[] = { 143, };
  2438 +static const unsigned pin144[] = { 144, };
  2439 +static const unsigned pin145[] = { 145, };
  2440 +static const unsigned pin146[] = { 146, };
  2441 +static const unsigned pin147[] = { 147, };
  2442 +static const unsigned pin148[] = { 148, };
  2443 +static const unsigned pin149[] = { 149, };
  2444 +static const unsigned pin150[] = { 150, };
  2445 +static const unsigned pin151[] = { 151, };
  2446 +static const unsigned pin152[] = { 152, };
  2447 +static const unsigned pin205[] = { 205, };
  2448 +static const unsigned pin206[] = { 206, };
  2449 +static const unsigned pin211[] = { 211, };
  2450 +static const unsigned pin212[] = { 212, };
  2451 +static const unsigned pin213[] = { 213, };
  2452 +static const unsigned pin214[] = { 214, };
  2453 +static const unsigned pin215[] = { 215, };
  2454 +static const unsigned pin216[] = { 216, };
  2455 +static const unsigned pin217[] = { 217, };
  2456 +static const unsigned pin218[] = { 218, };
  2457 +static const unsigned pin219[] = { 219, };
  2458 +static const unsigned pin220[] = { 220, };
  2459 +static const unsigned pin221[] = { 221, };
  2460 +static const unsigned pin222[] = { 222, };
  2461 +static const unsigned pin223[] = { 223, };
  2462 +static const unsigned pin224[] = { 224, };
  2463 +static const unsigned pin225[] = { 225, };
  2464 +static const unsigned pin226[] = { 226, };
  2465 +static const unsigned pin227[] = { 227, };
  2466 +static const unsigned pin228[] = { 228, };
  2467 +static const unsigned pin229[] = { 229, };
  2468 +static const unsigned pin230[] = { 230, };
  2469 +static const unsigned pin231[] = { 231, };
  2470 +static const unsigned pin232[] = { 232, };
  2471 +static const unsigned pin233[] = { 233, };
  2472 +static const unsigned pin234[] = { 234, };
  2473 +static const unsigned pin235[] = { 235, };
  2474 +static const unsigned pin236[] = { 236, };
  2475 +static const unsigned pin237[] = { 237, };
  2476 +static const unsigned pin238[] = { 238, };
  2477 +static const unsigned pin239[] = { 239, };
  2478 +static const unsigned pin240[] = { 240, };
  2479 +static const unsigned pin241[] = { 241, };
  2480 +static const unsigned pin242[] = { 242, };
  2481 +static const unsigned pin243[] = { 243, };
  2482 +static const unsigned pin244[] = { 244, };
  2483 +static const unsigned pin245[] = { 245, };
  2484 +
  2485 +static const unsigned pin_grp0[] = { 173, 174, };
  2486 +static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };
  2487 +static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,
  2488 + 190, 191, 192, };
  2489 +static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };
  2490 +static const unsigned pin_grp4[] = { 199, 200, };
  2491 +static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
  2492 + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
  2493 +static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };
  2494 +static const unsigned pin_grp7[] = { 98, 99, };
  2495 +static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,
  2496 + 166, 167, 168, 169, 170, 171, 172, };
  2497 +
  2498 +/* Define muxreg arrays */
  2499 +DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);
  2500 +DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);
  2501 +DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);
  2502 +DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);
  2503 +DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);
  2504 +DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);
  2505 +DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);
  2506 +DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);
  2507 +DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);
  2508 +DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);
  2509 +DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);
  2510 +DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);
  2511 +DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);
  2512 +DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);
  2513 +DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);
  2514 +DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);
  2515 +DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);
  2516 +DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);
  2517 +DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);
  2518 +DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);
  2519 +DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);
  2520 +DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);
  2521 +DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);
  2522 +DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);
  2523 +DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);
  2524 +DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);
  2525 +DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);
  2526 +DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);
  2527 +DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);
  2528 +DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);
  2529 +DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);
  2530 +DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);
  2531 +DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);
  2532 +DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);
  2533 +DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);
  2534 +DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);
  2535 +DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);
  2536 +DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);
  2537 +DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);
  2538 +DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);
  2539 +DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);
  2540 +DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);
  2541 +DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);
  2542 +DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);
  2543 +DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);
  2544 +DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);
  2545 +DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);
  2546 +DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);
  2547 +DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);
  2548 +DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);
  2549 +DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);
  2550 +DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);
  2551 +DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);
  2552 +DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);
  2553 +DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);
  2554 +DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);
  2555 +DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);
  2556 +DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);
  2557 +DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);
  2558 +DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);
  2559 +DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);
  2560 +DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);
  2561 +DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);
  2562 +DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);
  2563 +DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);
  2564 +DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);
  2565 +DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);
  2566 +DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);
  2567 +DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);
  2568 +DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);
  2569 +DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);
  2570 +DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);
  2571 +DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);
  2572 +DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);
  2573 +DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);
  2574 +DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);
  2575 +DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);
  2576 +DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);
  2577 +DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);
  2578 +DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);
  2579 +DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);
  2580 +DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);
  2581 +DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);
  2582 +DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);
  2583 +DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);
  2584 +DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);
  2585 +DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);
  2586 +DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);
  2587 +DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);
  2588 +DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);
  2589 +
  2590 +static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {
  2591 + GPIO_PINGROUP(i2c0_pins),
  2592 + GPIO_PINGROUP(ssp0_pins),
  2593 + GPIO_PINGROUP(ssp0_cs0_pins),
  2594 + GPIO_PINGROUP(ssp0_cs1_2_pins),
  2595 + GPIO_PINGROUP(i2s0_pins),
  2596 + GPIO_PINGROUP(i2s1_pins),
  2597 + GPIO_PINGROUP(clcd_pins),
  2598 + GPIO_PINGROUP(clcd_high_res_pins),
  2599 + GPIO_PINGROUP(pin18),
  2600 + GPIO_PINGROUP(pin19),
  2601 + GPIO_PINGROUP(pin20),
  2602 + GPIO_PINGROUP(pin21),
  2603 + GPIO_PINGROUP(pin22),
  2604 + GPIO_PINGROUP(pin23),
  2605 + GPIO_PINGROUP(pin143),
  2606 + GPIO_PINGROUP(pin144),
  2607 + GPIO_PINGROUP(pin145),
  2608 + GPIO_PINGROUP(pin146),
  2609 + GPIO_PINGROUP(pin147),
  2610 + GPIO_PINGROUP(pin148),
  2611 + GPIO_PINGROUP(pin149),
  2612 + GPIO_PINGROUP(pin150),
  2613 + GPIO_PINGROUP(pin151),
  2614 + GPIO_PINGROUP(pin152),
  2615 + GPIO_PINGROUP(smi_2_chips_pins),
  2616 + GPIO_PINGROUP(pin54),
  2617 + GPIO_PINGROUP(pin55),
  2618 + GPIO_PINGROUP(pin56),
  2619 + GPIO_PINGROUP(pin57),
  2620 + GPIO_PINGROUP(pin58),
  2621 + GPIO_PINGROUP(pin59),
  2622 + GPIO_PINGROUP(pin60),
  2623 + GPIO_PINGROUP(pin61),
  2624 + GPIO_PINGROUP(pin62),
  2625 + GPIO_PINGROUP(pin63),
  2626 + GPIO_PINGROUP(pin_grp0),
  2627 + GPIO_PINGROUP(pin_grp1),
  2628 + GPIO_PINGROUP(pin_grp2),
  2629 + GPIO_PINGROUP(pin_grp3),
  2630 + GPIO_PINGROUP(pin_grp4),
  2631 + GPIO_PINGROUP(pin_grp5),
  2632 + GPIO_PINGROUP(pin_grp6),
  2633 + GPIO_PINGROUP(pin_grp7),
  2634 + GPIO_PINGROUP(pin_grp8),
  2635 + GPIO_PINGROUP(nand_16bit_pins),
  2636 + GPIO_PINGROUP(pin205),
  2637 + GPIO_PINGROUP(pin206),
  2638 + GPIO_PINGROUP(pin211),
  2639 + GPIO_PINGROUP(pin212),
  2640 + GPIO_PINGROUP(pin213),
  2641 + GPIO_PINGROUP(pin214),
  2642 + GPIO_PINGROUP(pin215),
  2643 + GPIO_PINGROUP(pin216),
  2644 + GPIO_PINGROUP(pin217),
  2645 + GPIO_PINGROUP(pin218),
  2646 + GPIO_PINGROUP(pin219),
  2647 + GPIO_PINGROUP(pin220),
  2648 + GPIO_PINGROUP(pin221),
  2649 + GPIO_PINGROUP(pin222),
  2650 + GPIO_PINGROUP(pin223),
  2651 + GPIO_PINGROUP(pin224),
  2652 + GPIO_PINGROUP(pin225),
  2653 + GPIO_PINGROUP(pin226),
  2654 + GPIO_PINGROUP(pin227),
  2655 + GPIO_PINGROUP(pin228),
  2656 + GPIO_PINGROUP(pin229),
  2657 + GPIO_PINGROUP(pin230),
  2658 + GPIO_PINGROUP(pin231),
  2659 + GPIO_PINGROUP(pin232),
  2660 + GPIO_PINGROUP(pin233),
  2661 + GPIO_PINGROUP(pin234),
  2662 + GPIO_PINGROUP(pin235),
  2663 + GPIO_PINGROUP(pin236),
  2664 + GPIO_PINGROUP(pin237),
  2665 + GPIO_PINGROUP(pin238),
  2666 + GPIO_PINGROUP(pin239),
  2667 + GPIO_PINGROUP(pin240),
  2668 + GPIO_PINGROUP(pin241),
  2669 + GPIO_PINGROUP(pin242),
  2670 + GPIO_PINGROUP(pin243),
  2671 + GPIO_PINGROUP(pin244),
  2672 + GPIO_PINGROUP(pin245),
  2673 + GPIO_PINGROUP(keyboard_rowcol6_8_pins),
  2674 + GPIO_PINGROUP(uart0_pins),
  2675 + GPIO_PINGROUP(uart0_modem_pins),
  2676 + GPIO_PINGROUP(gpt0_tmr0_pins),
  2677 + GPIO_PINGROUP(gpt0_tmr1_pins),
  2678 + GPIO_PINGROUP(gpt1_tmr0_pins),
  2679 + GPIO_PINGROUP(gpt1_tmr1_pins),
  2680 + GPIO_PINGROUP(touch_xy_pins),
  2681 +};
  2682 +
2421 2683 static struct spear_pinctrl_machdata spear1310_machdata = {
2422 2684 .pins = spear1310_pins,
2423 2685 .npins = ARRAY_SIZE(spear1310_pins),
... ... @@ -2425,6 +2687,8 @@
2425 2687 .ngroups = ARRAY_SIZE(spear1310_pingroups),
2426 2688 .functions = spear1310_functions,
2427 2689 .nfunctions = ARRAY_SIZE(spear1310_functions),
  2690 + .gpio_pingroups = spear1310_gpio_pingroup,
  2691 + .ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),
2428 2692 .modes_supported = false,
2429 2693 };
2430 2694  
drivers/pinctrl/spear/pinctrl-spear300.c
Diff comments   View file @ f4f8e56
... ... @@ -661,6 +661,8 @@
661 661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662 662 spear3xx_machdata.functions = spear300_functions;
663 663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
  664 + spear3xx_machdata.gpio_pingroups = NULL;
  665 + spear3xx_machdata.ngpio_pingroups = 0;
664 666  
665 667 spear3xx_machdata.modes_supported = true;
666 668 spear3xx_machdata.pmx_modes = spear300_pmx_modes;
drivers/pinctrl/spear/pinctrl-spear310.c
Diff comments   View file @ f4f8e56
... ... @@ -388,6 +388,8 @@
388 388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389 389  
390 390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
  391 + pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
  392 + spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
391 393  
392 394 spear3xx_machdata.modes_supported = false;
393 395  
drivers/pinctrl/spear/pinctrl-spear320.c
Diff comments   View file @ f4f8e56
... ... @@ -3431,6 +3431,8 @@
3431 3431 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3432 3432  
3433 3433 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
  3434 + pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
  3435 + spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
3434 3436  
3435 3437 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3436 3438 if (ret)
drivers/pinctrl/spear/pinctrl-spear3xx.c
Diff comments   View file @ f4f8e56
... ... @@ -481,8 +481,45 @@
481 481 .ngroups = ARRAY_SIZE(timer_2_3_grps),
482 482 };
483 483  
  484 +/* Define muxreg arrays */
  485 +DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
  486 +DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
  487 +DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
  488 +DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
  489 +DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
  490 +DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
  491 +DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
  492 +DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
  493 +DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
  494 +DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
  495 +DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
  496 +DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
  497 +DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
  498 +DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
  499 +DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
  500 +
  501 +static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
  502 + GPIO_PINGROUP(firda_pins),
  503 + GPIO_PINGROUP(i2c_pins),
  504 + GPIO_PINGROUP(ssp_cs_pins),
  505 + GPIO_PINGROUP(ssp_pins),
  506 + GPIO_PINGROUP(mii_pins),
  507 + GPIO_PINGROUP(gpio0_pin0_pins),
  508 + GPIO_PINGROUP(gpio0_pin1_pins),
  509 + GPIO_PINGROUP(gpio0_pin2_pins),
  510 + GPIO_PINGROUP(gpio0_pin3_pins),
  511 + GPIO_PINGROUP(gpio0_pin4_pins),
  512 + GPIO_PINGROUP(gpio0_pin5_pins),
  513 + GPIO_PINGROUP(uart0_ext_pins),
  514 + GPIO_PINGROUP(uart0_pins),
  515 + GPIO_PINGROUP(timer_0_1_pins),
  516 + GPIO_PINGROUP(timer_2_3_pins),
  517 +};
  518 +
484 519 struct spear_pinctrl_machdata spear3xx_machdata = {
485 520 .pins = spear3xx_pins,
486 521 .npins = ARRAY_SIZE(spear3xx_pins),
  522 + .gpio_pingroups = spear3xx_gpio_pingroup,
  523 + .ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
487 524 };