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Commit f5b7efccdb057a2cc8ee32c83d2f034e494a1f4a

Authored by Dong Aisheng
Committed by Shawn Guo
1 parent 6c4d4efb9d
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

dma: mxs-dma: use global stmp_device functionality 

This can get rid of the mach-dependency.

Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Huang Shijie <b32955@freescale.com>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Vinod Koul <vinod.koul@intel.com>

Showing 2 changed files with 14 additions and 13 deletions Side-by-side Diff

... ... @@ -238,6 +238,7 @@
238 238 config MXS_DMA
239 239 bool "MXS DMA support"
240 240 depends on SOC_IMX23 || SOC_IMX28
  241 + select STMP_DEVICE
241 242 select DMA_ENGINE
242 243 help
243 244 Support the MXS DMA engine. This engine including APBH-DMA
drivers/dma/mxs-dma.c
Diff comments   View file @ f5b7efc
... ... @@ -23,10 +23,10 @@
23 23 #include <linux/dmaengine.h>
24 24 #include <linux/delay.h>
25 25 #include <linux/fsl/mxs-dma.h>
  26 +#include <linux/stmp_device.h>
26 27  
27 28 #include <asm/irq.h>
28 29 #include <mach/mxs.h>
29   -#include <mach/common.h>
30 30  
31 31 #include "dmaengine.h"
32 32  
33 33  
... ... @@ -138,10 +138,10 @@
138 138  
139 139 if (dma_is_apbh() && apbh_is_old())
140 140 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
141   - mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
  141 + mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
142 142 else
143 143 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
144   - mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
  144 + mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
145 145 }
146 146  
147 147 static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
148 148  
... ... @@ -170,10 +170,10 @@
170 170 /* freeze the channel */
171 171 if (dma_is_apbh() && apbh_is_old())
172 172 writel(1 << chan_id,
173   - mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
  173 + mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
174 174 else
175 175 writel(1 << chan_id,
176   - mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
  176 + mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
177 177  
178 178 mxs_chan->status = DMA_PAUSED;
179 179 }
180 180  
... ... @@ -186,10 +186,10 @@
186 186 /* unfreeze the channel */
187 187 if (dma_is_apbh() && apbh_is_old())
188 188 writel(1 << chan_id,
189   - mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
  189 + mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
190 190 else
191 191 writel(1 << chan_id,
192   - mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
  192 + mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
193 193  
194 194 mxs_chan->status = DMA_IN_PROGRESS;
195 195 }
196 196  
... ... @@ -220,11 +220,11 @@
220 220 /* completion status */
221 221 stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
222 222 stat1 &= MXS_DMA_CHANNELS_MASK;
223   - writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
  223 + writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
224 224  
225 225 /* error status */
226 226 stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
227   - writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
  227 + writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
228 228  
229 229 /*
230 230 * When both completion and error of termination bits set at the
... ... @@ -567,7 +567,7 @@
567 567 if (ret)
568 568 return ret;
569 569  
570   - ret = mxs_reset_block(mxs_dma->base);
  570 + ret = stmp_reset_block(mxs_dma->base);
571 571 if (ret)
572 572 goto err_out;
573 573  
574 574  
575 575  
... ... @@ -580,14 +580,14 @@
580 580 /* enable apbh burst */
581 581 if (dma_is_apbh()) {
582 582 writel(BM_APBH_CTRL0_APB_BURST_EN,
583   - mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
  583 + mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
584 584 writel(BM_APBH_CTRL0_APB_BURST8_EN,
585   - mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
  585 + mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
586 586 }
587 587  
588 588 /* enable irq for all the channels */
589 589 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
590   - mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
  590 + mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
591 591  
592 592 err_out:
593 593 clk_disable_unprepare(mxs_dma->clk);