Commit f5fa4098c3fcc0e504fbc0682dccd331dbbcf197

Authored by Arnd Bergmann
Committed by Nicolas Ferre
1 parent 13ab6aeb49

ARM: at91: suspend both memory controllers on at91sam9263

For the past three years, we have had a #warning in
mach-at91 about the sdram_selfrefresh_enable or
at91sam9_standby functions possibly not working on
at91sam9263. In the meantime a function was added
to do the right thing on at91sam9g45, which looks like
it should also work on '9263.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: remove paragraph in commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>

Showing 3 changed files with 28 additions and 6 deletions Side-by-side Diff

arch/arm/mach-at91/cpuidle.c
... ... @@ -38,6 +38,8 @@
38 38 at91rm9200_standby();
39 39 else if (cpu_is_at91sam9g45())
40 40 at91sam9g45_standby();
  41 + else if (cpu_is_at91sam9263())
  42 + at91sam9263_standby();
41 43 else
42 44 at91sam9_standby();
43 45  
arch/arm/mach-at91/pm.c
... ... @@ -267,6 +267,8 @@
267 267 at91rm9200_standby();
268 268 else if (cpu_is_at91sam9g45())
269 269 at91sam9g45_standby();
  270 + else if (cpu_is_at91sam9263())
  271 + at91sam9263_standby();
270 272 else
271 273 at91sam9_standby();
272 274 break;
arch/arm/mach-at91/pm.h
... ... @@ -70,13 +70,31 @@
70 70 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
71 71 }
72 72  
73   -#ifdef CONFIG_SOC_AT91SAM9263
74   -/*
75   - * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
76   - * handle those cases both here and in the Suspend-To-RAM support.
  73 +/* We manage both DDRAM/SDRAM controllers, we need more than one value to
  74 + * remember.
77 75 */
78   -#warning Assuming EB1 SDRAM controller is *NOT* used
79   -#endif
  76 +static inline void at91sam9263_standby(void)
  77 +{
  78 + u32 lpr0, lpr1;
  79 + u32 saved_lpr0, saved_lpr1;
  80 +
  81 + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
  82 + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
  83 + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  84 +
  85 + saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
  86 + lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
  87 + lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  88 +
  89 + /* self-refresh mode now */
  90 + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
  91 + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
  92 +
  93 + cpu_do_idle();
  94 +
  95 + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
  96 + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
  97 +}
80 98  
81 99 static inline void at91sam9_standby(void)
82 100 {