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Commit f64ee87614e80ca270de0b80c5164ab05f4f1d98

Authored by Paul Mundt
1 parent 7960a1d02b
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

sh: Split out irqflags.h in to _32 and _64 variants. 

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 5 changed files with 294 additions and 199 deletions Side-by-side Diff

include/asm-sh/cpu-sh5/registers.h
Diff comments   View file @ f64ee87
  1 +#ifndef __ASM_SH64_REGISTERS_H
  2 +#define __ASM_SH64_REGISTERS_H
  3 +
  4 +/*
  5 + * This file is subject to the terms and conditions of the GNU General Public
  6 + * License. See the file "COPYING" in the main directory of this archive
  7 + * for more details.
  8 + *
  9 + * include/asm-sh64/registers.h
  10 + *
  11 + * Copyright (C) 2000, 2001 Paolo Alberelli
  12 + * Copyright (C) 2004 Richard Curnow
  13 + */
  14 +
  15 +#ifdef __ASSEMBLY__
  16 +/* =====================================================================
  17 +**
  18 +** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
  19 +** Assigns symbolic names to control & target registers.
  20 +*/
  21 +
  22 +/*
  23 + * Define some useful aliases for control registers.
  24 + */
  25 +#define SR cr0
  26 +#define SSR cr1
  27 +#define PSSR cr2
  28 + /* cr3 UNDEFINED */
  29 +#define INTEVT cr4
  30 +#define EXPEVT cr5
  31 +#define PEXPEVT cr6
  32 +#define TRA cr7
  33 +#define SPC cr8
  34 +#define PSPC cr9
  35 +#define RESVEC cr10
  36 +#define VBR cr11
  37 + /* cr12 UNDEFINED */
  38 +#define TEA cr13
  39 + /* cr14-cr15 UNDEFINED */
  40 +#define DCR cr16
  41 +#define KCR0 cr17
  42 +#define KCR1 cr18
  43 + /* cr19-cr31 UNDEFINED */
  44 + /* cr32-cr61 RESERVED */
  45 +#define CTC cr62
  46 +#define USR cr63
  47 +
  48 +/*
  49 + * ABI dependent registers (general purpose set)
  50 + */
  51 +#define RET r2
  52 +#define ARG1 r2
  53 +#define ARG2 r3
  54 +#define ARG3 r4
  55 +#define ARG4 r5
  56 +#define ARG5 r6
  57 +#define ARG6 r7
  58 +#define SP r15
  59 +#define LINK r18
  60 +#define ZERO r63
  61 +
  62 +/*
  63 + * Status register defines: used only by assembly sources (and
  64 + * syntax independednt)
  65 + */
  66 +#define SR_RESET_VAL 0x0000000050008000
  67 +#define SR_HARMLESS 0x00000000500080f0 /* Write ignores for most */
  68 +#define SR_ENABLE_FPU 0xffffffffffff7fff /* AND with this */
  69 +
  70 +#if defined (CONFIG_SH64_SR_WATCH)
  71 +#define SR_ENABLE_MMU 0x0000000084000000 /* OR with this */
  72 +#else
  73 +#define SR_ENABLE_MMU 0x0000000080000000 /* OR with this */
  74 +#endif
  75 +
  76 +#define SR_UNBLOCK_EXC 0xffffffffefffffff /* AND with this */
  77 +#define SR_BLOCK_EXC 0x0000000010000000 /* OR with this */
  78 +
  79 +#else /* Not __ASSEMBLY__ syntax */
  80 +
  81 +/*
  82 +** Stringify reg. name
  83 +*/
  84 +#define __str(x) #x
  85 +
  86 +/* Stringify control register names for use in inline assembly */
  87 +#define __SR __str(SR)
  88 +#define __SSR __str(SSR)
  89 +#define __PSSR __str(PSSR)
  90 +#define __INTEVT __str(INTEVT)
  91 +#define __EXPEVT __str(EXPEVT)
  92 +#define __PEXPEVT __str(PEXPEVT)
  93 +#define __TRA __str(TRA)
  94 +#define __SPC __str(SPC)
  95 +#define __PSPC __str(PSPC)
  96 +#define __RESVEC __str(RESVEC)
  97 +#define __VBR __str(VBR)
  98 +#define __TEA __str(TEA)
  99 +#define __DCR __str(DCR)
  100 +#define __KCR0 __str(KCR0)
  101 +#define __KCR1 __str(KCR1)
  102 +#define __CTC __str(CTC)
  103 +#define __USR __str(USR)
  104 +
  105 +#endif /* __ASSEMBLY__ */
  106 +#endif /* __ASM_SH64_REGISTERS_H */
include/asm-sh/irqflags.h
Diff comments   View file @ f64ee87
1 1 #ifndef __ASM_SH_IRQFLAGS_H
2 2 #define __ASM_SH_IRQFLAGS_H
3 3  
4   -static inline void raw_local_irq_enable(void)
5   -{
6   - unsigned long __dummy0, __dummy1;
7   -
8   - __asm__ __volatile__ (
9   - "stc sr, %0\n\t"
10   - "and %1, %0\n\t"
11   -#ifdef CONFIG_CPU_HAS_SR_RB
12   - "stc r6_bank, %1\n\t"
13   - "or %1, %0\n\t"
  4 +#ifdef CONFIG_SUPERH32
  5 +#include "irqflags_32.h"
  6 +#else
  7 +#include "irqflags_64.h"
14 8 #endif
15   - "ldc %0, sr\n\t"
16   - : "=&r" (__dummy0), "=r" (__dummy1)
17   - : "1" (~0x000000f0)
18   - : "memory"
19   - );
20   -}
21 9  
22   -static inline void raw_local_irq_disable(void)
23   -{
24   - unsigned long flags;
25   -
26   - __asm__ __volatile__ (
27   - "stc sr, %0\n\t"
28   - "or #0xf0, %0\n\t"
29   - "ldc %0, sr\n\t"
30   - : "=&z" (flags)
31   - : /* no inputs */
32   - : "memory"
33   - );
34   -}
35   -
36   -static inline void set_bl_bit(void)
37   -{
38   - unsigned long __dummy0, __dummy1;
39   -
40   - __asm__ __volatile__ (
41   - "stc sr, %0\n\t"
42   - "or %2, %0\n\t"
43   - "and %3, %0\n\t"
44   - "ldc %0, sr\n\t"
45   - : "=&r" (__dummy0), "=r" (__dummy1)
46   - : "r" (0x10000000), "r" (0xffffff0f)
47   - : "memory"
48   - );
49   -}
50   -
51   -static inline void clear_bl_bit(void)
52   -{
53   - unsigned long __dummy0, __dummy1;
54   -
55   - __asm__ __volatile__ (
56   - "stc sr, %0\n\t"
57   - "and %2, %0\n\t"
58   - "ldc %0, sr\n\t"
59   - : "=&r" (__dummy0), "=r" (__dummy1)
60   - : "1" (~0x10000000)
61   - : "memory"
62   - );
63   -}
64   -
65   -static inline unsigned long __raw_local_save_flags(void)
66   -{
67   - unsigned long flags;
68   -
69   - __asm__ __volatile__ (
70   - "stc sr, %0\n\t"
71   - "and #0xf0, %0\n\t"
72   - : "=&z" (flags)
73   - : /* no inputs */
74   - : "memory"
75   - );
76   -
77   - return flags;
78   -}
79   -
80 10 #define raw_local_save_flags(flags) \
81 11 do { (flags) = __raw_local_save_flags(); } while (0)
82 12  
... ... @@ -90,25 +20,6 @@
90 20 unsigned long flags = __raw_local_save_flags();
91 21  
92 22 return raw_irqs_disabled_flags(flags);
93   -}
94   -
95   -static inline unsigned long __raw_local_irq_save(void)
96   -{
97   - unsigned long flags, __dummy;
98   -
99   - __asm__ __volatile__ (
100   - "stc sr, %1\n\t"
101   - "mov %1, %0\n\t"
102   - "or #0xf0, %0\n\t"
103   - "ldc %0, sr\n\t"
104   - "mov %1, %0\n\t"
105   - "and #0xf0, %0\n\t"
106   - : "=&z" (flags), "=&r" (__dummy)
107   - : /* no inputs */
108   - : "memory"
109   - );
110   -
111   - return flags;
112 23 }
113 24  
114 25 #define raw_local_irq_save(flags) \
include/asm-sh/irqflags_32.h
Diff comments   View file @ f64ee87
  1 +#ifndef __ASM_SH_IRQFLAGS_32_H
  2 +#define __ASM_SH_IRQFLAGS_32_H
  3 +
  4 +static inline void raw_local_irq_enable(void)
  5 +{
  6 + unsigned long __dummy0, __dummy1;
  7 +
  8 + __asm__ __volatile__ (
  9 + "stc sr, %0\n\t"
  10 + "and %1, %0\n\t"
  11 +#ifdef CONFIG_CPU_HAS_SR_RB
  12 + "stc r6_bank, %1\n\t"
  13 + "or %1, %0\n\t"
  14 +#endif
  15 + "ldc %0, sr\n\t"
  16 + : "=&r" (__dummy0), "=r" (__dummy1)
  17 + : "1" (~0x000000f0)
  18 + : "memory"
  19 + );
  20 +}
  21 +
  22 +static inline void raw_local_irq_disable(void)
  23 +{
  24 + unsigned long flags;
  25 +
  26 + __asm__ __volatile__ (
  27 + "stc sr, %0\n\t"
  28 + "or #0xf0, %0\n\t"
  29 + "ldc %0, sr\n\t"
  30 + : "=&z" (flags)
  31 + : /* no inputs */
  32 + : "memory"
  33 + );
  34 +}
  35 +
  36 +static inline void set_bl_bit(void)
  37 +{
  38 + unsigned long __dummy0, __dummy1;
  39 +
  40 + __asm__ __volatile__ (
  41 + "stc sr, %0\n\t"
  42 + "or %2, %0\n\t"
  43 + "and %3, %0\n\t"
  44 + "ldc %0, sr\n\t"
  45 + : "=&r" (__dummy0), "=r" (__dummy1)
  46 + : "r" (0x10000000), "r" (0xffffff0f)
  47 + : "memory"
  48 + );
  49 +}
  50 +
  51 +static inline void clear_bl_bit(void)
  52 +{
  53 + unsigned long __dummy0, __dummy1;
  54 +
  55 + __asm__ __volatile__ (
  56 + "stc sr, %0\n\t"
  57 + "and %2, %0\n\t"
  58 + "ldc %0, sr\n\t"
  59 + : "=&r" (__dummy0), "=r" (__dummy1)
  60 + : "1" (~0x10000000)
  61 + : "memory"
  62 + );
  63 +}
  64 +
  65 +static inline unsigned long __raw_local_save_flags(void)
  66 +{
  67 + unsigned long flags;
  68 +
  69 + __asm__ __volatile__ (
  70 + "stc sr, %0\n\t"
  71 + "and #0xf0, %0\n\t"
  72 + : "=&z" (flags)
  73 + : /* no inputs */
  74 + : "memory"
  75 + );
  76 +
  77 + return flags;
  78 +}
  79 +
  80 +static inline unsigned long __raw_local_irq_save(void)
  81 +{
  82 + unsigned long flags, __dummy;
  83 +
  84 + __asm__ __volatile__ (
  85 + "stc sr, %1\n\t"
  86 + "mov %1, %0\n\t"
  87 + "or #0xf0, %0\n\t"
  88 + "ldc %0, sr\n\t"
  89 + "mov %1, %0\n\t"
  90 + "and #0xf0, %0\n\t"
  91 + : "=&z" (flags), "=&r" (__dummy)
  92 + : /* no inputs */
  93 + : "memory"
  94 + );
  95 +
  96 + return flags;
  97 +}
  98 +
  99 +#endif /* __ASM_SH_IRQFLAGS_32_H */
include/asm-sh/irqflags_64.h
Diff comments   View file @ f64ee87
  1 +#ifndef __ASM_SH_IRQFLAGS_64_H
  2 +#define __ASM_SH_IRQFLAGS_64_H
  3 +
  4 +#include <asm/cpu/registers.h>
  5 +
  6 +#define SR_MASK_LL 0x00000000000000f0LL
  7 +#define SR_BL_LL 0x0000000010000000LL
  8 +
  9 +static inline void raw_local_irq_enable(void)
  10 +{
  11 + unsigned long long __dummy0, __dummy1 = ~SR_MASK_LL;
  12 +
  13 + __asm__ __volatile__("getcon " __SR ", %0\n\t"
  14 + "and %0, %1, %0\n\t"
  15 + "putcon %0, " __SR "\n\t"
  16 + : "=&r" (__dummy0)
  17 + : "r" (__dummy1));
  18 +}
  19 +
  20 +static inline void raw_local_irq_disable(void)
  21 +{
  22 + unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
  23 +
  24 + __asm__ __volatile__("getcon " __SR ", %0\n\t"
  25 + "or %0, %1, %0\n\t"
  26 + "putcon %0, " __SR "\n\t"
  27 + : "=&r" (__dummy0)
  28 + : "r" (__dummy1));
  29 +}
  30 +
  31 +static inline void set_bl_bit(void)
  32 +{
  33 + unsigned long long __dummy0, __dummy1 = SR_BL_LL;
  34 +
  35 + __asm__ __volatile__("getcon " __SR ", %0\n\t"
  36 + "or %0, %1, %0\n\t"
  37 + "putcon %0, " __SR "\n\t"
  38 + : "=&r" (__dummy0)
  39 + : "r" (__dummy1));
  40 +
  41 +}
  42 +
  43 +static inline void clear_bl_bit(void)
  44 +{
  45 + unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
  46 +
  47 + __asm__ __volatile__("getcon " __SR ", %0\n\t"
  48 + "and %0, %1, %0\n\t"
  49 + "putcon %0, " __SR "\n\t"
  50 + : "=&r" (__dummy0)
  51 + : "r" (__dummy1));
  52 +}
  53 +
  54 +static inline unsigned long __raw_local_save_flags(void)
  55 +{
  56 + unsigned long long __dummy = SR_MASK_LL;
  57 + unsigned long flags;
  58 +
  59 + __asm__ __volatile__ (
  60 + "getcon " __SR ", %0\n\t"
  61 + "and %0, %1, %0"
  62 + : "=&r" (flags)
  63 + : "r" (__dummy));
  64 +
  65 + return flags;
  66 +}
  67 +
  68 +static inline unsigned long __raw_local_irq_save(void)
  69 +{
  70 + unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
  71 + unsigned long flags;
  72 +
  73 + __asm__ __volatile__ (
  74 + "getcon " __SR ", %1\n\t"
  75 + "or %1, r63, %0\n\t"
  76 + "or %1, %2, %1\n\t"
  77 + "putcon %1, " __SR "\n\t"
  78 + "and %0, %2, %0"
  79 + : "=&r" (flags), "=&r" (__dummy0)
  80 + : "r" (__dummy1));
  81 +
  82 + return flags;
  83 +}
  84 +
  85 +#endif /* __ASM_SH_IRQFLAGS_64_H */
include/asm-sh64/registers.h
View file @ f64ee87
1   -#ifndef __ASM_SH64_REGISTERS_H
2   -#define __ASM_SH64_REGISTERS_H
3   -
4   -/*
5   - * This file is subject to the terms and conditions of the GNU General Public
6   - * License. See the file "COPYING" in the main directory of this archive
7   - * for more details.
8   - *
9   - * include/asm-sh64/registers.h
10   - *
11   - * Copyright (C) 2000, 2001 Paolo Alberelli
12   - * Copyright (C) 2004 Richard Curnow
13   - */
14   -
15   -#ifdef __ASSEMBLY__
16   -/* =====================================================================
17   -**
18   -** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
19   -** Assigns symbolic names to control & target registers.
20   -*/
21   -
22   -/*
23   - * Define some useful aliases for control registers.
24   - */
25   -#define SR cr0
26   -#define SSR cr1
27   -#define PSSR cr2
28   - /* cr3 UNDEFINED */
29   -#define INTEVT cr4
30   -#define EXPEVT cr5
31   -#define PEXPEVT cr6
32   -#define TRA cr7
33   -#define SPC cr8
34   -#define PSPC cr9
35   -#define RESVEC cr10
36   -#define VBR cr11
37   - /* cr12 UNDEFINED */
38   -#define TEA cr13
39   - /* cr14-cr15 UNDEFINED */
40   -#define DCR cr16
41   -#define KCR0 cr17
42   -#define KCR1 cr18
43   - /* cr19-cr31 UNDEFINED */
44   - /* cr32-cr61 RESERVED */
45   -#define CTC cr62
46   -#define USR cr63
47   -
48   -/*
49   - * ABI dependent registers (general purpose set)
50   - */
51   -#define RET r2
52   -#define ARG1 r2
53   -#define ARG2 r3
54   -#define ARG3 r4
55   -#define ARG4 r5
56   -#define ARG5 r6
57   -#define ARG6 r7
58   -#define SP r15
59   -#define LINK r18
60   -#define ZERO r63
61   -
62   -/*
63   - * Status register defines: used only by assembly sources (and
64   - * syntax independednt)
65   - */
66   -#define SR_RESET_VAL 0x0000000050008000
67   -#define SR_HARMLESS 0x00000000500080f0 /* Write ignores for most */
68   -#define SR_ENABLE_FPU 0xffffffffffff7fff /* AND with this */
69   -
70   -#if defined (CONFIG_SH64_SR_WATCH)
71   -#define SR_ENABLE_MMU 0x0000000084000000 /* OR with this */
72   -#else
73   -#define SR_ENABLE_MMU 0x0000000080000000 /* OR with this */
74   -#endif
75   -
76   -#define SR_UNBLOCK_EXC 0xffffffffefffffff /* AND with this */
77   -#define SR_BLOCK_EXC 0x0000000010000000 /* OR with this */
78   -
79   -#else /* Not __ASSEMBLY__ syntax */
80   -
81   -/*
82   -** Stringify reg. name
83   -*/
84   -#define __str(x) #x
85   -
86   -/* Stringify control register names for use in inline assembly */
87   -#define __SR __str(SR)
88   -#define __SSR __str(SSR)
89   -#define __PSSR __str(PSSR)
90   -#define __INTEVT __str(INTEVT)
91   -#define __EXPEVT __str(EXPEVT)
92   -#define __PEXPEVT __str(PEXPEVT)
93   -#define __TRA __str(TRA)
94   -#define __SPC __str(SPC)
95   -#define __PSPC __str(PSPC)
96   -#define __RESVEC __str(RESVEC)
97   -#define __VBR __str(VBR)
98   -#define __TEA __str(TEA)
99   -#define __DCR __str(DCR)
100   -#define __KCR0 __str(KCR0)
101   -#define __KCR1 __str(KCR1)
102   -#define __CTC __str(CTC)
103   -#define __USR __str(USR)
104   -
105   -#endif /* __ASSEMBLY__ */
106   -#endif /* __ASM_SH64_REGISTERS_H */