m68k/mvme16x: Add support for EARLY_PRINTK

Added support for EARLY_PRINTK when running on an MVME16x board. Signed-off-by: Kars de Jong <jongk@linux-m68k.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>

m68k/mvme16x: Add support for EARLY_PRINTK
Added support for EARLY_PRINTK when running on an MVME16x board. Signed-off-by: Kars de Jong <jongk@linux-m68k.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Kars de Jong · Geert Uytterhoeven
1 parent f8bd9de913
Showing 2 changed files with 171 additions and 0 deletions Side-by-side Diff
arch/m68k/Kconfig.debug
arch/m68k/mvme16x/config.c
@@ -2,6 +2,17 @@
  
 source "lib/Kconfig.debug"
  
+config EARLY_PRINTK
+	bool "Early printk" if EMBEDDED
+	depends on MVME16x
+	default y
+	help
+          Write kernel log output directly to a serial port.
+
+          This is useful for kernel debugging when your machine crashes very
+          early before the console code is initialized.
+          You should normally say N here, unless you want to debug such a crash.
+
 if !MMU
  
 config FULLDEBUG
@@ -124,7 +124,164 @@
 #define PccSCCMICR	0x1d
 #define PccSCCTICR	0x1e
 #define PccSCCRICR	0x1f
+#define PccTPIACKR	0x25
  
+#ifdef CONFIG_EARLY_PRINTK
+
+/**** cd2401 registers ****/
+#define CD2401_ADDR	(0xfff45000)
+
+#define CyGFRCR         (0x81)
+#define CyCCR		(0x13)
+#define      CyCLR_CHAN		(0x40)
+#define      CyINIT_CHAN	(0x20)
+#define      CyCHIP_RESET	(0x10)
+#define      CyENB_XMTR		(0x08)
+#define      CyDIS_XMTR		(0x04)
+#define      CyENB_RCVR		(0x02)
+#define      CyDIS_RCVR		(0x01)
+#define CyCAR		(0xee)
+#define CyIER		(0x11)
+#define      CyMdmCh		(0x80)
+#define      CyRxExc		(0x20)
+#define      CyRxData		(0x08)
+#define      CyTxMpty		(0x02)
+#define      CyTxRdy		(0x01)
+#define CyLICR		(0x26)
+#define CyRISR		(0x89)
+#define      CyTIMEOUT		(0x80)
+#define      CySPECHAR		(0x70)
+#define      CyOVERRUN		(0x08)
+#define      CyPARITY		(0x04)
+#define      CyFRAME		(0x02)
+#define      CyBREAK		(0x01)
+#define CyREOIR		(0x84)
+#define CyTEOIR		(0x85)
+#define CyMEOIR		(0x86)
+#define      CyNOTRANS		(0x08)
+#define CyRFOC		(0x30)
+#define CyRDR		(0xf8)
+#define CyTDR		(0xf8)
+#define CyMISR		(0x8b)
+#define CyRISR		(0x89)
+#define CyTISR		(0x8a)
+#define CyMSVR1		(0xde)
+#define CyMSVR2		(0xdf)
+#define      CyDSR		(0x80)
+#define      CyDCD		(0x40)
+#define      CyCTS		(0x20)
+#define      CyDTR		(0x02)
+#define      CyRTS		(0x01)
+#define CyRTPRL		(0x25)
+#define CyRTPRH		(0x24)
+#define CyCOR1		(0x10)
+#define      CyPARITY_NONE	(0x00)
+#define      CyPARITY_E		(0x40)
+#define      CyPARITY_O		(0xC0)
+#define      Cy_5_BITS		(0x04)
+#define      Cy_6_BITS		(0x05)
+#define      Cy_7_BITS		(0x06)
+#define      Cy_8_BITS		(0x07)
+#define CyCOR2		(0x17)
+#define      CyETC		(0x20)
+#define      CyCtsAE		(0x02)
+#define CyCOR3		(0x16)
+#define      Cy_1_STOP		(0x02)
+#define      Cy_2_STOP		(0x04)
+#define CyCOR4		(0x15)
+#define      CyREC_FIFO		(0x0F)  /* Receive FIFO threshold */
+#define CyCOR5		(0x14)
+#define CyCOR6		(0x18)
+#define CyCOR7		(0x07)
+#define CyRBPR		(0xcb)
+#define CyRCOR		(0xc8)
+#define CyTBPR		(0xc3)
+#define CyTCOR		(0xc0)
+#define CySCHR1		(0x1f)
+#define CySCHR2 	(0x1e)
+#define CyTPR		(0xda)
+#define CyPILR1		(0xe3)
+#define CyPILR2		(0xe0)
+#define CyPILR3		(0xe1)
+#define CyCMR		(0x1b)
+#define      CyASYNC		(0x02)
+#define CyLICR          (0x26)
+#define CyLIVR          (0x09)
+#define CySCRL		(0x23)
+#define CySCRH		(0x22)
+#define CyTFTC		(0x80)
+
+static void cons_write(struct console *co, const char *str, unsigned count)
+{
+	volatile unsigned char *base_addr = (u_char *)CD2401_ADDR;
+	volatile u_char sink;
+	u_char ier;
+	int port;
+	u_char do_lf = 0;
+	int i = 0;
+
+	/* Ensure transmitter is enabled! */
+
+	port = 0;
+	base_addr[CyCAR] = (u_char)port;
+	while (base_addr[CyCCR])
+		;
+	base_addr[CyCCR] = CyENB_XMTR;
+
+	ier = base_addr[CyIER];
+	base_addr[CyIER] = CyTxMpty;
+
+	while (1) {
+		if (pcc2chip[PccSCCTICR] & 0x20)
+		{
+			/* We have a Tx int. Acknowledge it */
+			sink = pcc2chip[PccTPIACKR];
+			if ((base_addr[CyLICR] >> 2) == port) {
+				if (i == count) {
+					/* Last char of string is now output */
+					base_addr[CyTEOIR] = CyNOTRANS;
+					break;
+				}
+				if (do_lf) {
+					base_addr[CyTDR] = '\n';
+					str++;
+					i++;
+					do_lf = 0;
+				}
+				else if (*str == '\n') {
+					base_addr[CyTDR] = '\r';
+					do_lf = 1;
+				}
+				else {
+					base_addr[CyTDR] = *str++;
+					i++;
+				}
+				base_addr[CyTEOIR] = 0;
+			}
+			else
+				base_addr[CyTEOIR] = CyNOTRANS;
+		}
+	}
+
+	base_addr[CyIER] = ier;
+}
+
+static struct console cons_info =
+{
+	.name	= "sercon",
+	.write	= cons_write,
+	.flags	= CON_PRINTBUFFER | CON_BOOT,
+	.index	= -1,
+};
+
+static void __init mvme16x_early_console(void)
+{
+	register_console(&cons_info);
+
+	printk(KERN_INFO "MVME16x: early console registered\n");
+}
+#endif
+
 void __init config_mvme16x(void)
 {
     p_bdid p = &mvme_bdid;
@@ -183,6 +340,9 @@
 	pcc2chip[PccSCCMICR] = 0x10;
 	pcc2chip[PccSCCTICR] = 0x10;
 	pcc2chip[PccSCCRICR] = 0x10;
+#ifdef CONFIG_EARLY_PRINTK
+	mvme16x_early_console();
+#endif
     }
 }
...	...	@@ -2,6 +2,17 @@
2	2
3	3	source "lib/Kconfig.debug"
4	4
	5	+config EARLY_PRINTK
	6	+ bool "Early printk" if EMBEDDED
	7	+ depends on MVME16x
	8	+ default y
	9	+ help
	10	+ Write kernel log output directly to a serial port.
	11	+
	12	+ This is useful for kernel debugging when your machine crashes very
	13	+ early before the console code is initialized.
	14	+ You should normally say N here, unless you want to debug such a crash.
	15	+
5	16	if !MMU
6	17
7	18	config FULLDEBUG
...	...	@@ -124,7 +124,164 @@
124	124	#define PccSCCMICR 0x1d
125	125	#define PccSCCTICR 0x1e
126	126	#define PccSCCRICR 0x1f
	127	+#define PccTPIACKR 0x25
127	128
	129	+#ifdef CONFIG_EARLY_PRINTK
	130	+
	131	+/** cd2401 registers **/
	132	+#define CD2401_ADDR (0xfff45000)
	133	+
	134	+#define CyGFRCR (0x81)
	135	+#define CyCCR (0x13)
	136	+#define CyCLR_CHAN (0x40)
	137	+#define CyINIT_CHAN (0x20)
	138	+#define CyCHIP_RESET (0x10)
	139	+#define CyENB_XMTR (0x08)
	140	+#define CyDIS_XMTR (0x04)
	141	+#define CyENB_RCVR (0x02)
	142	+#define CyDIS_RCVR (0x01)
	143	+#define CyCAR (0xee)
	144	+#define CyIER (0x11)
	145	+#define CyMdmCh (0x80)
	146	+#define CyRxExc (0x20)
	147	+#define CyRxData (0x08)
	148	+#define CyTxMpty (0x02)
	149	+#define CyTxRdy (0x01)
	150	+#define CyLICR (0x26)
	151	+#define CyRISR (0x89)
	152	+#define CyTIMEOUT (0x80)
	153	+#define CySPECHAR (0x70)
	154	+#define CyOVERRUN (0x08)
	155	+#define CyPARITY (0x04)
	156	+#define CyFRAME (0x02)
	157	+#define CyBREAK (0x01)
	158	+#define CyREOIR (0x84)
	159	+#define CyTEOIR (0x85)
	160	+#define CyMEOIR (0x86)
	161	+#define CyNOTRANS (0x08)
	162	+#define CyRFOC (0x30)
	163	+#define CyRDR (0xf8)
	164	+#define CyTDR (0xf8)
	165	+#define CyMISR (0x8b)
	166	+#define CyRISR (0x89)
	167	+#define CyTISR (0x8a)
	168	+#define CyMSVR1 (0xde)
	169	+#define CyMSVR2 (0xdf)
	170	+#define CyDSR (0x80)
	171	+#define CyDCD (0x40)
	172	+#define CyCTS (0x20)
	173	+#define CyDTR (0x02)
	174	+#define CyRTS (0x01)
	175	+#define CyRTPRL (0x25)
	176	+#define CyRTPRH (0x24)
	177	+#define CyCOR1 (0x10)
	178	+#define CyPARITY_NONE (0x00)
	179	+#define CyPARITY_E (0x40)
	180	+#define CyPARITY_O (0xC0)
	181	+#define Cy_5_BITS (0x04)
	182	+#define Cy_6_BITS (0x05)
	183	+#define Cy_7_BITS (0x06)
	184	+#define Cy_8_BITS (0x07)
	185	+#define CyCOR2 (0x17)
	186	+#define CyETC (0x20)
	187	+#define CyCtsAE (0x02)
	188	+#define CyCOR3 (0x16)
	189	+#define Cy_1_STOP (0x02)
	190	+#define Cy_2_STOP (0x04)
	191	+#define CyCOR4 (0x15)
	192	+#define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
	193	+#define CyCOR5 (0x14)
	194	+#define CyCOR6 (0x18)
	195	+#define CyCOR7 (0x07)
	196	+#define CyRBPR (0xcb)
	197	+#define CyRCOR (0xc8)
	198	+#define CyTBPR (0xc3)
	199	+#define CyTCOR (0xc0)
	200	+#define CySCHR1 (0x1f)
	201	+#define CySCHR2 (0x1e)
	202	+#define CyTPR (0xda)
	203	+#define CyPILR1 (0xe3)
	204	+#define CyPILR2 (0xe0)
	205	+#define CyPILR3 (0xe1)
	206	+#define CyCMR (0x1b)
	207	+#define CyASYNC (0x02)
	208	+#define CyLICR (0x26)
	209	+#define CyLIVR (0x09)
	210	+#define CySCRL (0x23)
	211	+#define CySCRH (0x22)
	212	+#define CyTFTC (0x80)
	213	+
	214	+static void cons_write(struct console co, const char str, unsigned count)
	215	+{
	216	+ volatile unsigned char base_addr = (u_char )CD2401_ADDR;
	217	+ volatile u_char sink;
	218	+ u_char ier;
	219	+ int port;
	220	+ u_char do_lf = 0;
	221	+ int i = 0;
	222	+
	223	+ /* Ensure transmitter is enabled! */
	224	+
	225	+ port = 0;
	226	+ base_addr[CyCAR] = (u_char)port;
	227	+ while (base_addr[CyCCR])
	228	+ ;
	229	+ base_addr[CyCCR] = CyENB_XMTR;
	230	+
	231	+ ier = base_addr[CyIER];
	232	+ base_addr[CyIER] = CyTxMpty;
	233	+
	234	+ while (1) {
	235	+ if (pcc2chip[PccSCCTICR] & 0x20)
	236	+ {
	237	+ /* We have a Tx int. Acknowledge it */
	238	+ sink = pcc2chip[PccTPIACKR];
	239	+ if ((base_addr[CyLICR] >> 2) == port) {
	240	+ if (i == count) {
	241	+ /* Last char of string is now output */
	242	+ base_addr[CyTEOIR] = CyNOTRANS;
	243	+ break;
	244	+ }
	245	+ if (do_lf) {
	246	+ base_addr[CyTDR] = '\n';
	247	+ str++;
	248	+ i++;
	249	+ do_lf = 0;
	250	+ }
	251	+ else if (*str == '\n') {
	252	+ base_addr[CyTDR] = '\r';
	253	+ do_lf = 1;
	254	+ }
	255	+ else {
	256	+ base_addr[CyTDR] = *str++;
	257	+ i++;
	258	+ }
	259	+ base_addr[CyTEOIR] = 0;
	260	+ }
	261	+ else
	262	+ base_addr[CyTEOIR] = CyNOTRANS;
	263	+ }
	264	+ }
	265	+
	266	+ base_addr[CyIER] = ier;
	267	+}
	268	+
	269	+static struct console cons_info =
	270	+{
	271	+ .name = "sercon",
	272	+ .write = cons_write,
	273	+ .flags = CON_PRINTBUFFER \| CON_BOOT,
	274	+ .index = -1,
	275	+};
	276	+
	277	+static void __init mvme16x_early_console(void)
	278	+{
	279	+ register_console(&cons_info);
	280	+
	281	+ printk(KERN_INFO "MVME16x: early console registered\n");
	282	+}
	283	+#endif
	284	+
128	285	void __init config_mvme16x(void)
129	286	{
130	287	p_bdid p = &mvme_bdid;
...	...	@@ -183,6 +340,9 @@
183	340	pcc2chip[PccSCCMICR] = 0x10;
184	341	pcc2chip[PccSCCTICR] = 0x10;
185	342	pcc2chip[PccSCCRICR] = 0x10;
	343	+#ifdef CONFIG_EARLY_PRINTK
	344	+ mvme16x_early_console();
	345	+#endif
186	346	}
187	347	}
188	348