[ARM] Separate VIC (vectored interrupt controller) support from Versatile

Other machines may wish to make use of the VIC support code, so move it to arch/arm/common. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

[ARM] Separate VIC (vectored interrupt controller) support from Versatile
Other machines may wish to make use of the VIC support code, so move it to arch/arm/common. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King · Russell King
1 parent 5ff3fd2716
Showing 8 changed files with 151 additions and 77 deletions Side-by-side Diff
arch/arm/Kconfig
arch/arm/common/Kconfig
arch/arm/common/Makefile
arch/arm/common/vic.c
arch/arm/mach-versatile/core.c
include/asm-arm/arch-versatile/entry-macro.S
include/asm-arm/arch-versatile/platform.h
include/asm-arm/hardware/vic.h
@@ -180,6 +180,7 @@
 config ARCH_VERSATILE
 	bool "Versatile"
 	select ARM_AMBA
+	select ARM_VIC
 	select ICST307
 	help
 	  This enables support for ARM Ltd Versatile board.
-config ICST525
+config ARM_GIC
 	bool
  
-config ARM_GIC
+config ARM_VIC
+	bool
+
+config ICST525
 	bool
  
 config ICST307
@@ -4,6 +4,7 @@
  
 obj-y				+= rtctime.o
 obj-$(CONFIG_ARM_GIC)		+= gic.o
+obj-$(CONFIG_ARM_VIC)		+= vic.o
 obj-$(CONFIG_ICST525)		+= icst525.o
 obj-$(CONFIG_ICST307)		+= icst307.o
 obj-$(CONFIG_SA1111)		+= sa1111.o
+/*
+ *  linux/arch/arm/common/vic.c
+ *
+ *  Copyright (C) 1999 - 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/list.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/hardware/vic.h>
+
+static void __iomem *vic_base;
+
+static void vic_mask_irq(unsigned int irq)
+{
+	irq -= IRQ_VIC_START;
+	writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR);
+}
+
+static void vic_unmask_irq(unsigned int irq)
+{
+	irq -= IRQ_VIC_START;
+	writel(1 << irq, vic_base + VIC_INT_ENABLE);
+}
+
+static struct irqchip vic_chip = {
+	.ack	= vic_mask_irq,
+	.mask	= vic_mask_irq,
+	.unmask	= vic_unmask_irq,
+};
+
+void __init vic_init(void __iomem *base, u32 vic_sources)
+{
+	unsigned int i;
+
+	vic_base = base;
+
+	/* Disable all interrupts initially. */
+
+	writel(0, vic_base + VIC_INT_SELECT);
+	writel(0, vic_base + VIC_INT_ENABLE);
+	writel(~0, vic_base + VIC_INT_ENABLE_CLEAR);
+	writel(0, vic_base + VIC_IRQ_STATUS);
+	writel(0, vic_base + VIC_ITCR);
+	writel(~0, vic_base + VIC_INT_SOFT_CLEAR);
+
+	/*
+	 * Make sure we clear all existing interrupts
+	 */
+	writel(0, vic_base + VIC_VECT_ADDR);
+	for (i = 0; i < 19; i++) {
+		unsigned int value;
+
+		value = readl(vic_base + VIC_VECT_ADDR);
+		writel(value, vic_base + VIC_VECT_ADDR);
+	}
+
+	for (i = 0; i < 16; i++) {
+		void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4);
+		writel(VIC_VECT_CNTL_ENABLE | i, reg);
+	}
+
+	writel(32, vic_base + VIC_DEF_VECT_ADDR);
+
+	for (i = 0; i < 32; i++) {
+		unsigned int irq = IRQ_VIC_START + i;
+
+		set_irq_chip(irq, &vic_chip);
+
+		if (vic_sources & (1 << i)) {
+			set_irq_handler(irq, do_level_IRQ);
+			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+		}
+	}
+}
@@ -35,6 +35,7 @@
 #include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst307.h>
+#include <asm/hardware/vic.h>
  
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -56,24 +57,6 @@
 #define VA_VIC_BASE		__io_address(VERSATILE_VIC_BASE)
 #define VA_SIC_BASE		__io_address(VERSATILE_SIC_BASE)
  
-static void vic_mask_irq(unsigned int irq)
-{
-	irq -= IRQ_VIC_START;
-	writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
-}
-
-static void vic_unmask_irq(unsigned int irq)
-{
-	irq -= IRQ_VIC_START;
-	writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
-}
-
-static struct irqchip vic_chip = {
-	.ack	= vic_mask_irq,
-	.mask	= vic_mask_irq,
-	.unmask	= vic_unmask_irq,
-};
-
 static void sic_mask_irq(unsigned int irq)
 {
 	irq -= IRQ_SIC_START;
  
  
  
@@ -127,43 +110,12 @@
  
 void __init versatile_init_irq(void)
 {
-	unsigned int i, value;
+	unsigned int i;
  
-	/* Disable all interrupts initially. */
+	vic_init(VA_VIC_BASE, ~(1 << 31));
  
-	writel(0, VA_VIC_BASE + VIC_INT_SELECT);
-	writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
-	writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
-	writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
-	writel(0, VA_VIC_BASE + VIC_ITCR);
-	writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
-
-	/*
-	 * Make sure we clear all existing interrupts
-	 */
-	writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
-	for (i = 0; i < 19; i++) {
-		value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
-		writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
-	}
-
-	for (i = 0; i < 16; i++) {
-		value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
-		writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
-	}
-
-	writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
-
-	for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
-		if (i != IRQ_VICSOURCE31) {
-			set_irq_chip(i, &vic_chip);
-			set_irq_handler(i, do_level_IRQ);
-			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-		}
-	}
-
 	set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
-	vic_unmask_irq(IRQ_VICSOURCE31);
+	enable_irq(IRQ_VICSOURCE31);
  
 	/* Do second interrupt controller */
 	writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
@@ -877,7 +829,7 @@
 	ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 	do {
 		ticks1 = ticks2;
-		status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
+		status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
 		ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 	} while (ticks2 > ticks1);
  
@@ -8,6 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 #include <asm/hardware.h>
+#include <asm/hardware/vic.h>
  
 		.macro	disable_fiq
 		.endm
@@ -293,27 +293,8 @@
  * 	VERSATILE_SYS_IC 
  * 
  */
-#define VIC_IRQ_STATUS                  0
-#define VIC_FIQ_STATUS                  0x04
-#define VIC_IRQ_RAW_STATUS              0x08
-#define VIC_INT_SELECT                  0x0C	/* 1 = FIQ, 0 = IRQ */
-#define VIC_IRQ_ENABLE                  0x10	/* 1 = enable, 0 = disable */
-#define VIC_IRQ_ENABLE_CLEAR            0x14
-#define VIC_IRQ_SOFT                    0x18
-#define VIC_IRQ_SOFT_CLEAR              0x1C
-#define VIC_PROTECT                     0x20
-#define VIC_VECT_ADDR                   0x30
-#define VIC_DEF_VECT_ADDR               0x34
-#define VIC_VECT_ADDR0                  0x100	/* 0 to 15 */
-#define VIC_VECT_CNTL0                  0x200	/* 0 to 15 */
-#define VIC_ITCR                        0x300   /* VIC test control register */
+/* VIC definitions in include/asm-arm/hardware/vic.h */
  
-#define VIC_FIQ_RAW_STATUS              0x08
-#define VIC_FIQ_ENABLE                  0x10	/* 1 = enable, 0 = disable */
-#define VIC_FIQ_ENABLE_CLEAR            0x14
-#define VIC_FIQ_SOFT                    0x18
-#define VIC_FIQ_SOFT_CLEAR              0x1C
-
 #define SIC_IRQ_STATUS                  0
 #define SIC_IRQ_RAW_STATUS              0x04
 #define SIC_IRQ_ENABLE                  0x08
@@ -324,8 +305,6 @@
 #define SIC_INT_PIC_ENABLE              0x20	/* read status of pass through mask */
 #define SIC_INT_PIC_ENABLES             0x20	/* set interrupt pass through bits */
 #define SIC_INT_PIC_ENABLEC             0x24	/* Clear interrupt pass through bits */
-
-#define VICVectCntl_Enable		(1 << 5)
  
 /* ------------------------------------------------------------------------
  *  Interrupts - bit assignment (primary)
+/*
+ *  linux/include/asm-arm/hardware/vic.h
+ *
+ *  Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_HARDWARE_VIC_H
+#define __ASM_ARM_HARDWARE_VIC_H
+
+#define VIC_IRQ_STATUS			0x00
+#define VIC_FIQ_STATUS			0x04
+#define VIC_RAW_STATUS			0x08
+#define VIC_INT_SELECT			0x0c	/* 1 = FIQ, 0 = IRQ */
+#define VIC_INT_ENABLE			0x10	/* 1 = enable, 0 = disable */
+#define VIC_INT_ENABLE_CLEAR		0x14
+#define VIC_INT_SOFT			0x18
+#define VIC_INT_SOFT_CLEAR		0x1c
+#define VIC_PROTECT			0x20
+#define VIC_VECT_ADDR			0x30
+#define VIC_DEF_VECT_ADDR		0x34
+
+#define VIC_VECT_ADDR0			0x100	/* 0 to 15 */
+#define VIC_VECT_CNTL0			0x200	/* 0 to 15 */
+#define VIC_ITCR			0x300	/* VIC test control register */
+
+#define VIC_VECT_CNTL_ENABLE		(1 << 5)
+
+#ifndef __ASSEMBLY__
+void vic_init(void __iomem *base, u32 vic_sources);
+#endif
+
+#endif
...	...	@@ -180,6 +180,7 @@
180	180	config ARCH_VERSATILE
181	181	bool "Versatile"
182	182	select ARM_AMBA
	183	+ select ARM_VIC
183	184	select ICST307
184	185	help
185	186	This enables support for ARM Ltd Versatile board.
1		-config ICST525
	1	+config ARM_GIC
2	2	bool
3	3
4		-config ARM_GIC
	4	+config ARM_VIC
	5	+ bool
	6	+
	7	+config ICST525
5	8	bool
6	9
7	10	config ICST307
...	...	@@ -4,6 +4,7 @@
4	4
5	5	obj-y += rtctime.o
6	6	obj-$(CONFIG_ARM_GIC) += gic.o
	7	+obj-$(CONFIG_ARM_VIC) += vic.o
7	8	obj-$(CONFIG_ICST525) += icst525.o
8	9	obj-$(CONFIG_ICST307) += icst307.o
9	10	obj-$(CONFIG_SA1111) += sa1111.o
	1	+/*
	2	+ * linux/arch/arm/common/vic.c
	3	+ *
	4	+ * Copyright (C) 1999 - 2003 ARM Limited
	5	+ * Copyright (C) 2000 Deep Blue Solutions Ltd
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or modify
	8	+ * it under the terms of the GNU General Public License as published by
	9	+ * the Free Software Foundation; either version 2 of the License, or
	10	+ * (at your option) any later version.
	11	+ *
	12	+ * This program is distributed in the hope that it will be useful,
	13	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+ * GNU General Public License for more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License
	18	+ * along with this program; if not, write to the Free Software
	19	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	+ */
	21	+#include <linux/init.h>
	22	+#include <linux/list.h>
	23	+
	24	+#include <asm/io.h>
	25	+#include <asm/irq.h>
	26	+#include <asm/mach/irq.h>
	27	+#include <asm/hardware/vic.h>
	28	+
	29	+static void __iomem *vic_base;
	30	+
	31	+static void vic_mask_irq(unsigned int irq)
	32	+{
	33	+ irq -= IRQ_VIC_START;
	34	+ writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR);
	35	+}
	36	+
	37	+static void vic_unmask_irq(unsigned int irq)
	38	+{
	39	+ irq -= IRQ_VIC_START;
	40	+ writel(1 << irq, vic_base + VIC_INT_ENABLE);
	41	+}
	42	+
	43	+static struct irqchip vic_chip = {
	44	+ .ack = vic_mask_irq,
	45	+ .mask = vic_mask_irq,
	46	+ .unmask = vic_unmask_irq,
	47	+};
	48	+
	49	+void __init vic_init(void __iomem *base, u32 vic_sources)
	50	+{
	51	+ unsigned int i;
	52	+
	53	+ vic_base = base;
	54	+
	55	+ /* Disable all interrupts initially. */
	56	+
	57	+ writel(0, vic_base + VIC_INT_SELECT);
	58	+ writel(0, vic_base + VIC_INT_ENABLE);
	59	+ writel(~0, vic_base + VIC_INT_ENABLE_CLEAR);
	60	+ writel(0, vic_base + VIC_IRQ_STATUS);
	61	+ writel(0, vic_base + VIC_ITCR);
	62	+ writel(~0, vic_base + VIC_INT_SOFT_CLEAR);
	63	+
	64	+ /*
	65	+ * Make sure we clear all existing interrupts
	66	+ */
	67	+ writel(0, vic_base + VIC_VECT_ADDR);
	68	+ for (i = 0; i < 19; i++) {
	69	+ unsigned int value;
	70	+
	71	+ value = readl(vic_base + VIC_VECT_ADDR);
	72	+ writel(value, vic_base + VIC_VECT_ADDR);
	73	+ }
	74	+
	75	+ for (i = 0; i < 16; i++) {
	76	+ void __iomem reg = vic_base + VIC_VECT_CNTL0 + (i 4);
	77	+ writel(VIC_VECT_CNTL_ENABLE \| i, reg);
	78	+ }
	79	+
	80	+ writel(32, vic_base + VIC_DEF_VECT_ADDR);
	81	+
	82	+ for (i = 0; i < 32; i++) {
	83	+ unsigned int irq = IRQ_VIC_START + i;
	84	+
	85	+ set_irq_chip(irq, &vic_chip);
	86	+
	87	+ if (vic_sources & (1 << i)) {
	88	+ set_irq_handler(irq, do_level_IRQ);
	89	+ set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	90	+ }
	91	+ }
	92	+}
...	...	@@ -35,6 +35,7 @@
35	35	#include <asm/leds.h>
36	36	#include <asm/hardware/arm_timer.h>
37	37	#include <asm/hardware/icst307.h>
	38	+#include <asm/hardware/vic.h>
38	39
39	40	#include <asm/mach/arch.h>
40	41	#include <asm/mach/flash.h>
...	...	@@ -56,24 +57,6 @@
56	57	#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
57	58	#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
58	59
59		-static void vic_mask_irq(unsigned int irq)
60		-{
61		- irq -= IRQ_VIC_START;
62		- writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
63		-}
64		-
65		-static void vic_unmask_irq(unsigned int irq)
66		-{
67		- irq -= IRQ_VIC_START;
68		- writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
69		-}
70		-
71		-static struct irqchip vic_chip = {
72		- .ack = vic_mask_irq,
73		- .mask = vic_mask_irq,
74		- .unmask = vic_unmask_irq,
75		-};
76		-
77	60	static void sic_mask_irq(unsigned int irq)
78	61	{
79	62	irq -= IRQ_SIC_START;
80	63
81	64
82	65
...	...	@@ -127,43 +110,12 @@
127	110
128	111	void __init versatile_init_irq(void)
129	112	{
130		- unsigned int i, value;
	113	+ unsigned int i;
131	114
132		- /* Disable all interrupts initially. */
	115	+ vic_init(VA_VIC_BASE, ~(1 << 31));
133	116
134		- writel(0, VA_VIC_BASE + VIC_INT_SELECT);
135		- writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
136		- writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
137		- writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
138		- writel(0, VA_VIC_BASE + VIC_ITCR);
139		- writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
140		-
141		- /*
142		- * Make sure we clear all existing interrupts
143		- */
144		- writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
145		- for (i = 0; i < 19; i++) {
146		- value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
147		- writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
148		- }
149		-
150		- for (i = 0; i < 16; i++) {
151		- value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
152		- writel(value \| VICVectCntl_Enable \| i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
153		- }
154		-
155		- writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
156		-
157		- for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
158		- if (i != IRQ_VICSOURCE31) {
159		- set_irq_chip(i, &vic_chip);
160		- set_irq_handler(i, do_level_IRQ);
161		- set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
162		- }
163		- }
164		-
165	117	set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
166		- vic_unmask_irq(IRQ_VICSOURCE31);
	118	+ enable_irq(IRQ_VICSOURCE31);
167	119
168	120	/* Do second interrupt controller */
169	121	writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
...	...	@@ -877,7 +829,7 @@
877	829	ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
878	830	do {
879	831	ticks1 = ticks2;
880		- status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
	832	+ status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
881	833	ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
882	834	} while (ticks2 > ticks1);
883	835
...	...	@@ -8,6 +8,7 @@
8	8	* warranty of any kind, whether express or implied.
9	9	*/
10	10	#include <asm/hardware.h>
	11	+#include <asm/hardware/vic.h>
11	12
12	13	.macro disable_fiq
13	14	.endm
...	...	@@ -293,27 +293,8 @@
293	293	* VERSATILE_SYS_IC
294	294	*
295	295	*/
296		-#define VIC_IRQ_STATUS 0
297		-#define VIC_FIQ_STATUS 0x04
298		-#define VIC_IRQ_RAW_STATUS 0x08
299		-#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */
300		-#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
301		-#define VIC_IRQ_ENABLE_CLEAR 0x14
302		-#define VIC_IRQ_SOFT 0x18
303		-#define VIC_IRQ_SOFT_CLEAR 0x1C
304		-#define VIC_PROTECT 0x20
305		-#define VIC_VECT_ADDR 0x30
306		-#define VIC_DEF_VECT_ADDR 0x34
307		-#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
308		-#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
309		-#define VIC_ITCR 0x300 /* VIC test control register */
	296	+/* VIC definitions in include/asm-arm/hardware/vic.h */
310	297
311		-#define VIC_FIQ_RAW_STATUS 0x08
312		-#define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
313		-#define VIC_FIQ_ENABLE_CLEAR 0x14
314		-#define VIC_FIQ_SOFT 0x18
315		-#define VIC_FIQ_SOFT_CLEAR 0x1C
316		-
317	298	#define SIC_IRQ_STATUS 0
318	299	#define SIC_IRQ_RAW_STATUS 0x04
319	300	#define SIC_IRQ_ENABLE 0x08
...	...	@@ -324,8 +305,6 @@
324	305	#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */
325	306	#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
326	307	#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
327		-
328		-#define VICVectCntl_Enable (1 << 5)
329	308
330	309	/* ------------------------------------------------------------------------
331	310	* Interrupts - bit assignment (primary)
	1	+/*
	2	+ * linux/include/asm-arm/hardware/vic.h
	3	+ *
	4	+ * Copyright (c) ARM Limited 2003. All rights reserved.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify
	7	+ * it under the terms of the GNU General Public License as published by
	8	+ * the Free Software Foundation; either version 2 of the License, or
	9	+ * (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	+ */
	20	+#ifndef __ASM_ARM_HARDWARE_VIC_H
	21	+#define __ASM_ARM_HARDWARE_VIC_H
	22	+
	23	+#define VIC_IRQ_STATUS 0x00
	24	+#define VIC_FIQ_STATUS 0x04
	25	+#define VIC_RAW_STATUS 0x08
	26	+#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
	27	+#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
	28	+#define VIC_INT_ENABLE_CLEAR 0x14
	29	+#define VIC_INT_SOFT 0x18
	30	+#define VIC_INT_SOFT_CLEAR 0x1c
	31	+#define VIC_PROTECT 0x20
	32	+#define VIC_VECT_ADDR 0x30
	33	+#define VIC_DEF_VECT_ADDR 0x34
	34	+
	35	+#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
	36	+#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
	37	+#define VIC_ITCR 0x300 /* VIC test control register */
	38	+
	39	+#define VIC_VECT_CNTL_ENABLE (1 << 5)
	40	+
	41	+#ifndef __ASSEMBLY__
	42	+void vic_init(void __iomem *base, u32 vic_sources);
	43	+#endif
	44	+
	45	+#endif