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Commit ffc493062ce9987156945aa21a677d83a179fc0a

Authored by Laxman Dewangan
Committed by Vinod Koul
1 parent f986ffedd7
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

dma: tegra: enable/disable dma clock 

Enable the DMA clock when allocating channel and
disable clock when freeing channels.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>

Showing 1 changed file with 17 additions and 1 deletions Side-by-side Diff

drivers/dma/tegra20-apb-dma.c
Diff comments   View file @ ffc4930
... ... @@ -1119,15 +1119,21 @@
1119 1119 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1120 1120 {
1121 1121 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  1122 + struct tegra_dma *tdma = tdc->tdma;
  1123 + int ret;
1122 1124  
1123 1125 dma_cookie_init(&tdc->dma_chan);
1124 1126 tdc->config_init = false;
1125   - return 0;
  1127 + ret = clk_prepare_enable(tdma->dma_clk);
  1128 + if (ret < 0)
  1129 + dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
  1130 + return ret;
1126 1131 }
1127 1132  
1128 1133 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1129 1134 {
1130 1135 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  1136 + struct tegra_dma *tdma = tdc->tdma;
1131 1137  
1132 1138 struct tegra_dma_desc *dma_desc;
1133 1139 struct tegra_dma_sg_req *sg_req;
... ... @@ -1163,6 +1169,7 @@
1163 1169 list_del(&sg_req->node);
1164 1170 kfree(sg_req);
1165 1171 }
  1172 + clk_disable_unprepare(tdma->dma_clk);
1166 1173 }
1167 1174  
1168 1175 /* Tegra20 specific DMA controller information */
... ... @@ -1255,6 +1262,13 @@
1255 1262 }
1256 1263 }
1257 1264  
  1265 + /* Enable clock before accessing registers */
  1266 + ret = clk_prepare_enable(tdma->dma_clk);
  1267 + if (ret < 0) {
  1268 + dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
  1269 + goto err_pm_disable;
  1270 + }
  1271 +
1258 1272 /* Reset DMA controller */
1259 1273 tegra_periph_reset_assert(tdma->dma_clk);
1260 1274 udelay(2);
... ... @@ -1264,6 +1278,8 @@
1264 1278 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1265 1279 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1266 1280 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
  1281 +
  1282 + clk_disable_unprepare(tdma->dma_clk);
1267 1283  
1268 1284 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1269 1285 for (i = 0; i < cdata->nr_channels; i++) {