08 Oct, 2013

2 commits

  • The order of arguments in the call to vco_set() for the ICST clocks appears to
    have been switched in error, which results in the VCO not being initialised
    correctly. This in turn stops the integrated LCD on things like Integrator/CP
    from working correctly.

    This patch fixes the order and restores the expected functionality.

    Reviewed-by: Linus Walleij
    Signed-off-by: Jonathan Austin
    Signed-off-by: Mike Turquette
    Cc: stable@vger.kernel.org

    Jonathan Austin
     
  • The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this,
    the SD driver was getting the incorrect clock value. This prevented the
    SD driver from initializing correctly.

    Signed-off-by: Dinh Nguyen
    CC: Arnd Bergmann
    CC: Olof Johansson
    Reviewed-by: Pavel Machek
    Cc: linux-arm-kernel@lists.infradead.org
    Signed-off-by: Mike Turquette

    Dinh Nguyen
     

07 Oct, 2013

1 commit

  • This patch fixes the tclk frequency array for the Armada-370 SoC.
    This bug has been introduced by commit 6b72333d
    ("clk: mvebu: add Armada 370 SoC-centric clock init").

    A wrong tclk frequency affects the following drivers: mvsdio, mvneta,
    i2c-mv64xxx and mvebu-devbus. This list may be incomplete.

    About the mvneta Ethernet driver, note that the tclk frequency is used
    to compute the Rx time coalescence. Then, this bug harms the coalescence
    configuration and also degrades the networking performances with the
    default values.

    Signed-off-by: Simon Guinot
    Cc: Andrew Lunn
    Cc: Gregory CLEMENT
    Cc: Sebastian Hesselbarth
    Acked-by: Jason Cooper
    Cc: stable@vger.kernel.org
    Signed-off-by: Michael Turquette

    Simon Guinot
     

02 Oct, 2013

1 commit

  • This fixes a regression for the Nomadik on the main system
    timers.

    The Nomadik seemed a bit slow and its heartbeat wasn't looking
    healthy. And it was not strange, because it has been connected
    to the 32768 Hz clock at boot, while being told by the clock driver
    that it was 2.4MHz. Actually connect the TIMCLK to 2.4MHz by
    default as this is what we want for nice scheduling, clocksource
    and clock event.

    Cc: stable@vger.kernel.org
    Signed-off-by: Linus Walleij
    Signed-off-by: Mike Turquette

    Linus Walleij
     

10 Sep, 2013

2 commits

  • Pull clock framework changes from Michael Turquette:
    "The common clk framework changes for 3.12 are dominated by clock
    driver patches, both new drivers and fixes to existing. A high
    percentage of these are for Samsung platforms like Exynos. Core
    framework fixes and some new features like automagical clock
    re-parenting round out the patches"

    * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
    clk: only call get_parent if there is one
    clk: samsung: exynos5250: Simplify registration of PLL rate tables
    clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
    clk: samsung: exynos4: Register PLL rate tables for Exynos4210
    clk: samsung: exynos4: Reorder registration of mout_vpllsrc
    clk: samsung: pll: Add support for rate configuration of PLL46xx
    clk: samsung: pll: Use new registration method for PLL46xx
    clk: samsung: pll: Add support for rate configuration of PLL45xx
    clk: samsung: pll: Use new registration method for PLL45xx
    clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
    clk: samsung: exynos4: Remove checks for DT node
    clk: samsung: exynos4: Remove unused static clkdev aliases
    clk: samsung: Modify _get_rate() helper to use __clk_lookup()
    clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
    clocksource: samsung_pwm_timer: Get clock from device tree
    ARM: dts: exynos4: Specify PWM clocks in PWM node
    pwm: samsung: Update DT bindings documentation to cover clocks
    clk: Move symbol export to proper location
    clk: fix new_parent dereference before null check
    clk: wm831x: Initialise wm831x pointer on init
    ...

    Linus Torvalds
     
  • In __clk_init(), after a clock is mostly initialized, a scan is done
    of the orphan clocks to see if the clock being registered is the
    parent of any of them.

    This code assumes that any clock that provides a get_parent method
    actually has at least one parent, and that's not a valid assumption.

    As a result, an orphan clock with no parent can return *something*
    as the parent index, and that value is blindly used to dereference
    the orphan's parent_names[] array (which will be ZERO_SIZE_PTR or
    NULL).

    Fix this by ensuring get_parent is only called for orphans with at
    least one parent.

    Signed-off-by: Alex Elder
    Signed-off-by: Mike Turquette

    Alex Elder
     

07 Sep, 2013

14 commits

  • Since the _get_rate() helper has been modified to use __clk_lookup()
    internally, checking of PLL input rates can be done using it and so the
    registration code can be simplified.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • This patch adds rate tables for PLLs that can be reconfigured at runtime
    for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
    input clock of 24 MHz and so are registered only in this case. MPLL does
    not need runtime reconfiguration and so table for it is not provided.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • This patch adds rate tables for PLLs that can be reconfigured at runtime
    for Exynos4210 SoCs. Provided tables contain PLL coefficients for
    input clock of 24 MHz and so are registered only in this case. MPLL does
    not need runtime reconfiguration and so table for it is not provided.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • Since PLL input frequency must be known before PLL registration,
    mout_vpllsrc clock which is a reference clock of VPLL must be registered
    before VPLL.

    This patch reorders clock registration to register mout_vpllsrc before
    VPLL.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • This patch implements round_rate and set_rate callbacks of PLL46xx
    driver to allow reconfiguration of PLL at runtime.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • This patch modifies PLL46xx support code and its users to use the
    recently introduced common PLL registration helper.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • This patch implements round_rate and set_rate callbacks of PLL45xx
    driver to allow reconfiguration of PLL at runtime.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • This patch modifies PLL45xx support code and its users to use the
    recently introduced common PLL registration helper.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • This array defines PLLs specific to Exynos 4x12 SoCs and not for all
    Exynos 4 SoCs, so the name should represent that.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • Exynos 4 supports only DT based bootup, so non-DT cases does not need to
    be handled anymore.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • Since Exynos does not support legacy non-DT boot anymore, most of clock
    lookups happen using device tree, so most of static clkdev aliases are no
    longer necessary. This patch removes them.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • There is no need to use clkdev inside the clock driver to retrieve the
    clocks for internal use. Instead __clk_lookup() helper can be used to
    look up clocks by their platform name.

    This patch modifies the behavior of _get_rate() helper to look up clocks
    by platform name and adjusts all users of it to pass platform names
    instead of clkdev aliases.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • Exynos cpufreq driver is the only remaining piece of code that needs
    static clkdev aliases for operation, because it can not do device tree
    based clock lookups yet.

    This patch moves clock alias definitions for those clocks to separate
    arrays that can be used with samsung_clk_register_alias() helper.

    Signed-off-by: Tomasz Figa
    Signed-off-by: Kyungmin Park
    Reviewed-by: Sylwester Nawrocki
    Signed-off-by: Mike Turquette

    Tomasz Figa
     
  • Pull ARM SoC platform changes from Olof Johansson:
    "This branch contains mostly additions and changes to platform
    enablement and SoC-level drivers. Since there's sometimes a
    dependency on device-tree changes, there's also a fair amount of
    those in this branch.

    Pieces worth mentioning are:

    - Mbus driver for Marvell platforms, allowing kernel configuration
    and resource allocation of on-chip peripherals.
    - Enablement of the mbus infrastructure from Marvell PCI-e drivers.
    - Preparation of MSI support for Marvell platforms.
    - Addition of new PCI-e host controller driver for Tegra platforms
    - Some churn caused by sharing of macro names between i.MX 6Q and 6DL
    platforms in the device tree sources and header files.
    - Various suspend/PM updates for Tegra, including LP1 support.
    - Versatile Express support for MCPM, part of big little support.
    - Allwinner platform support for A20 and A31 SoCs (dual and quad
    Cortex-A7)
    - OMAP2+ support for DRA7, a new Cortex-A15-based SoC.

    The code that touches other architectures are patches moving MSI
    arch-specific functions over to weak symbols and removal of
    ARCH_SUPPORTS_MSI, acked by PCI maintainers"

    * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)
    tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE
    PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource
    ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list
    ARM: dts: vf610-twr: enable i2c0 device
    ARM: dts: i.MX51: Add one more I2C2 pinmux entry
    ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
    ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
    ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
    ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
    ARM: dts: i.MX27: Disable AUDMUX in the template
    ARM: dts: wandboard: Add support for SDIO bcm4329
    ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
    ARM: dts: imx53-qsb: Make USBH1 functional
    ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
    ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
    ARM: dts: imx6qdl-sabresd: Add touchscreen support
    ARM: imx: add ocram clock for imx53
    ARM: dts: imx: ocram size is different between imx6q and imx6dl
    ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
    ARM: dts: i.MX27: Remove clock name from CPU node
    ...

    Linus Torvalds
     

04 Sep, 2013

1 commit

  • The __clk_get_flags() symbol is exported immediately following the
    clk_unprepare_unused_subtree() function. This is unusual, since a symbol
    export typically follows body of the function that it exports.

    Signed-off-by: Thierry Reding
    Signed-off-by: Mike Turquette

    Thierry Reding
     

31 Aug, 2013

2 commits

  • Commit 71472c0 (clk: add support for clock reparent on set_rate) added a
    dereference of the new_parent pointer in clk_reparent(), but as detected
    by smatch clk_reparent() later checks whether new_parent is NULL.

    The dereference was in order to clear the new parent's new_child pointer
    to avoid duplicate POST_RATE_CHANGE notifications, so clearly isn't
    necessary if the new parent is NULL, so move it inside the "if
    (new_parent)" block.

    Reported-by: Dan Carpenter
    Signed-off-by: James Hogan
    Signed-off-by: Mike Turquette

    James Hogan
     
  • Otherwise any attempt to interact with the hardware will crash. This is
    what happens when drivers get written blind.

    Signed-off-by: Mark Brown
    Cc: stable@vger.kernel.org
    Signed-off-by: Mike Turquette

    Mark Brown
     

30 Aug, 2013

6 commits


29 Aug, 2013

2 commits


28 Aug, 2013

9 commits