Doug / smarc-fsl-linux-kernel

15 Jul, 2013

1 commit

  • 8bd26e3a7   arm: delete __cpuinit/__CPUINIT usage from all ARM users ... Browse Code »

    The __cpuinit type of throwaway sections might have made sense
    some time ago when RAM was more constrained, but now the savings
    do not offset the cost and complications. For example, the fix in
    commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
    is a good example of the nasty type of bugs that can be created
    with improper use of the various __init prefixes.

    After a discussion on LKML[1] it was decided that cpuinit should go
    the way of devinit and be phased out. Once all the users are gone,
    we can then finally remove the macros themselves from linux/init.h.

    Note that some harmless section mismatch warnings may result, since
    notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
    and are flagged as __cpuinit -- so if we remove the __cpuinit from
    the arch specific callers, we will also get section mismatch warnings.
    As an intermediate step, we intend to turn the linux/init.h cpuinit
    related content into no-ops as early as possible, since that will get
    rid of these warnings. In any case, they are temporary and harmless.

    This removes all the ARM uses of the __cpuinit macros from C code,
    and all __CPUINIT from assembly code. It also had two ".previous"
    section statements that were paired off against __CPUINIT
    (aka .section ".cpuinit.text") that also get removed here.

    [1] https://lkml.org/lkml/2013/5/20/589

    Cc: Russell King
    Cc: Will Deacon
    Cc: linux-arm-kernel@lists.infradead.org
    Signed-off-by: Paul Gortmaker

    Paul Gortmaker
     

25 Sep, 2012

1 commit

  • 031bd879f   ARM: mm: implement LoUIS API for cache maintenance ops ... Browse Code »

    ARM v7 architecture introduced the concept of cache levels and related
    control registers. New processors like A7 and A15 embed an L2 unified cache
    controller that becomes part of the cache level hierarchy. Some operations in
    the kernel like cpu_suspend and __cpu_disable do not require a flush of the
    entire cache hierarchy to DRAM but just the cache levels belonging to the
    Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
    correspond to L1.

    The current cache flushing API used in cpu_suspend and __cpu_disable,
    flush_cache_all(), ends up flushing the whole cache hierarchy since for
    v7 it cleans and invalidates all cache levels up to Level of Coherency
    (LoC) which cripples system performance when used in hot paths like hotplug
    and cpuidle.

    Therefore a new kernel cache maintenance API must be added to cope with
    latest ARM system requirements.

    This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.

    This function cleans and invalidates all data cache levels up to the
    Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
    cache for processors that support it (> v7).

    This patch also creates an alias of the cache LoUIS function to flush_kern_all
    for all processor versions prior to v7, so that the current cache flushing
    behaviour is unchanged for those processors.

    v7 cache maintenance code implements a cache LoUIS function that cleans and
    invalidates the D-cache up to LoUIS and invalidates the I-cache, according
    to the new API.

    Reviewed-by: Santosh Shilimkar
    Reviewed-by: Nicolas Pitre
    Signed-off-by: Lorenzo Pieralisi
    Tested-by: Shawn Guo

    Lorenzo Pieralisi
     

02 May, 2012

1 commit

  • c5102f593   ARM: 7408/1: cacheflush: return error to userspace when flushing syscall fails ... Browse Code »

    The cacheflush syscall can fail for two reasons:

    (1) The arguments are invalid (nonsensical address range or no VMA)

    (2) The region generates a translation fault on a VIPT or PIPT cache

    This patch allows do_cache_op to return an error code to userspace in
    the case of the above. The various coherent_user_range implementations
    are modified to return 0 in the case of VIVT caches or -EFAULT in the
    case of an abort on v6/v7 cores.

    Reviewed-by: Catalin Marinas
    Signed-off-by: Will Deacon
    Signed-off-by: Russell King

    Will Deacon
     

06 Dec, 2011

1 commit

07 Jul, 2011

1 commit

23 Feb, 2011

1 commit

  • f6b0fa02e   ARM: pm: add generic CPU suspend/resume support ... Browse Code »

    This adds core support for saving and restoring CPU coprocessor
    registers for suspend/resume support. This contains support for suspend
    with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
    Tested on Assabet and Tegra 2.

    Tested-by: Colin Cross
    Tested-by: Kukjin Kim
    Signed-off-by: Russell King

    Russell King
     

28 Oct, 2010

1 commit

  • c8c90860c   ARM: 6466/1: implement flush_icache_all for the rest of the CPUs ... Browse Code »

    Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for
    CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
    flush_icache_all(). It also implemented this for v6 and v7 but not
    for v5 and backwards. Without the function pointer in place, we
    will be calling wrong cache functions.

    For example with ep93xx we get following:

    Unable to handle kernel paging request at virtual address ee070f38
    pgd = c0004000
    [ee070f38] *pgd=00000000
    Internal error: Oops: 80000005 [#1] PREEMPT
    last sysfs file:
    Modules linked in:
    CPU: 0 Not tainted (2.6.36+ #1)
    PC is at 0xee070f38
    LR is at __dma_alloc+0x11c/0x2d0
    pc : [] lr : [] psr: 60000013
    sp : c581bde0 ip : 00000000 fp : c0472000
    r10: c0472000 r9 : 000000d0 r8 : 00020000
    r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000
    r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000
    Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
    Control: c000717f Table: c0004000 DAC: 00000017
    Process swapper (pid: 1, stack limit = 0xc581a270)
    [] (__dma_alloc+0x11c/0x2d0)
    [] (dma_alloc_writecombine+0x1c/0x24)
    [] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
    [] (ep93xx_pcm_new+0x5c/0x88)
    [] (snd_soc_instantiate_cards+0x8a8/0xbc0)
    [] (soc_probe+0xfc/0x134)
    [] (platform_drv_probe+0x18/0x1c)
    [] (driver_probe_device+0xb0/0x16c)
    [] (bus_for_each_drv+0x48/0x84)
    [] (device_attach+0x50/0x68)
    [] (bus_probe_device+0x24/0x44)
    [] (device_add+0x2fc/0x44c)
    [] (platform_device_add+0x104/0x15c)
    [] (simone_init+0x60/0x94)
    [] (do_one_initcall+0xd0/0x1a4)

    __dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
    calling dmac_flush_range(). Now since the entries in the
    arm920_cache_fns are shifted by one, we jump into address 0xee070f38
    which is actually next instruction after the arm920_cache_fns
    structure.

    So implement flush_icache_all() for the rest of the supported CPUs
    using a generic 'invalidate I cache' instruction.

    Signed-off-by: Mika Westerberg
    Signed-off-by: Russell King

    Mika Westerberg
     

08 Oct, 2010

1 commit

27 Jul, 2010

1 commit

  • 9ca03a21e   ARM: Factor out common code from cpu_proc_fin() ... Browse Code »

    All implementations of cpu_proc_fin() start by disabling interrupts
    and then flush caches. Rather than have every processors proc_fin()
    implementation do this, move it out into generic code - and move the
    cache flush past setup_mm_for_reboot() (so it can benefit from having
    caches still enabled.)

    This allows cpu_proc_fin() to become independent of the L1/L2 cache
    types, and eventually move the L2 cache flushing into the L2 support
    code.

    Signed-off-by: Russell King

    Russell King
     

15 Feb, 2010

2 commits

14 Dec, 2009

1 commit

03 Oct, 2009

1 commit

  • 4fb284743   ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() ... Browse Code »

    Instruction fault status register, IFSR, was introduced on ARMv6 to
    provide status information about the last insturction fault. It
    needed for proper prefetch abort handling.

    Now we have three prefetch abort model:

    * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
    * ARMv6 - provides IFSR, but not IFAR;
    * ARMv7 - provides both IFSR and IFAR.

    Signed-off-by: Kirill A. Shutemov
    Signed-off-by: Russell King

    Kirill A. Shutemov
     

01 Oct, 2008

1 commit

13 Aug, 2008

1 commit

18 May, 2008

1 commit

24 Apr, 2008

1 commit

  • 4a1fd556c   [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f ... Browse Code »

    The proc-*.S files have the _prefetch_abort pointer placed at the end
    of the processor structure but the cpu-multi32.h defines it in the
    second position. The patch also fixes the support for XSC3 and the
    MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

    Signed-off-by: Catalin Marinas
    Signed-off-by: Russell King

    Catalin Marinas
     

30 Nov, 2006

1 commit

29 Sep, 2006

1 commit

  • 0f45d7f36   [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores. ... Browse Code »

    There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a
    dummy abort handler which returns zero for the base restored Data Abort
    model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up
    for the base updated Data Abort model cores.

    Signed-off-by: Hyok S. Choi
    Signed-off-by: Russell King

    Hyok S. Choi
     

28 Sep, 2006

1 commit