13 Apr, 2013
2 commits
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The composite clock assumes that any clock implementing the .recalc_rate
callback will also implement .round_rate and .set_rate. This is not
always true; the basic fixed-rate clock will only implement .recalc_rate
and a fixed-divider clock may choose to implement .recalc_rate and
.round_rate but not .set_rate.Fix this by conditionally registering .round_rate and .set_rate
callbacks based on the rate_ops passed in to clk_composite_register.Signed-off-by: Mike Turquette
Cc: Prashant Gaikwad
Tested-by: Emilio López
Cc: Gregory CLEMENT -
Rename all div_hw and div_ops related variables and functions to use
rate_hw, rate_ops, etc. This is to make the rate-change portion of the
composite clk implementation more generic. A patch following this one
will allow for fixed-rate clocks to reuse this infrastructure.Signed-off-by: Mike Turquette
Reviewed-by: Prashant Gaikwad
Tested-by: Emilio López
Cc: Gregory CLEMENT
27 Mar, 2013
1 commit
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Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.Signed-off-by: Prashant Gaikwad
Signed-off-by: Mike Turquette
