22 Nov, 2012

1 commit

  • Flag CLK_SET_RATE_PARENT is required for a clock, where we want to
    propagate clk_set_rate to its parent. This patch adds this to multiple clocks.

    Signed-off-by: Vipul Kumar Samar
    Signed-off-by: Shiraz Hashim
    Signed-off-by: Rajeev Kumar
    Signed-off-by: Vijay Kumar Mishra
    Signed-off-by: Vijay Kumar Mishra
    Signed-off-by: Viresh Kumar
    Signed-off-by: Mike Turquette

    Vipul Kumar Samar
     

21 Jun, 2012

1 commit

  • viresh.kumar@st.com email-id doesn't exist anymore as I have left the
    company. Replace ST's id with viresh.linux@gmail.com.

    It also updates .mailmap file to fix address for 'git shortlog'

    Signed-off-by: Viresh Kumar
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Viresh Kumar
     

13 May, 2012

1 commit

  • All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
    values of eq, x and y.

    Fout from synthesizer can be given from two equations:
    Fout1 = (Fin * X/Y)/2 EQ1
    Fout2 = Fin * X/Y EQ2

    This patch adds in support for this type of clock.

    Signed-off-by: Viresh Kumar
    Reviewed-by: Mike Turquette

    Viresh Kumar