17 Apr, 2013

2 commits


16 Apr, 2013

5 commits


29 Jan, 2013

1 commit

  • Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
    manually, which is fully taken care of by the hardware. This needs
    some special awareness into existing interrupr injection path:

    - for pending interrupt, instead of direct injection, we may need
    update architecture specific indicators before resuming to guest.

    - A pending interrupt, which is masked by ISR, should be also
    considered in above update action, since hardware will decide
    when to inject it at right time. Current has_interrupt and
    get_interrupt only returns a valid vector from injection p.o.v.

    Reviewed-by: Marcelo Tosatti
    Signed-off-by: Kevin Tian
    Signed-off-by: Yang Zhang
    Signed-off-by: Gleb Natapov

    Yang Zhang
     

21 Jul, 2012

1 commit

  • When more than 1 source id is in use for the same GSI, we have the
    following race related to handling irq_states race:

    CPU 0 clears bit 0. CPU 0 read irq_state as 0. CPU 1 sets level to 1.
    CPU 1 calls kvm_ioapic_set_irq(1). CPU 0 calls kvm_ioapic_set_irq(0).
    Now ioapic thinks the level is 0 but irq_state is not 0.

    Fix by performing all irq_states bitmap handling under pic/ioapic lock.
    This also removes the need for atomics with irq_states handling.

    Reported-by: Gleb Natapov
    Signed-off-by: Michael S. Tsirkin
    Signed-off-by: Marcelo Tosatti

    Michael S. Tsirkin
     

17 Apr, 2012

1 commit

  • Intel spec says that TMR needs to be set/cleared
    when IRR is set, but kvm also clears it on EOI.

    I did some tests on a real (AMD based) system,
    and I see same TMR values both before
    and after EOI, so I think it's a minor bug in kvm.

    This patch fixes TMR to be set/cleared on IRR set
    only as per spec.

    And now that we don't clear TMR, we can save
    an atomic read of TMR on EOI that's not propagated
    to ioapic, by checking whether ioapic needs
    a specific vector first and calculating
    the mode afterwards.

    Signed-off-by: Michael S. Tsirkin
    Signed-off-by: Marcelo Tosatti

    Michael S. Tsirkin
     

13 May, 2010

1 commit


01 Mar, 2010

2 commits

  • If we fail to init ioapic device or the fail to setup the default irq
    routing, the device register by kvm_create_pic() and kvm_ioapic_init()
    remain unregister. This patch fixed to do this.

    Signed-off-by: Wei Yongjun
    Signed-off-by: Avi Kivity

    Wei Yongjun
     
  • When the guest acknowledges an interrupt, it sends an EOI message to the local
    apic, which broadcasts it to the ioapic. To handle the EOI, we need to take
    the ioapic mutex.

    On large guests, this causes a lot of contention on this mutex. Since large
    guests usually don't route interrupts via the ioapic (they use msi instead),
    this is completely unnecessary.

    Avoid taking the mutex by introducing a handled_vectors bitmap. Before taking
    the mutex, check if the ioapic was actually responsible for the acked vector.
    If not, we can return early.

    Signed-off-by: Avi Kivity
    Signed-off-by: Marcelo Tosatti

    Avi Kivity
     

03 Dec, 2009

2 commits


10 Jun, 2009

8 commits


24 Mar, 2009

1 commit

  • IRQ injection status is either -1 (if there was no CPU found
    that should except the interrupt because IRQ was masked or
    ioapic was misconfigured or ...) or >= 0 in that case the
    number indicates to how many CPUs interrupt was injected.
    If the value is 0 it means that the interrupt was coalesced
    and probably should be reinjected.

    Signed-off-by: Gleb Natapov
    Signed-off-by: Avi Kivity

    Gleb Natapov
     

31 Dec, 2008

1 commit


15 Oct, 2008

2 commits

  • Moving irqchip_in_kernel() from ioapic.h to irq.h.

    Signed-off-by: Xiantao Zhang
    Signed-off-by: Avi Kivity

    Xiantao Zhang
     
  • Based on a patch from: Ben-Ami Yassour
    which was based on a patch from: Amit Shah

    Notify IRQ acking on PIC/APIC emulation. The previous patch missed two things:

    - Edge triggered interrupts on IOAPIC
    - PIC reset with IRR/ISR set should be equivalent to ack (LAPIC probably
    needs something similar).

    Signed-off-by: Marcelo Tosatti
    CC: Amit Shah
    CC: Ben-Ami Yassour
    Signed-off-by: Avi Kivity

    Marcelo Tosatti
     

31 Jan, 2008

1 commit