27 Jul, 2011
3 commits
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After changing all consumers of atomics to include , we
ran into some compile time errors due to this dependency chain:linux/atomic.h
-> asm/atomic.h
-> asm-generic/atomic-long.hwhere atomic-long.h could use funcs defined later in linux/atomic.h
without a prototype. This patches moves the code that includes
asm-generic/atomic*.h to linux/atomic.h.Archs that need need to select
CONFIG_GENERIC_ATOMIC64 from now on (some of them used to include it
unconditionally).Compile tested on i386 and x86_64 with allnoconfig.
Signed-off-by: Arun Sharma
Cc: Eric Dumazet
Cc: Ingo Molnar
Cc: David Miller
Acked-by: Mike Frysinger
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This is in preparation for more generic atomic primitives based on
__atomic_add_unless.Signed-off-by: Arun Sharma
Signed-off-by: Hans-Christian Egtvedt
Reviewed-by: Eric Dumazet
Cc: Ingo Molnar
Cc: David Miller
Acked-by: Mike Frysinger
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This allows us to move duplicated code in
(atomic_inc_not_zero() for now) toSigned-off-by: Arun Sharma
Reviewed-by: Eric Dumazet
Cc: Ingo Molnar
Cc: David Miller
Cc: Eric Dumazet
Acked-by: Mike Frysinger
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
09 Jul, 2010
2 commits
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Currently, the 32-bit and 64-bit atomic operations on ARM do not
include memory constraints in the inline assembly blocks. In the
case of barrier-less operations [for example, atomic_add], this
means that the compiler may constant fold values which have actually
been modified by a call to an atomic operation.This issue can be observed in the atomic64_test routine in
/lib/atomic64_test.c:00000000 :
0: e1a0c00d mov ip, sp
4: e92dd830 push {r4, r5, fp, ip, lr, pc}
8: e24cb004 sub fp, ip, #4
c: e24dd008 sub sp, sp, #8
10: e24b3014 sub r3, fp, #20
14: e30d000d movw r0, #53261 ; 0xd00d
18: e3011337 movw r1, #4919 ; 0x1337
1c: e34c0001 movt r0, #49153 ; 0xc001
20: e34a1aa3 movt r1, #43683 ; 0xaaa3
24: e16300f8 strd r0, [r3, #-8]!
28: e30c0afe movw r0, #51966 ; 0xcafe
2c: e30b1eef movw r1, #48879 ; 0xbeef
30: e34d0eaf movt r0, #57007 ; 0xdeaf
34: e34d1ead movt r1, #57005 ; 0xdead
38: e1b34f9f ldrexd r4, [r3]
3c: e1a34f90 strexd r4, r0, [r3]
40: e3340000 teq r4, #0
44: 1afffffb bne 38
48: e59f0004 ldr r0, [pc, #4] ; 54
4c: e3a0101e mov r1, #30
50: ebfffffe bl 0
54: 00000000 .word 0x00000000The atomic64_set (0x38-0x44) writes to the atomic64_t, but the
compiler doesn't see this, assumes the test condition is always
false and generates an unconditional branch to __bug. The rest of the
test is optimised away.This patch adds suitable memory constraints to the atomic operations on ARM
to ensure that the compiler is informed of the correct data hazards. We have
to use the "Qo" constraints to avoid hitting the GCC anomaly described at
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44492 , where the compiler
makes assumptions about the writeback in the addressing mode used by the
inline assembly. These constraints forbid the use of auto{inc,dec} addressing
modes, so it doesn't matter if we don't use the operand exactly once.Cc: stable@kernel.org
Reviewed-by: Nicolas Pitre
Signed-off-by: Will Deacon
Signed-off-by: Russell King -
The atomic64_add_unless function compares an atomic variable with
a given value and, if they are not equal, adds another given value
to the atomic variable. The function returns zero if the addition
did not occur and non-zero otherwise.On ARM, the return value is initialised to 1 in C code. Inline assembly
code then performs the atomic64_add_unless operation, setting the
return value to 0 iff the addition does not occur. This means that
when the addition *does* occur, the value of ret must be preserved
across the inline assembly and therefore requires a "+r" constraint
rather than the current one of "=&r".Thanks to Nicolas Pitre for helping to spot this.
Cc: stable@kernel.org
Reviewed-by: Nicolas Pitre
Signed-off-by: Will Deacon
Signed-off-by: Russell King
17 May, 2010
1 commit
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In preparation for removing volatile from the atomic_t definition, this
patch adds a volatile cast to all the atomic read functions.Signed-off-by: Anton Blanchard
Signed-off-by: Linus Torvalds
16 Feb, 2010
1 commit
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In preparation for perf-events support, ARM needs to support atomic64_t
operations. v6k and above support the ldrexd and strexd instructions to
do just that.This patch adds atomic64 support to the ARM architecture. v6k and above
make use of new instructions whilst older cores fall back on the generic
solution using spinlocks. If and when v7-M cores are supported by Linux,
they will need to fall back on the spinlock implementation too.Signed-off-by: Will Deacon
Acked-by: Catalin Marinas
Signed-off-by: Russell King
19 Sep, 2009
1 commit
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The patch adds a CLREX or dummy STREX to the exception return path. This
is needed because several atomic/locking operations use a pair of
LDREX/STREXEQ and the EQ condition may not always be satisfied. This
would leave the exclusive monitor status set and may cause problems with
atomic/locking operations in the interrupted code.With this patch, the atomic_set() operation can be a simple STR
instruction (on SMP systems, the global exclusive monitor is cleared by
STR anyway). Clearing the exclusive monitor during context switch is no
longer needed as this is handled by the exception return path anyway.Signed-off-by: Catalin Marinas
Reported-by: Jamie Lokier
26 Jul, 2009
1 commit
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fix the following 'make includecheck' warning:
arch/arm/include/asm/atomic.h: asm/system.h is included more than once.
Signed-off-by: Jaswinder Singh Rajput
Signed-off-by: Russell King
12 Jun, 2009
1 commit
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The existing asm-generic/atomic.h only defines the
atomic_long type. This renames it to atomic-long.h
so we have a place to add a truly generic atomic.h
that can be used on all non-SMP systems.Signed-off-by: Remis Lima Baima
Signed-off-by: Arnd Bergmann
Acked-by: Ingo Molnar
29 May, 2009
1 commit
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Mathieu Desnoyers pointed out that the ARM barriers were lacking:
- cmpxchg, xchg and atomic add return need memory barriers on
architectures which can reorder the relative order in which memory
read/writes can be seen between CPUs, which seems to include recent
ARM architectures. Those barriers are currently missing on ARM.- test_and_xxx_bit were missing SMP barriers.
So put these barriers in. Provide separate atomic_add/atomic_sub
operations which do not require barriers.Reported-Reviewed-and-Acked-by: Mathieu Desnoyers
Signed-off-by: Russell King
07 Jan, 2009
1 commit
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The atomic_t type cannot currently be used in some header files because it
would create an include loop with asm/atomic.h. Move the type definition
to linux/types.h to break the loop.Signed-off-by: Matthew Wilcox
Cc: Huang Ying
Cc:
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
03 Aug, 2008
1 commit
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Move platform independent header files to arch/arm/include/asm, leaving
those in asm/arch* and asm/plat* alone.Signed-off-by: Russell King