13 Mar, 2010
1 commit
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With a 64-bit wide data bus only the lowest 8-bits of the ECC syndrome are
relevant. With a 32-bit wide data bus only the lowest 16-bits are
relevant on most architectures.Without this change, the ECC syndrome displayed can be mildly confusing,
eg:EDAC MPC85xx MC1: syndrome: 0x25252525
When in reality the ECC syndrome is 0x25.
A variety of Freescale manuals say a variety of different things about how
to decode the CAPTURE_ECC (syndrome) register. I don't have a system with
a 32-bit bus to test on, but I believe the change is correct. It'd be
good to get an ACK from someone at Freescale about this change though.Signed-off-by: Peter Tyser
Signed-off-by: Doug Thompson
Cc: Kumar Gala
Cc: Dave Jiang
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
01 Jul, 2009
1 commit
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Since some new MPC85xx SOCs support DDR3 memory now, so add DDR3 memory
type for MPC85xx EDAC.Signed-off-by: Yang Shi
Cc: Doug Thompson
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
08 Feb, 2008
1 commit
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EDAC chip driver support for Freescale MPC85xx platforms. PPC based.
Signed-off-by: Dave Jiang
Cc: Alan Cox
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds