10 Jul, 2012
16 commits
-
* pci/bjorn-p2p-bridge-windows:
sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases()
PCI: support sizing P2P bridge I/O windows with 1K granularity
PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)
PCI: allow P2P bridge windows starting at PCI bus address zeroConflicts:
drivers/pci/probe.c
include/linux/pci.h -
The generic code to read P2P bridge windows is functionally equivalent
to the sparc-specific pci_cfg_fake_ranges(), so use the generic code.The "if (!res->start) res->start = ..." removed from the I/O window code
here was an artifact of the Intel 1K window support from 9d265124d051 and
is no longer necessary (it probably was just cloned from x86 and was never
useful on sparc).Acked-by: David S. Miller
Signed-off-by: Bjorn Helgaas -
* pci/bjorn-disable-decode:
PCI: disable MEM decoding while updating 64-bit MEM BARs
PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too -
* pci/myron-final-fixups-v2:
PCI: call final fixups hot-added devices
PCI: move final fixups from __init to __devinit
x86/PCI: move final fixups from __init to __devinit
MIPS/PCI: move final fixups from __init to __devinit
PCI: never discard enable/suspend/resume_early/resume fixups
PCI: release temporary reference in __nv_msi_ht_cap_quirk()
PCI: restructure 'pci_do_fixups()' -
Final fixups are currently applied only at boot-time by
pci_apply_final_quirks(), which is an fs_initcall(). Hot-added devices
don't get these fixups, so they may not be completely initialized.This patch makes us run final fixups for hot-added devices in
pci_bus_add_device() just before the new device becomes eligible for driver
binding.This patch keeps the fs_initcall() for devices present at boot because we
do resource assignment between pci_bus_add_device and the fs_initcall(),
and we don't want to break any fixups that depend on that assignment. This
is a design issue that may be addressed in the future -- any resource
assignment should be done *before* device_add().[bhelgaas: changelog]
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Final fixups are executed during device enumeration. If we support
hotplug, this may be after boot, so final fixups cannot be __init.[bhelgaas: changelog]
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Final fixups are executed during device enumeration. If we support
hotplug, this may be after boot, so final fixups cannot be __init.[bhelgaas: changelog]
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Final fixups are executed during device enumeration. If we support
hotplug, this may be after boot, so final fixups cannot be __init.[bhelgaas: changelog]
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Some bridges support I/O windows with 1K alignment, not just the 4K
alignment defined by the PCI spec. For example, see the IOBL_ADR register
and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2).This patch adds support for sizing the window in 1K increments based
on the requirements of downstream devices.[bhelgaas: changelog, comment]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
9d265124d051 and 15a260d53f7c added quirks for P2P bridges that support
I/O windows that start/end at 1K boundaries, not just the 4K boundaries
defined by the PCI spec. For details, see the IOBL_ADR register and the
EN1K bit in the CNF register in the Intel 82870P2 (P64H2).These quirks complicate the code that reads P2P bridge windows
(pci_read_bridge_io() and pci_cfg_fake_ranges()) because the bridge
I/O resource is updated in the HEADER quirk, in pci_read_bridge_io(),
in pci_setup_bridge(), and again in the FINAL quirk. This is confusing
and makes it impossible to reassign the bridge windows after FINAL
quirks are run.This patch adds support for 1K windows in the generic paths, so the
HEADER quirk only has to enable this support. The FINAL quirk, which
used to undo damage done by pci_setup_bridge(), is no longer needed.This removes "if (!res->start) res->start = ..." from pci_read_bridge_io();
that was part of 9d265124d051 to avoid overwriting the resource filled in
by the quirk. Since pci_read_bridge_io() itself now knows about
granularity, the quirk no longer updates the resource and this test is no
longer needed.Signed-off-by: Bjorn Helgaas
-
When we update 64-bit BARs, we have to perform two config writes. Between
the writes, the half-written BAR value could match a MEM access intended
for another device. This could result in corruption of this device (for
writes) or an unexpected response machine check (for reads).To prevent this, disable MEM decoding while updating such BARs. This uses
the same safety test as 253d2e5498, which disables both MEM and IO while
sizing BARs, namely, we don't disable decoding for host bridge devices.Signed-off-by: Bjorn Helgaas
-
After 253d2e5498, we disable MEM and IO decoding for most devices while we
size 32-bit BARs. However, we restore the original COMMAND register before
we size the upper 32 bits of 64-bit BARs, so we can still cause a conflict.This patch waits to restore the original COMMAND register until we're
completely finished sizing the BAR.Reference: https://lkml.org/lkml/2007/8/25/154
Acked-by: Jacob Pan
Signed-off-by: Bjorn Helgaas -
The enable/suspend/resume_early/resume fixups can be called at any time, so
they can't be __init or __devinit.[bhelgaas: changelog]
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
__nv_msi_ht_cap_quirk() acquires a temporary reference via
'pci_get_bus_and_slot()' that is never released.This patch releases the temporary reference.
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
This patch restructures pci_do_fixups()'s quirk invocations in the style
of initcall_debug_start() and initcall_debug_report(), so we have only
one call site for the quirk.[bhelgaas: changelog]
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
cd81e1ea1a4c added checks that prevent us from using P2P bridge windows
that start at PCI bus address zero. The reason was to "prevent us from
overwriting resources that are unassigned."But generic code should allow address zero in both BARs and bridge
windows, so I think that commit was a mistake.Windows at bus address zero are legal and likely to exist on machines with
an offset between bus addresses and CPU addresses. For example, in the
following hypothetical scenario, the bridge at 00:01.0 has a window at bus
address zero and the device at 01:00.0 has a BAR at bus address zero, and
I think both are perfectly valid:PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x100000000-0x1ffffffff] (bus address [0x00000000-0xffffffff])
pci 0000:00:01.0: PCI bridge to [bus 01]
pci 0000:00:01.0: bridge window [mem 0x100000000-0x100ffffff]
pci 0000:01:00.0: reg 10: [mem 0x100000000-0x100ffffff]Acked-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
06 Jul, 2012
17 commits
-
* pci/rafael-pci_set_power_state-rebase:
PCI / PM: restore the original behavior of pci_set_power_state() -
* pci/myron-pcibios_setup:
xtensa/PCI: factor out pcibios_setup()
x86/PCI: adjust section annotations for pcibios_setup()
unicore32/PCI: adjust section annotations for pcibios_setup()
tile/PCI: factor out pcibios_setup()
sparc/PCI: factor out pcibios_setup()
sh/PCI: adjust section annotations for pcibios_setup()
sh/PCI: factor out pcibios_setup()
powerpc/PCI: factor out pcibios_setup()
parisc/PCI: factor out pcibios_setup()
MIPS/PCI: adjust section annotations for pcibios_setup()
MIPS/PCI: factor out pcibios_setup()
microblaze/PCI: factor out pcibios_setup()
ia64/PCI: factor out pcibios_setup()
cris/PCI: factor out pcibios_setup()
alpha/PCI: factor out pcibios_setup()
PCI: pull pcibios_setup() up into core -
Commit cc2893b6 (PCI: Ensure we re-enable devices on resume)
addressed the problem with USB not being powered after resume on
recent Lenovo machines, but it did that in a suboptimal way.
Namely, it should have changed the relevant code paths only,
which are pci_pm_resume_noirq() and pci_pm_restore_noirq() supposed
to restore the device's power and standard configuration registers
after system resume from suspend or hibernation. Instead, however,
it modified pci_set_power_state() which is executed in several
other situations too. That resulted in some undesirable effects,
like attempting to change a device's power state in the same way
multiple times in a row (up to as many as 4 times in a row in the
snd_hda_intel driver).Fix the bug addressed by commit cc2893b6 in an alternative way,
by forcibly powering up all devices in pci_pm_default_resume_early(),
which is called by pci_pm_resume_noirq() and pci_pm_restore_noirq()
to restore the device's power and standard configuration registers,
and modifying pci_pm_runtime_resume() to avoid the forcible power-up
if not necessary. Then, revert the changes made by commit cc2893b6
to make the confusion introduced by it go away.Acked-by: Matthew Garrett
Signed-off-by: Rafael J. Wysocki
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Make pcibios_setup() consistently use the "__init" section annotation.
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Make pcibios_setup() consistently use the "__init" section annotation.
Acked-by: Guan Xuetao
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Acked-by: Chris Metcalf
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Acked-by: David S. Miller
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Make pcibios_setup() consistently use the "__init" section annotation.
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Tested-by: Nobuhiro Iwamatsu
Acked-by: Paul Mundt
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Acked-by: Benjamin Herrenschmidt
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Make pcibios_setup() consistently use the "__init" section annotation.
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Acked-by: Michal Simek
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Acked-by: Tony Luck
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.This patch fixes what looks like a bug in cris, which implements
pcibios_setup() such that pci_setup() doesn't look for any generic
options.Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas
26 Jun, 2012
2 commits
-
The PCI core provides a generic pcibios_setup() routine. Drop this
architecture-specific version in favor of that.Acked-by: Richard Henderson
Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas -
Currently, all of the architectures implement their own pcibios_setup()
routine. Most of the implementations do nothing so this patch introduces
a generic (__weak) routine in the core that can be used by all
architectures as a default. If necessary, it can be overridden by
architecture-specific code.Signed-off-by: Myron Stowe
Signed-off-by: Bjorn Helgaas
24 Jun, 2012
5 commits
-
* topic/huang-d3cold-v7:
PCI/PM: add PCIe runtime D3cold support
PCI: do not call pci_set_power_state with PCI_D3cold
PCI/PM: add runtime PM support to PCIe port
ACPI/PM: specify lowest allowed state for device sleep state -
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.For more information about PCIe D3cold and corresponding ACPI support,
please refer to:- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki
Originally-by: Zheng Yan
Signed-off-by: Huang Ying
Signed-off-by: Bjorn Helgaas -
PCI subsystem has not been ready for D3cold support yet. So
PCI_D3cold should not be used as parameter for pci_set_power_state.
This patch is needed for upcoming PCI_D3cold support.This patch has no functionality change, because pci_set_power_state
will bound the parameter to PCI_D3hot too.CC: Michal Miroslaw
CC: Jesse Barnes
Reviewed-by: Rafael J. Wysocki
Signed-off-by: Huang Ying
Signed-off-by: Bjorn Helgaas -
This patch adds runtime PM support to PCIe port. This is needed by
PCIe D3cold support, where PCIe device without ACPI node may be
powered on/off by PCIe port.Because runtime suspend is broken for some chipsets, a black list is
used to disable runtime PM support for these chipsets.Reviewed-by: Rafael J. Wysocki
Signed-off-by: Zheng Yan
Signed-off-by: Huang Ying
Signed-off-by: Bjorn Helgaas -
Lower device sleep state can save more power, but has more exit
latency too. Sometimes, to satisfy some power QoS and other
requirement, we need to constrain the lowest device sleep state.In this patch, a parameter to specify lowest allowed state for
acpi_pm_device_sleep_state is added. So that the caller can enforce
the constraint via the parameter.This is needed by PCIe D3cold support, where the lowest power state
allowed may be D3_HOT instead of default D3_COLD.CC: Len Brown
CC: linux-acpi@vger.kernel.org
Reviewed-by: Rafael J. Wysocki
Signed-off-by: Huang Ying
Signed-off-by: Bjorn Helgaas
