14 Jul, 2012

5 commits

  • Some architectures supports only 16-bit or 32-bit read/write access to
    their IO space. Add a 'reg-io-width' platform and OF parameter which
    specifies the IO width to support these platforms.

    reg-io-width can be specified as 1, 2 or 4, and has a default value
    of 1 if it is unspecified.

    Signed-off-by: Ganesan Ramalingam
    Signed-off-by: Jayachandran C
    Signed-off-by: Wolfram Sang

    Ganesan Ramalingam
     
  • Update for change in i2c-ocores.h which uses reg_shift to
    specify the register offset shifts instead of regstep.

    Signed-off-by: Jayachandran C
    Acked-by: Richard Rojfors
    Signed-off-by: Wolfram Sang

    Jayachandran C
     
  • Deprecate 'regstep' property and use the standard 'reg-shift' property
    for register offset shifts. 'regstep' will still be supported as an
    optional property, but will give a warning when used.

    Signed-off-by: Ganesan Ramalingam
    Signed-off-by: Jayachandran C
    Signed-off-by: Wolfram Sang

    Ganesan Ramalingam
     
  • Cleanups to i2c-cores, no change in logic, changes are:
    * Move i2c-ocores device tree documentation from source file to
    Documentation/devicetree/bindings/i2c/i2c-ocores.txt.
    * Add \n to dev_warn and dev_err messages where missing
    * Minor updates to the text and formatting fixes.

    Signed-off-by: Jayachandran C
    Signed-off-by: Wolfram Sang

    Jayachandran C
     
  • As git history indicates, the driver predates the git era and is heavily
    used and worked on since. Not EXPERIMENTAL anymore.

    Signed-off-by: Wolfram Sang
    Cc: Rodolfo Giometti
    Cc: Florian Fainelli

    Wolfram Sang
     

13 Jul, 2012

11 commits

  • There's no point in using _sync() as we don't really care if the suspend
    has completed immediately.

    Signed-off-by: Mark Brown
    Reviewed-by: Shubhrajyoti D
    Signed-off-by: Wolfram Sang

    Mark Brown
     
  • This commit fixes warning introduced in 27452498a ("i2c-s3c2410: Rework
    device type handling"):

    drivers/i2c/busses/i2c-s3c2410.c: In function 's3c24xx_get_device_quirks':
    drivers/i2c/busses/i2c-s3c2410.c:125: warning: passing argument 1 of 'of_match_node' from incompatible pointer type
    include/linux/of.h:245: note: expected 'const struct of_device_id *' but argument is of type 'const struct of_device_id (*)[4]'

    Signed-off-by: Karol Lewandowski
    Signed-off-by: Kyungmin Park
    Signed-off-by: Wolfram Sang

    Karol Lewandowski
     
  • This patch configures the I2C bus timing registers according
    to information passed via DT. Currently, 100kHz and 400kHz
    modes are supported.

    The TIMING2 register value is wrong in the documentation for
    i.MX28! This was found and fixed by:
    Shawn Guo

    Signed-off-by: Marek Vasut
    Signed-off-by: Wolfram Sang

    Marek Vasut
     
  • Depend on 1e92bf6d80b5a0a137455c96bf6cdd9c1a5b531e

    Signed-off-by: Sonic Zhang
    Signed-off-by: Wolfram Sang

    Sonic Zhang
     
  • Depend on commit cf93feb3a0dee97c7896016a352a3226139fbcf4

    Signed-off-by: Sonic Zhang
    Signed-off-by: Wolfram Sang

    Sonic Zhang
     
  • TWI bit mask macros are moved to twi head file.
    Depend on commit 61c16b5c7414b6d0511dc384e0ea994e250e6339

    Signed-off-by: Sonic Zhang
    Signed-off-by: Bob Liu
    Signed-off-by: Wolfram Sang

    Sonic Zhang
     
  • Current driver was developed based on BF537 0.2 HRM. In high system load, BUFRDERR error
    interrupt may be raised if XMTSERV interrupt of last TX byte is not served in time
    (set RSTART bit), which breaks restart tranfer as expected.

    "Buffer Read Error (BUFRDERR)" description in Blackfin HRM only applys to BF537
    rev. < 0.3. In later rev. and later announced Blackfin chips, such as BF527 and
    BF548, a new TWI master feature "Clock Stretching" is added into the TWI controller,
    BUFRDERR interrupt is not triggered after TX FIFO is empty.

    This patch sets RSTART bit at the beginning of the first transfer. The SCL and SDA
    is hold till XMTSERV interrupt of last TX byte is served. Restart transfer is not broken
    in high system load.

    Signed-off-by: Sonic Zhang

    [wsa: fixed spaces around operators]

    Signed-off-by: Wolfram Sang

    Sonic Zhang
     
  • In order to mark I2C transfer fail when MEN bit in I2C controller is
    reset unexpectedly in MCOMP interrupt, interrupt status bits XMTSERV or
    RCVSERV should be checked.

    Master Transfer Complete (MCOMP).
    [1] The initiated master transfer has completed. In the absence of a
    repeat start, the bus has been released.
    [0] The completion of a transfer has not been detected.

    Signed-off-by: Sonic Zhang

    [wsa: fixed spaces around operators and typo in commit message]

    Signed-off-by: Wolfram Sang

    Sonic Zhang
     
  • Some fault i2c device may hold the sda/scl line and cause i2c driver
    wait in the BUS busy loop. The I2C framework already retry the
    transfer loop before timeout. Return -EAGAIN instead of pull BUSBUSY
    in the other loop.

    Signed-off-by: Sonic Zhang
    Signed-off-by: Wolfram Sang

    Sonic Zhang
     
  • For transfer counts > 255 bytes i2c-bfin-twi sets the data
    transfer counter DCNT to 0xFF indicating unlimited transfers.
    It then uses a flag iface->manual_stop to manually issue the STOP
    condition, once the required amount of bytes are received.

    We found that on I2C receive operation issuing the STOP condition
    together with a FULL RCV FIFO (2bytes) will cause SDA and SCL be
    constantly driven low.

    This patch stops receiving operation immediately in last rx interrupt.
    This patch also wakes up waiting process when transfer completes.
    Signed-off-by: Sonic Zhang
    Signed-off-by: Wolfram Sang

    Sonic Zhang
     
  • For transfer counts > 255 bytes i2c-bfin-twi sets the data
    transfer counter DCNT to 0xFF indicating unlimited transfers.
    It then uses a flag iface->manual_stop to manually issue the STOP
    condition, once the required amount of bytes are received.

    We found that on I2C receive operation issuing the STOP condition
    together with a FULL RCV FIFO (2bytes) will cause SDA and SCL be
    constantly driven low.

    Temporary workaround until further investigation:
    Discard the RCV FIFO before issuing the STOP condition.

    Signed-off-by: Michael Hennerich
    Signed-off-by: Sonic Zhang
    Signed-off-by: Wolfram Sang

    Michael Hennerich
     

12 Jul, 2012

16 commits


10 Jul, 2012

1 commit

  • sparse found this assignment of u32 to an int. Fix it:

    drivers/i2c/busses/i2c-imx.c:540:56: warning: incorrect type in argument 3 (different signedness)

    and also fix the type in platform_data. All current users use values
    which fit into the old and new type, so it is a safe change.

    Signed-off-by: Wolfram Sang
    Reviewed-by: Richard Zhao
    Acked-by: Sascha Hauer

    Wolfram Sang
     

09 Jul, 2012

7 commits