12 Jun, 2012

1 commit

  • The fixups are executed once the pci-device is found which is during
    boot process so __init seems fine as long as the platform does not
    support hotplug.

    However it is possible to remove the PCI bus at run time and have it
    rediscovered again via "echo 1 > /sys/bus/pci/rescan" and this will call
    the fixups again.

    Cc: x86@kernel.org
    Signed-off-by: Sebastian Andrzej Siewior
    Signed-off-by: Bjorn Helgaas

    Sebastian Andrzej Siewior
     

06 Dec, 2011

1 commit


21 Jul, 2011

1 commit

  • This code uses PCI_CLASS_REVISION instead of PCI_REVISION_ID, so
    it wasn't converted by commit 44c10138fd4bbc ("PCI: Change all
    drivers to use pci_device->revision") before being moved to arch/x86/...

    Signed-off-by: Sergei Shtylyov
    Cc: Jesse Barnes
    Cc: Dave Jones
    Link: http://lkml.kernel.org/r/201107111901.39281.sshtylyov@ru.mvista.com
    Signed-off-by: Ingo Molnar

    Sergei Shtylyov
     

15 Sep, 2010

1 commit


15 Jul, 2010

1 commit

  • commit 30a564be (x86, hpet: Restrict read back to affected ATI
    chipset) restricted the workaround for the HPET bug to SMX00
    chipsets. This was reasonable as those were the only ones against
    which we ever got a bug report.

    Stephan Wolf reported now that this patch breaks his IXP400 based
    machine. Though it's confirmed to work on other IXP400 based systems.

    To error out on the safe side, we force the HPET readback workaround
    for all ATI SMbus class chipsets.

    Reported-by: Stephan Wolf
    LKML-Reference:
    Signed-off-by: Thomas Gleixner
    Tested-by: Stephan Wolf
    Acked-by: Borislav Petkov

    Thomas Gleixner
     

18 May, 2010

1 commit


29 Apr, 2010

1 commit

  • After programming the HPET, we do a readback as a workaround for
    ATI/SBx00 chipsets as a synchronization. Unfortunately this triggers
    an erratum in newer ICH chipsets (ICH9+) where reading the comparator
    immediately after the write returns the old value. Furthermore, as
    always, I/O reads are bad for performance.

    Therefore, restrict the readback to the chipsets that need it, or, for
    debugging purposes, when we are running with hpet=verbose.

    Signed-off-by: Thomas Gleixner
    Acked-by: Venkatesh Pallipadi
    LKML-Reference:
    Signed-off-by: H. Peter Anvin

    Thomas Gleixner
     

23 Jan, 2010

1 commit

  • HPET MSI on platforms with ATI SB700/SB800 as they seem to have some
    side-effects on floppy DMA. Do not use HPET MSI on such platforms.

    Original problem report from Mark Hounschell
    http://lkml.indiana.edu/hypermail/linux/kernel/0912.2/01118.html

    [ This patch needs to go to stable as well. But, there are some
    conflicts that prevents the patch from going as is. I can
    rebase/resubmit to stable once the patch goes upstream.
    hpa: still Cc:'ing stable@ as an FYI. ]

    Tested-by: Mark Hounschell
    Signed-off-by: Venkatesh Pallipadi
    Cc:
    LKML-Reference:
    Signed-off-by: H. Peter Anvin

    Pallipadi, Venkatesh
     

16 Nov, 2009

1 commit

  • Fix panic seen on some IBM and HP systems on 2.6.32-rc6:

    BUG: unable to handle kernel NULL pointer dereference at (null)
    IP: [] find_next_bit+0x77/0x9c
    [...]
    [] cpumask_next_and+0x2e/0x3b
    [] pci_device_probe+0x8e/0xf5
    [] ? driver_sysfs_add+0x47/0x6c
    [] driver_probe_device+0xd9/0x1f9
    [] __driver_attach+0x58/0x7c
    [] ? __driver_attach+0x0/0x7c
    [] bus_for_each_dev+0x54/0x89
    [] driver_attach+0x19/0x1b
    [] bus_add_driver+0xd3/0x23d
    [] driver_register+0x98/0x109
    [] __pci_register_driver+0x63/0xd3
    [] ? up_read+0x26/0x2a
    [] ? k8temp_init+0x0/0x20 [k8temp]
    [] k8temp_init+0x1e/0x20 [k8temp]
    [] do_one_initcall+0x6d/0x185
    [] sys_init_module+0xd3/0x236
    [] system_call_fastpath+0x16/0x1b

    I put in a printk and commented out the set_dev_node()
    call when and got this output:

    quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x0
    quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x1
    quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x2
    quirk_amd_nb_node: current numa_node = 0x0, would set to val & 7 = 0x3

    I.e. the issue appears to be that the HW has set val to a valid
    value, however, the system is only configured for a single
    node -- 0, the others are offline.

    Check to see if the node is actually online before setting
    the numa node for an AMD northbridge in quirk_amd_nb_node().

    Signed-off-by: Prarit Bhargava
    Cc: bhavna.sarathy@amd.com
    Cc: jbarnes@virtuousgeek.org
    Cc: andreas.herrmann3@amd.com
    LKML-Reference:
    [ v2: clean up the code and add comments ]
    Signed-off-by: Ingo Molnar

    Prarit Bhargava
     

10 Sep, 2009

1 commit


07 Jun, 2009

1 commit


24 Apr, 2009

1 commit

  • The HPET in the ICH4M is not documented in the data sheet
    because it was not officially validated.

    While it is fine for hackers to continue to use "hpet=force"
    to enable the hardware that they have, it is not prudent to
    solicit additional "hpet=force" users on this hardware.

    [ Impact: remove hpet=force syslog message on old-ICH systems ]

    Signed-off-by: Len Brown
    Acked-by: Venkatesh Pallipadi
    LKML-Reference:
    Signed-off-by: Ingo Molnar

    Len Brown
     

18 Apr, 2009

1 commit

  • Currently the numa_node attribute for these PCI devices is 0 (it
    corresponds to the numa_node for PCI bus 0). This is not a big issue
    but incorrect.

    This inconsistency can be fixed by reading the node number from CPU
    NB function 0.

    [ Impact: fill in dev->numa_node information, to optimize DMA allocations ]

    Signed-off-by: Andreas Herrmann
    Cc: jbarnes@virtuousgeek.org
    LKML-Reference:
    Signed-off-by: Ingo Molnar

    Andreas Herrmann
     

29 Mar, 2009

1 commit


10 Mar, 2009

1 commit


13 Jan, 2009

1 commit

  • Intel "Smackover" x58 BIOS don't have HPET enabled in the BIOS, so allow
    to force enable it at least. The register layout is the same as in other
    recent ICHs, so all the code can be reused.

    Using numerical PCI-ID because it's unlikely the PCI-ID will be used
    anywhere else.

    Signed-off-by: Andi Kleen
    Signed-off-by: Andrew Morton
    Signed-off-by: Ingo Molnar

    Andi Kleen
     

17 Dec, 2008

1 commit

  • Impact: auto-enable HPET on Fujitsu u9200

    HPET timer is listed in the ACPI table, but needs a quirk entry in order to
    work. Unfortunately, the quirk code runs after first HPET hpet_enable() which
    has already determined that the timer doesn't work (reads 0xFFFFFFFF). This
    patch allows hpet_enable() to be called again after running the quirk code.

    Signed-off-by: Janne Kulmala
    Signed-off-by: Ingo Molnar

    Janne Kulmala
     

16 Oct, 2008

1 commit


06 Sep, 2008

1 commit

  • The current quirk is incomplete. Some more chipset fiddling has to be
    done to enable HPET interrupts. This patch aims to do this. From my
    tests it seems to work faultlessly.

    But the official statement is that HPET is not supported on SB4X0.

    Users will still have to use hpet=force to enable it.

    Use it at your own risk.

    Signed-off-by: Andreas Herrmann
    Signed-off-by: Ingo Molnar

    Andreas Herrmann
     

16 Jul, 2008

1 commit

  • * 'timers/for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
    x86: add PCI ID for 6300ESB force hpet
    x86: add another PCI ID for ICH6 force-hpet
    kernel-paramaters: document pmtmr= command line option
    acpi_pm clccksource: fix printk format warning
    nohz: don't stop idle tick if softirqs are pending.
    pmtmr: allow command line override of ioport
    nohz: reduce jiffies polling overhead
    hrtimer: Remove unused variables in ktime_divns()
    hrtimer: remove warning in hres_timers_resume
    posix-timers: print RT watchdog message

    Linus Torvalds
     

14 Jul, 2008

2 commits

  • 00:1f.0 ISA bridge: Intel Corporation 6300ESB LPC Interface Controller (rev 02)
    00:1f.0 Class 0601: 8086:25a1 (rev 02)

    kernel: pci 0000:00:1f.0: Force enabled HPET at 0xfed00000
    kernel: hpet clockevent registered
    kernel: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
    kernel: hpet0: 3 64-bit timers, 14318180 Hz

    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Joe Buehler
     
  • Tested on Asus P5GDC-V

    $ lspci -n -n |grep ISA
    00:1f.0 ISA bridge [0601]: Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge [8086:2640] (rev 03)

    Force enabled HPET at base address 0xfed00000
    hpet clockevent registered
    hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
    hpet0: 3 64-bit timers, 14318180 Hz

    Signed-off-by: Krzysztof Piotr Oledzki
    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Krzysztof Oledzki
     

05 Jun, 2008

1 commit

  • Tested on Asus P5GDC-V

    $ lspci -n -n |grep ISA
    00:1f.0 ISA bridge [0601]: Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge [8086:2640] (rev 03)

    Force enabled HPET at base address 0xfed00000
    hpet clockevent registered
    hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
    hpet0: 3 64-bit timers, 14318180 Hz

    Signed-off-by: Krzysztof Piotr Oledzki
    Cc: mingo@elte.hu
    Signed-off-by: Thomas Gleixner

    Krzysztof Oledzki
     

13 May, 2008

2 commits

  • We have a lot of HPET quirks available which might force enable HPET
    even when the BIOS does not enable it. Some of those quirks depend on
    the command line option "hpet=force".

    Andrew pointed out that hoping that the user will find out about this
    boot option is not really helpful.

    Emit a kernel info which informs the user about the "hpet=force" boot
    option when we enter a quirk which depends on this option and the user
    did not provide it.

    Signed-off-by: Thomas Gleixner

    Thomas Gleixner
     
  • Add quirk to allow forced usage of HPET on ATI SB400.
    I stumbled over machines where HPET is enabled but not reported
    by BIOS. This patch configures the HPET base address and makes
    it known to the OS.

    Signed-off-by: Andreas Herrmann
    Signed-off-by: Thomas Gleixner

    Andreas Herrmann
     

22 Mar, 2008

1 commit

  • this patch allows hpet=force on nVidia nForce 430 southbridge.
    This patch was tested by me on my old Asus A8N-VM CSM (where bios does not
    support hpet and does not advertise it via acpi entry). My nForce430 version:
    lspci -nn | grep LPC
    00:0a.0 ISA bridge [0601]: nVidia Corporation MCP51 LPC Bridge [10de:0260]
    (rev a2)

    Kernel 2.6.24.3 after patching and using hpet=force reports this:
    dmesg | grep -i hpet
    Kernel command line: root=/dev/sda8 ro vga=773 video=vesafb:mtrr:4,ywrap
    vt.default_utf8=0 hpet=force
    Force enabled HPET at base address 0xfed00000
    hpet clockevent registered
    Time: hpet clocksource has been installed.

    grep -i hpet /proc/timer_list
    Clock Event Device: hpet
    set_next_event: hpet_legacy_next_event
    set_mode: hpet_legacy_set_mode

    grep Clock /proc/timer_list (before patching)
    Clock Event Device: pit
    Clock Event Device: lapic

    grep Clock /proc/timer_list (after patching)
    Clock Event Device: hpet
    Clock Event Device: lapic

    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Zbigniew Luszpinski
     

12 Feb, 2008

1 commit

  • Since we may not have a pci_dev for the device we need to access, we can't
    use pci_read_config_word. But raw_pci_read is an internal implementation
    detail; it's better to use the architected pci_bus_read_config_word
    interface. Using PCI_DEVFN instead of a mysterious constant helps
    reassure everyone that we really do intend to access device 8.

    [ Thanks to Grant Grundler for pointing out to me that this is exactly
    what the write immediately above this is doing -- enabling device 8 to
    respond to config space cycles.
    - Matthew

    Grant also says:

    "Can you also add a comment which points at the Intel
    documentation?

    The 'Intel E7320 Memory Controller Hub (MCH) Datasheet' at

    http://download.intel.com/design/chipsets/datashts/30300702.pdf

    Page 69 documents register F4h (DEVPRES1).

    And I just doubled checked that the 0xf4 register value is
    restored later in the quirk (obvious when you look at the code
    but not from the patch"

    so here it is.
    - Linus ]

    Signed-off-by: Matthew Wilcox
    Acked-by: Grant Grundler
    Signed-off-by: Linus Torvalds

    Matthew Wilcox
     

11 Feb, 2008

1 commit

  • We want to allow different implementations of pci_raw_ops for standard
    and extended config space on x86. Rather than clutter generic code with
    knowledge of this, we make pci_raw_ops private to x86 and use it to
    implement the new raw interface -- raw_pci_read() and raw_pci_write().

    Signed-off-by: Matthew Wilcox
    Signed-off-by: Linus Torvalds

    Matthew Wilcox
     

07 Feb, 2008

1 commit

  • arch/x86/kernel/quirks.c:384:3: warning: returning void-valued expression
    arch/x86/kernel/quirks.c:387:3: warning: returning void-valued expression
    arch/x86/kernel/quirks.c:390:3: warning: returning void-valued expression
    arch/x86/kernel/quirks.c:393:3: warning: returning void-valued expression

    Signed-off-by: Harvey Harrison
    Signed-off-by: Thomas Gleixner
    Signed-off-by: Ingo Molnar

    Harvey Harrison
     

02 Feb, 2008

1 commit


30 Jan, 2008

1 commit

  • Some consumer ICH9 boards (such as the Abit IP35 Pro) do not provide a BIOS
    option for enabling the HPET. The same ICH workaround used for 6,7,8 can be
    applied to 9. Here I enable the only PCI id that was visible on my system.

    I have confirmed the HPETs work both from userspace and as a clocksource for
    the running kernel (2.6.24 here) after applying this patch.

    Force enabled HPET at base address 0xfed00000
    hpet clockevent registered
    hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
    hpet0: 4 64-bit timers, 14318180 Hz

    Signed-off-by: Alistair John Strachan
    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Alistair John Strachan
     

24 Oct, 2007

2 commits

  • Add support to force_hpet for all known MCP55 (nForce 5) chipset
    LPC bridges.

    These are the untested nForce 5 chips (taken from Mikko's original
    patch, and checked against pci.ids).

    Signed-off-by: Carlos Corbacho
    Signed-off-by: Thomas Gleixner
    Signed-off-by: Ingo Molnar

    arch/x86/kernel/quirks.c | 18 ++++++++++++++++++
    1 file changed, 18 insertions(+)

    Carlos Corbacho
     
  • This patch adds a quirk from LinuxBIOS to force enable HPET on
    the nVidia CK804 (nForce 4) chipset.

    This quirk can very likely support more than just nForce 4
    (LinuxBIOS use the same code for nForce 5), and possibly nForce 3,
    but I don't have those chipsets, so cannot add and test them.

    Tested on an Abit KN9 (CK804).

    Signed-off-by: Carlos Corbacho
    Signed-off-by: Thomas Gleixner
    Signed-off-by: Ingo Molnar

    Documentation/kernel-parameters.txt | 3 +-
    arch/x86/kernel/quirks.c | 37 +++++++++++++++++++++++++++++++++++-
    2 files changed, 38 insertions(+), 2 deletions(-)

    Carlos Corbacho
     

20 Oct, 2007

3 commits

  • ICH3 and ICH4 have undocumented HPET capabilities. This patch enables
    HPET for platforms based around these ICHs.

    Tested on various ICH3 and ICH4 platforms.

    Because HPET is not officially documented for ICH3/4 and may not have
    been validated by chipset folks, we're on thin ice here. I'd recommend
    testing this patch in -hrt or -mm for a while and wait for
    success/failure reports before feeding it upstream.

    tglx: depends on the force_hpet command line option !

    Signed-off-by: Udo A. Steinberg
    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Udo A. Steinberg
     
  • This patch adds quirks to force enable HPET on Via VT8235 and
    VT8237 chipsets. The datasheet for 8237 documents HPET
    functionality (although wrongly) whereas HPET is undocumented
    for 8235.

    Tested on A7V880 (8237) and K7VT4A+ (8235) boards.

    tglx: depends on the force_hept commandline option

    Signed-off-by: Udo A. Steinberg
    Cc: Venkatesh Pallipadi
    Cc: Andi Kleen
    Cc: john stultz
    Cc: Greg KH
    Signed-off-by: Andrew Morton
    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Udo A. Steinberg
     
  • Signed-off-by: Thomas Gleixner
    Signed-off-by: Ingo Molnar

    Thomas Gleixner
     

13 Oct, 2007

4 commits

  • Add another PCI ID for ICH7 force hpet.

    Signed-off-by: Venkatesh Pallipadi
    Cc: Andi Kleen
    Cc: john stultz
    Cc: Greg KH
    Signed-off-by: Andrew Morton
    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner
    Signed-off-by: Arjan van de Ven

    Venki Pallipadi
     
  • A bugfix in ich5 hpet force detect which caused resumes to fail. Thanks to
    Udo A Steinberg for reporting the problem.

    Signed-off-by: Venkatesh Pallipadi
    Cc: Andi Kleen
    Cc: john stultz
    Cc: Greg KH
    Signed-off-by: Andrew Morton
    Signed-off-by: Ingo Molnar
    Signed-off-by: Arjan van de Ven
    Signed-off-by: Thomas Gleixner

    Venki Pallipadi
     
  • force_enable hpet for ICH5.

    [ Build fixes from Andrew Morton ]

    Signed-off-by: Venkatesh Pallipadi
    Cc: Andi Kleen
    Cc: john stultz
    Cc: Greg KH
    Signed-off-by: Andrew Morton
    Signed-off-by: Ingo Molnar
    Signed-off-by: Arjan van de Ven
    Signed-off-by: Thomas Gleixner

    Venki Pallipadi
     
  • Force detect and/or enable HPET on ICH chipsets. This patch just handles the
    detection part and following patches use this information. Adds a function to
    repeat the force enabling during resume time.

    Using HPET this way, instead of PIT increases the time CPUs can reside in
    C-state when system is totally idle. On my test system with Core 2 Duo,
    average C-state residency goes up from ~20mS to ~80mS.

    [ Build fixed from Andrew Morton ]

    Signed-off-by: Venkatesh Pallipadi
    Cc: Andi Kleen
    Cc: john stultz
    Cc: Greg KH
    Signed-off-by: Andrew Morton
    Signed-off-by: Ingo Molnar
    Signed-off-by: Arjan van de Ven
    Signed-off-by: Thomas Gleixner

    Venki Pallipadi