17 Dec, 2014
6 commits
-
SSI and SSI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.Signed-off-by: Shengjiu Wang
-
SAI and SAI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.Signed-off-by: Shengjiu Wang
-
The default setting of sai is RX sync with TX, TX output the I2S clock. So
When recording, we should set TCR2's divider, not RCR2's divider.Signed-off-by: Shengjiu Wang
-
The bclk caculation should according to the slot num, not the channels.
Because sometime we have two slots, but only one slot is enabled for mono
channel.
As when the codec wm8962 works on mono mode, it needs two slots I2S signal.
So here set the default slots of sai to 2, and add function set_tdm_slots for
future usage.Signed-off-by: Shengjiu Wang
-
The issue only can duplicate with PAL camera.
It is cause by vadc did not detect right video mode.
Add 0.5s delay before mode detect to resolved the issue.Signed-off-by: Sandor Yu
-
When the busfreq is in audio_bus_freq_mode, the AHB bus is at 8MHz,
in low_bus_freq_mode, the AHB needs to run at 24MHz. So when switching
from audio_bus_freq_mode to low_bus_freq_mode, make sure the AHB is at
24MHz in low_bus_freq_mode.Signed-off-by: Bai Ping
12 Dec, 2014
3 commits
-
The CAN transceiver on MX6SX Sabreauto board seems in sleep mode
by default after power up the board. User has to press the wakeup
key on ARD baseboard before using the transceiver, or it may not
work properly when power up the board at the first time(warm reset
does not have such issue).This patch wakeup the transceiver firstly if needed during intialization
by control the wakeup pin, then user do not have to press wakeup key
button to enable the transceiver.
BTW, stby gpio is also updated which is wrong before.Signed-off-by: Dong Aisheng
-
This property is used to wakeup transceiver if it's in
sleep mode.Signed-off-by: Dong Aisheng
-
1. Watermark level in sdma use byte as its unit. but asrc driver use
word, there is mismatch between them. Here fix this issue and sdma can
work more efficiency.
2. Enlarge the larst_period_size, when use small size, for some case,
the dma task will timeout, because sdma has no much data for output.Signed-off-by: Shengjiu Wang
11 Dec, 2014
2 commits
-
The kernel log is
[] (__dabt_svc+0x38/0x60) from [] (mutex_lock+0xc/0x4c)
[] (mutex_lock+0xc/0x4c) from [] (snd_soc_dapm_stream_event+0x20/0xe4)
[] (snd_soc_dapm_stream_event+0x20/0xe4) from [] (close_delayed_work+0x3c/0x48)
[] (close_delayed_work+0x3c/0x48) from [] (process_one_work+0xfc/0x34c)
[] (process_one_work+0xfc/0x34c) from [] (worker_thread+0x144/0x3a4)
[] (worker_thread+0x144/0x3a4) from [] (kthread+0xa4/0xb0)
[] (kthread+0xa4/0xb0) from [] (ret_from_fork+0x14/0x3c)The alsa driver use shedule_delayed_work when close pcm in remove module.
But after remove module the resource is released, so there will be kernel dump.
So here use ignore_pmdown_time to avoid to use shedule_delayed_work, then this
issue can be avoided.Signed-off-by: Shengjiu Wang
-
If vadc unit test abnormal exit, such as kill -9 pid,
next time run the unit test the image corrupted.In original implement, restore VADC specific register code in
streamoff function.
In specifical case, vadc unit test abnormal exit,
the code in streamoff function will been executed in the next run.
It is called from VIDIOC_REQBUFS.
So csi will lose vadc configuration, and image is corrupted.Move restore VADC specific register code from streamoff function
to device close function. Issue resolved.Signed-off-by: Sandor Yu
10 Dec, 2014
3 commits
-
NAND scans the bad blocks during kernel boots up, which invokes the
gpmi_ecc_read_oob function to check the badblock mark for each block. In
this function the oob data was raw read from NAND chip without ECC, so
it hardly to guarantee the consistency of the data considering the
possible bitflips. It found that in some MLC NAND the oob data changed
and consequently the BBT changed in different power cycles. This issue
may cause the UBIFS mount failed.To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT
in NAND flash. On the first time kernel boot up, all bad blocks and
probably some fake bad block would be recognized and be recorded in
on-nand bad block table. From the second time boot, kernel will read BBT
from NAND Flash rather than calling gpmi_ecc_read_oob function to check
bad block.No bad block would be missed when create BBT since the probability that
16bit bad block mark filps from 0x00 to 0xFF is extremely low.Signed-off-by: Allen Xu
(cherry picked from commit d957353768a1b6d39b340b9d10b22fc42b0aa8e2) -
stream off should be called by pxp_close when stream is on.
Signed-off-by: Liu Xiaowen
(cherry picked from commit 481208f831519db30b3e33ddabefdd1fc66417d9) -
use the string "okay" instead to enable backlight
Signed-off-by: Robby Cai
(cherry picked from commit 5468fd8a98086ec68347f92c4a525ea4c1b71c5f)
09 Dec, 2014
1 commit
-
The reproduce step:
$ echo 8 > /proc/sys/kernel/printk
$ echo 1 > /sys/class/graphics/fb0/blank
$ ifconfig eth0 down
$ ifconfig eth1 down
$ cat /sys/kernel/debug/clk/osc/pll2_bus/pll2_pfd2_396m/periph2_pre/periph2/mmdc_podf/clk_rate
396000000The expected result should be '24000000' and following message.
Bus freq set to 24000000 start...
Bus freq set to 24000000 done!This patch did the following to fix it.
- Move the pm runtime handling into csi v4l2 driver, request high bus frequency
when the device opens and release high bus frequency when device closes.
- Add new api csisw_reset() to mainly do DMA reflash otherwise potentially
meet garbage data when CSI starts to work on imx6sl.Signed-off-by: Robby Cai
(cherry picked from commit 857a52585c92cad8d851751f859e8e23ea4ae250)
06 Dec, 2014
2 commits
-
Add more CAAM era values to the CAAM driver's caam_get_era()
function. Read only 32 bits of data since the data required
to identify the IP_ID and MAJ_REV is located in the first 32
bits of the register. And, update the function for use with
ARM/Little Endian devices.Signed-off-by: Victoria Milhoan
(cherry picked from commit 6050d7faf2d0c063195aa9454c130548a9f8058f) -
The caam_get_jrdev() function is no longer needed. The
caam_jr_alloc() function is used instead to allocate a job
ring device from the CAAM driver.Signed-off-by: Victoria Milhoan
(cherry picked from commit bae574f498f4928ee5a42abeb419b045af5e1d91)
05 Dec, 2014
1 commit
-
The branch determined by GPMI_IS_MX6SX() should not include
acquire_dma_channels() function which causes unbalanced dma
request/release on other platform.Removed GPMI_IS_MX6SX() to make code simple although it is not necessary
to restore GPMI/BCH registers for i.MX6Q/DLSigned-off-by: Allen Xu
(cherry picked from commit 54cd0fe03180dc44e3783bca1546e61d698abd2f)
04 Dec, 2014
3 commits
-
Update the i.MX6DL cpu operating points to comply with the latest
published datasheet. Latest i.MX6DL datasheet of Rev.4, 10/2014
updates the 396MHz setpoint's min voltage from 1.075V to 1.125V, Add a
25mV margin to cover the board IR drop, here use 1.15V for 396MHz to
match datasheet.Signed-off-by: Bai Ping
-
If QSPI probe failed in some cases, such as board rework, the error
patch was not handled correctly.This issue may cause kernle dump in fec driver, since the
pm_qos_remove_request() in QSPI driver was not invoked when probe
failed.Signed-off-by: Allen Xu
(cherry picked from commit 350d532e0266a0a6918cbc6a17952ef64aef2521) -
Add the ddrsmp parameter for 19x19 arm2 board.
2 ---- i.MX6SX 19x19 ARM2 boardAnd reduce the clock frequency from 53Mhz to 29Mhz.
Signed-off-by: Allen Xu
(cherry picked from commit 44a1d6c7b438fa1139572e864ee6aa111de39f18)
01 Dec, 2014
7 commits
-
The new property "ddrsmp" was added into device tree. Update the doc
accordingly.Signed-off-by: Ye.Li
(cherry picked from commit 4239df12c5d6c3ac19a25e120ffe17df93c358a3) -
The ddr sample point is board related, so add ddrsmp parameter to device
tree for i.MX6SX 17x17 ARM2 board.DDRSMP value:
2 ---- i.MX6SX 17x17 ARM2 boardSigned-off-by: Allen Xu
(cherry picked from commit c5d9eb443cda0c4d6e5705a2b51904f49b4f8297) -
QSPI1 cannot wake up CCM from WAIT mode on SX ARD board, add pmqos to
let CCM NOT enter WAIT mode when accessing QSPI1, refer to TKT245618.Signed-off-by: Allen Xu
(cherry picked from commit feb3b71bffc8afd440c0b972334f2479ebfefa1d) -
Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for i.MX6SX Sabreauto/Sabresd board.DDRSMP value:
0 ---- i.MX6SX Sabresd board (RevB and RevA)
2 ---- i.MX6SX Sabreauto boardThe Sabresd RevA board also needs to reduce clock to 29Mhz according to
the Spansion spec.Signed-off-by: Ye.Li
(cherry picked from commit c9115cc22d836b5b980ca20932a005ea61b20082) -
By default, job ring 0 is the owner of the Secure Memory area
within CAAM. This patch modifies the Secure Memory module to
use job ring 0 for all accesses.Signed-off-by: Victoria Milhoan
(cherry picked from commit bb447bfb241d34492365bf881257b1a742a29c02) -
imx_clk_gate2_flags() uses CGR value 2b'11, while imx_clk_gate()
use CGR value 2b'01. We need 2b'11 which means "clock is on during
all modes, except STOP mode".Signed-off-by: Robby Cai
(cherry picked from commit 51841a54f6746ce06b16a3297014069a2b3b97c2) -
Previously PWM3 is always enabled even when the LCDIF1 is not used.
This is not correct, since the default DTS file enables CSI while
disable LCDIF1 due to pin conflict between CSI and LCDIF1 on imx6sx-sdb board.This patch fixed it.
Signed-off-by: Robby Cai
(cherry picked from commit f77c15ccab9e8a68870048d4964b2dd15b3d4c0c)
29 Nov, 2014
3 commits
-
We meet below oops at rare cases when we do g_serial test at SMP platform,
in our cases, the g_serial will be removed after some access.
It seems the tty still tries to write when the port is freed.Unable to handle kernel NULL pointer dereference at virtual address 000000b0
pgd = 80004000
[000000b0] *pgd=00000000
Internal error: Oops: 17 1 PREEMPT SMP ARM
Modules linked in: usb_f_acm u_serial g_serial libcomposite configfs ov5642_camera ov5640_camera_mipi ov5640_camera mxc_dcic mxc_v4l2_capture ipu_bg_overlay_sdc ipu_still ipu_prp_enc ipu_csi_enc ipu_fg_overlay_sdc evbug
CPU: 0 PID: 25 Comm: kworker/0:1 Not tainted 3.10.53-02612-g3ac9b04-dirty #210
Workqueue: events flush_to_ldisc
task: a80ae580 ti: a80e8000 task.ti: a80e8000
PC is at _raw_spin_lock_irqsave+0x18/0x58
LR is at _raw_spin_lock_irqsave+0x18/0x58
pc : [] lr : [] psr: 800f0093
sp : a80e9da0 ip : 00000001 fp : a8d97c00
r10: a8d97e88 r9 : a8d97c00 r8 : 0000000d
r7 : 0000006c r6 : a8da7400 r5 : 200f0013 r4 : 000000b0
r3 : a80e8000 r2 : 00000000 r1 : a8d97c00 r0 : 00000001
Flags: Nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 38cf404a DAC: 00000015
Process kworker/0:1 (pid: 25, stack limit = 0xa80e8238)
Stack: (0xa80e9da0 to 0xa80ea000)
9da0: 7f095a30 00000000 000000b0 7f095a44 a8da7400 a8d95d1f a8da7400 802d8484
9dc0: a80ae580 802d5ab0 a83a2500 a8d97e70 a8d97c00 a8da7400 a8d95d1f a8d95c1f
9de0: 0000006c 0000000d a8d97c00 00000000 a8d97c00 802d7010 a8044080 00000000
9e00: 00000000 80cc00c0 806ae500 00000000 00000000 00000002 00000000 815977d0
9e20: 00000000 00000000 00000020 00000000 80cbcc40 a8044080 ffffbe45 00000000
9e40: 00000001 81598c40 00000000 806848b8 80009038 ffffffff 00000000 8004e7c8
9e60: 80cbe000 00000002 a80e9e8c 80684b9c 00000000 80051a10 a805c780 80cbcc40
9e80: a805c780 80cbcc40 a80e9f2c 80683850 81598840 8068490c 00000000 80cceed4
9ea0: 00000000 8004e744 81598840 a8ae5400 a8da7400 a8ae5410 a93a7940 a8ae5464
9ec0: a8d95d1c 0000000f a8d95c1c 802db1f4 802db118 a8105980 a8ae5400 81598840
9ee0: 8159ba00 00000000 00000000 a80e8038 81598840 800436d4 a8105998 a80e8000
9f00: a80e8030 00000001 a80e8000 a8105980 81598854 a8105998 a80e8000 a80e8030
9f20: 00000001 a80e8000 81598840 80044358 80044220 00000000 00000000 80d15701
9f40: a80e9f64 a808fe98 00000000 a8105980 80044220 00000000 00000000 00000000
9f60: 00000000 80049730 fcbb7bfd 00000000 ffdfdbfb a8105980 00000000 00000000
9f80: a80e9f80 a80e9f80 00000000 00000000 a80e9f90 a80e9f90 a80e9fac a808fe98
9fa0: 8004967c 00000000 00000000 8000e118 00000000 00000000 00000000 00000000
9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 32fdff6f 9355fcea
[] (_raw_spin_lock_irqsave+0x18/0x58) from [] (gs_write_room+0x14/0x60 [u_serial])
[] (gs_write_room+0x14/0x60 [u_serial]) from [] (tty_write_room+0x18/0x24)
[] (tty_write_room+0x18/0x24) from [] (process_echoes+0x48/0x2a8)
[] (process_echoes+0x48/0x2a8) from [] (n_tty_receive_buf+0x384/0x101c)
[] (n_tty_receive_buf+0x384/0x101c) from [] (flush_to_ldisc+0xdc/0x140)
[] (flush_to_ldisc+0xdc/0x140) from [] (process_one_work+0xf8/0x360)
[] (process_one_work+0xf8/0x360) from [] (worker_thread+0x138/0x3d4)
[] (worker_thread+0x138/0x3d4) from [] (kthread+0xb4/0xb8)
[] (kthread+0xb4/0xb8) from [] (ret_from_fork+0x14/0x3c)
Code: e10f5000 f10c0080 e3a00001 ebe735b3 (e1943f9f)
--[ end trace b1a6974fbb8c89dc ]--Signed-off-by: Peter Chen
-
We meet below oops at rare cases when we do g_serial test at SMP platform,
in our cases, the g_serial will be removed after some access.
gserial_disconnect may be called before the complete handler is called,
in this case, the port->port_usb is NULL at gs_start_tx, it matches
the below oops.PC is at gs_start_tx+0x20/0x22c [u_serial]
LR is at gs_write_complete+0x60/0x88 [u_serial]
pc : [] lr : [] psr: 600e0193
sp : a83adc10 ip : 00000002 fp : a8849f80
r10: a803d64c r9 : a87dfeec r8 : a8849fbc
r7 : a803d64c r6 : a87dfeb0 r5 : a8849f80 r4 : a87dfe00
r3 : 00000000 r2 : 00000100 r1 : a8849c24 r0 : a87dfe00
Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 38e0404a DAC: 00000015
Process kworker/0:2 (pid: 105, stack limit = 0xa83ac238)
Stack: (0xa83adc10 to 0xa83ae000)
dc00: 81299260 a87dfeb0 00000002 a803d64c
dc20: a8849f80 a87dfe00 a8849f80 a87dfeb0 a803d64c a8849fbc 00000002 a803d64c
dc40: a8849f80 7f095894 a8849fb4 00000002 a8849fbc a8849fbc a803d6a4 803ed524
dc60: a8849fb4 a8849680 00000009 00000001 80cc64e4 a803d010 a803d014 a803d684
dc80: a803d64c 00000009 803ec908 a803d170 00100000 38a9ea00 80d15d88 a803d010
dca0: a8009958 00000000 00000000 0000004b a8009900 80d1574f 00000001 803ea2f4
dcc0: 803ea2a4 a83cd140 a8009958 80079ab4 a8849b00 a8849b00 a95f9fc0 a8009900
dce0: a8009958 a83cd140 f4a00100 80bafa3c a8807000 a8807288 a8807000 80079c18
dd00: a8009900 a8009958 00000000 8007c948 8007c8c4 0000004b 0000004b 8007927c
dd20: 80cbbf00 8000e948 f4a0010c 80cc6914 a83add50 80008558 7f095ca0 8068484c
dd40: 400e0013 ffffffff a83add84 8000dc80 a87dfeb0 200e0013 a83add60 0000a556
dd60: a87dfe00 00000002 a87dfeb0 200e0013 80bafa3c a8807000 a8807288 a8807000
dd80: a8991d44 a83add98 7f095ca0 8068484c 400e0013 ffffffff 00000000 7f095ca0
dda0: a8808000 00000001 a8991c00 00001fff a8809000 802d59b0 00000a00 a8808000
ddc0: 00000001 802d5bec a83addf4 a8807270 00000000 a8991c00 a96bf562 a96bf462
dde0: 0000000a 000000bb a8807000 00000000 a8807000 802d7b64 80d1574f 400e0013
de00: a88072a0 80cc00c0 806ae500 a8009900 a8009958 a83cd140 f4a00100 a87dfe64
de20: a91c481c 806845b8 a8009900 80079c24 80cbbf00 0000004b 600e0193 800815c0
de40: 80cbbf00 0000004b 00000000 f4a00100 a87dfe64 8000e94c f4a0010c 80cc6914
de60: a83ade80 80008558 802db1d8 8068484c 800e0013 ffffffff a83adeb4 8000dc80
de80: a87dfe10 200e0013 00000000 00003193 a87dfe00 a8991c00 a87dfe10 a8faa500
dea0: a87dfe64 a91c491c 00000100 a87dfe00 a8991c00 a87dfe10 a8faa500 a87dfe64
dec0: a96bf51c 00000100 a96bf41c 802db1f4 802db118 a820e600 a87dfe00 81597840
dee0: 8159aa00 00000000 00000000 a83ac038 81597840 800436d4 a820e600 81597854
df00: a820e618 a83ac000 a83ac030 a820e600 81597854 a820e618 a83ac000 a83ac030
df20: 00000001 a83ac000 81597840 8004446c 80044220 00000000 00000000 80d15701
df40: a83adf64 a808fe98 00000000 a820e600 80044220 00000000 00000000 00000000
df60: 00000000 80049730 7cff2e7d 00000000 27dddefd a820e600 00000000 00000000
df80: a83adf80 a83adf80 00000000 00000000 a83adf90 a83adf90 a83adfac a808fe98
dfa0: 8004967c 00000000 00000000 8000e118 00000000 00000000 00000000 00000000
dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 e4b9dbff e5bdd7ff
[] (gs_start_tx+0x20/0x22c [u_serial]) from [] (gs_write_complete+0x60/0x88 [u_serial])
[] (gs_write_complete+0x60/0x88 [u_serial]) from [] (udc_irq+0x478/0xd20)
[] (udc_irq+0x478/0xd20) from [] (ci_irq+0x50/0x118)
[] (ci_irq+0x50/0x118) from [] (handle_irq_event_percpu+0x54/0x17c)
[] (handle_irq_event_percpu+0x54/0x17c) from [] (handle_irq_event+0x3c/0x5c)
[] (handle_irq_event+0x3c/0x5c) from [] (handle_fasteoi_irq+0x84/0x14c)
[] (handle_fasteoi_irq+0x84/0x14c) from [] (generic_handle_irq+0x2c/0x3c)
[] (generic_handle_irq+0x2c/0x3c) from [] (handle_IRQ+0x40/0x90)
[] (handle_IRQ+0x40/0x90) from [] (gic_handle_irq+0x2c/0x5c)
[] (gic_handle_irq+0x2c/0x5c) from [] (__irq_svc+0x40/0x70)
Exception stack(0xa83add50 to 0xa83add98)
dd40: a87dfeb0 200e0013 a83add60 0000a556
dd60: a87dfe00 00000002 a87dfeb0 200e0013 80bafa3c a8807000 a8807288 a8807000
dd80: a8991d44 a83add98 7f095ca0 8068484c 400e0013 ffffffff
[] (__irq_svc+0x40/0x70) from [] (_raw_spin_unlock_irqrestore+0x20/0x48)
[] (_raw_spin_unlock_irqrestore+0x20/0x48) from [] (gs_write+0x48/0x68 [u_serial])
[] (gs_write+0x48/0x68 [u_serial]) from [] (do_output_char+0x148/0x1b8)
[] (do_output_char+0x148/0x1b8) from [] (process_echoes+0x184/0x2a8)
[] (process_echoes+0x184/0x2a8) from [] (n_tty_receive_buf+0xed8/0x101c)
[] (n_tty_receive_buf+0xed8/0x101c) from [] (flush_to_ldisc+0xdc/0x140)
[] (flush_to_ldisc+0xdc/0x140) from [] (process_one_work+0xf8/0x360)
[] (process_one_work+0xf8/0x360) from [] (worker_thread+0x24c/0x3d4)
[] (worker_thread+0x24c/0x3d4) from [] (kthread+0xb4/0xb8)
[] (kthread+0xb4/0xb8) from [] (ret_from_fork+0x14/0x3c)
Code: e1a04000 e28020b0 e58d2004 e3a02c01 (e593705c)Signed-off-by: Peter Chen
-
If system is in audio busfreq mode, when entering low power idle, set the MMDC podf
to 8 for power saving. Before exiting low power idle, the PODF value need to be restored
to the original value.Signed-off-by: Bai Ping
28 Nov, 2014
7 commits
-
If the controller is powered down, it may not pull down dp and dm any more,
so the status of dp and dm is unknown, it will confuse the device.So for controllers which will power off its controller, we need to
override pulldown feature, and pull down dp and dm by software
before the sytem enters suspend, and disable override feature after
system resume.Besides, it fixes issue that the low speed device will be disconnected
after system resume when the controller is powered off during system
suspend.Signed-off-by: Peter Chen
-
The user can override controller's behavior for 15K pulldown resistor
with this API.Signed-off-by: Peter Chen
-
This API is used for platforms (may be specific for mxs PHY) which can
pull down 15K resistor when necessarySigned-off-by: Peter Chen
-
M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;Signed-off-by: Anson Huang
-
As M4's clk switch MUX is NOT a glitchless one, when M4 try to
switch its parent, it needs to be gated, so M4 can NOT switch its
parent by itself, need A9 to help do it.Have to remove M4 from shared memory, it means M4's clk will be
managed by A9 completely.Signed-off-by: Anson Huang
-
For AVB 1722 non-canonical packet that don't define in linux networking,
we inserts VLAN tag for application to think it as VLAN packet.(cherry-picked from commit: 6a156113269dd133ac6361dcfe8fd390cdae1e5e)
Signed-off-by: Fugang Duan
-
For DCIC module all lcdif data and signal pins
should configuration to SION(Software Input On Field)
to enable loopback mode.
But the pin of LCD1_RESET not required,
so remove SION setting otherwise imx6sx sdb board can not
resume from power suspend.Signed-off-by: Sandor Yu
(cherry picked from commit ada39ddc49f527672281e510abe06d3f40559383)
27 Nov, 2014
1 commit
-
Add HW VLAN ctag check for VLAN hw acceleration.
(cherry-picked from commit: 47828ce6f54d78f173e405d732b358362aa8dd51)
Signed-off-by: Fugang Duan
26 Nov, 2014
1 commit
-
i.MX6SX-AI board has two enet MACs (MAC0 and MAC1), they share MAC0 MII
bus. When PHY0 don't connect to enet MAC0, MAC0 mii bus probe phy0 failed,
and the net interface is set to unattach mode. During suspend resume test,
driver don't reinit MAC0 after resume back, so MII bus don't work that causes
MAC1 also cannot access PHY1.The patch just is workaround that reinit MAC0 MII bus for MAC1 using.
(cherry-picked from commit: 8ab1562923ef47d523e76db06af0aa3e704c5316)
Signed-off-by: Fugang Duan